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Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.

This commit is contained in:
Simon Pilgrim 2021-08-26 13:15:29 +01:00
parent 379b6394d9
commit 47f2affa08
1 changed files with 2 additions and 2 deletions
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4
llvm/lib/Target/X86/X86MCInstLower.cpp
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@ -1341,7 +1341,7 @@ void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
if (!Sym) { if (!Sym) {
std::string Name = AccessInfo.IsWrite ? "store" : "load"; std::string Name = AccessInfo.IsWrite ? "store" : "load";
std::string SymName = "__asan_check_" + Name + std::string SymName = "__asan_check_" + Name +
utostr(1 << AccessInfo.AccessSizeIndex) + "_rn" + utostr(1ULL << AccessInfo.AccessSizeIndex) + "_rn" +
utostr(Reg); utostr(Reg);
Sym = OutContext.getOrCreateSymbol(SymName); Sym = OutContext.getOrCreateSymbol(SymName);
} }
@ -1519,7 +1519,7 @@ void X86AsmPrinter::emitAsanReportError(Module &M, unsigned Reg,
MCSubtargetInfo &STI) { MCSubtargetInfo &STI) {
std::string Name = AccessInfo.IsWrite ? "store" : "load"; std::string Name = AccessInfo.IsWrite ? "store" : "load";
MCSymbol *ReportError = OutContext.getOrCreateSymbol( MCSymbol *ReportError = OutContext.getOrCreateSymbol(
"__asan_report_" + Name + utostr(1 << AccessInfo.AccessSizeIndex)); "__asan_report_" + Name + utostr(1ULL << AccessInfo.AccessSizeIndex));
OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr) OutStreamer->emitInstruction(MCInstBuilder(X86::MOV64rr)
.addReg(X86::RDI) .addReg(X86::RDI)
.addReg(X86::NoRegister + Reg), .addReg(X86::NoRegister + Reg),