forked from OSchip/llvm-project
Fix printing of immediate operands by looking at their operand types in
the TargetInstrInfo. This fixes UnitTests 2003-05-26-Shorts and 2003-07-09-LoadShorts. llvm-svn: 15296
This commit is contained in:
Misha Brukman
parent
92ca8eccd8
commit
47d5a22f8b
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@ -75,6 +75,7 @@ namespace {
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void printMachineInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
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void printImmOp(const MachineOperand &MO, unsigned ArgType);
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void printConstantPool(MachineConstantPool *MCP);
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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@ -419,13 +420,11 @@ void Printer::printOp(const MachineOperand &MO,
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return;
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case MachineOperand::MO_SignExtendedImmed:
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O << (short)MO.getImmedValue();
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case MachineOperand::MO_UnextendedImmed:
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std::cerr << "printOp() does not handle immediate values\n";
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abort();
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return;
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case MachineOperand::MO_UnextendedImmed:
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O << (unsigned short)MO.getImmedValue();
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return;
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case MachineOperand::MO_PCRelativeDisp:
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std::cerr << "Shouldn't use addPCDisp() when building PPC MachineInstrs";
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abort();
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@ -479,6 +478,17 @@ void Printer::printOp(const MachineOperand &MO,
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}
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}
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void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
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int Imm = MO.getImmedValue();
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if (ArgType == PPC32II::Simm16 || ArgType == PPC32II::Disimm16) {
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O << (short)Imm;
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} else if (ArgType == PPC32II::Zimm16) {
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O << (unsigned short)Imm;
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} else {
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O << Imm;
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}
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}
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/// printMachineInstruction -- Print out a single PPC32 LLVM instruction
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/// MI in Darwin syntax to the current output stream.
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///
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@ -486,11 +496,10 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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unsigned Opcode = MI->getOpcode();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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unsigned int i;
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unsigned i;
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unsigned int ArgCount = MI->getNumOperands();
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//Desc.TSFlags & PPC32II::ArgCountMask;
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unsigned int ArgType[] = {
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unsigned ArgCount = MI->getNumOperands();
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unsigned ArgType[] = {
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(Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
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(Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
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(Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask,
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@ -516,15 +525,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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O << "\n";
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return;
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} else if (Opcode == PPC32::CALLpcrel) {
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O << TII.getName(MI->getOpcode()) << " ";
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O << TII.getName(Opcode) << " ";
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printOp(MI->getOperand(0));
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O << "\n";
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return;
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} else if (Opcode == PPC32::CALLindirect) {
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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O << TII.getName(Opcode) << " ";
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printImmOp(MI->getOperand(0), ArgType[0]);
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O << ", ";
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printOp(MI->getOperand(1));
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printImmOp(MI->getOperand(1), ArgType[0]);
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O << "\n";
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return;
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} else if (Opcode == PPC32::MovePCtoLR) {
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@ -537,7 +546,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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return;
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}
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O << TII.getName(MI->getOpcode()) << " ";
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O << TII.getName(Opcode) << " ";
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if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) {
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printOp(MI->getOperand(0));
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O << ", lo16(";
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@ -562,7 +571,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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} else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) {
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printOp(MI->getOperand(0));
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O << ", ";
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printOp(MI->getOperand(1));
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printImmOp(MI->getOperand(1), ArgType[1]);
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O << "(";
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if (MI->getOperand(2).hasAllocatedReg() &&
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MI->getOperand(2).getReg() == PPC32::R0)
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@ -584,6 +593,8 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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assert(8 == MI->getOperand(i).getImmedValue()
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&& "branch off PC not to pc+8?");
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//printOp(MI->getOperand(i));
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} else if (MI->getOperand(i).isImmediate()) {
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printImmOp(MI->getOperand(i), ArgType[i]);
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} else {
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printOp(MI->getOperand(i));
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}
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@ -75,6 +75,7 @@ namespace {
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void printMachineInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
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void printImmOp(const MachineOperand &MO, unsigned ArgType);
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void printConstantPool(MachineConstantPool *MCP);
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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@ -419,13 +420,11 @@ void Printer::printOp(const MachineOperand &MO,
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return;
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case MachineOperand::MO_SignExtendedImmed:
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O << (short)MO.getImmedValue();
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case MachineOperand::MO_UnextendedImmed:
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std::cerr << "printOp() does not handle immediate values\n";
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abort();
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return;
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case MachineOperand::MO_UnextendedImmed:
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O << (unsigned short)MO.getImmedValue();
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return;
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case MachineOperand::MO_PCRelativeDisp:
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std::cerr << "Shouldn't use addPCDisp() when building PPC MachineInstrs";
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abort();
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@ -479,6 +478,17 @@ void Printer::printOp(const MachineOperand &MO,
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}
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}
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void Printer::printImmOp(const MachineOperand &MO, unsigned ArgType) {
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int Imm = MO.getImmedValue();
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if (ArgType == PPC32II::Simm16 || ArgType == PPC32II::Disimm16) {
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O << (short)Imm;
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} else if (ArgType == PPC32II::Zimm16) {
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O << (unsigned short)Imm;
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} else {
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O << Imm;
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}
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}
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/// printMachineInstruction -- Print out a single PPC32 LLVM instruction
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/// MI in Darwin syntax to the current output stream.
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///
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@ -486,11 +496,10 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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unsigned Opcode = MI->getOpcode();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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unsigned int i;
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unsigned i;
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unsigned int ArgCount = MI->getNumOperands();
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//Desc.TSFlags & PPC32II::ArgCountMask;
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unsigned int ArgType[] = {
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unsigned ArgCount = MI->getNumOperands();
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unsigned ArgType[] = {
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(Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
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(Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
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(Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask,
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@ -516,15 +525,15 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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O << "\n";
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return;
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} else if (Opcode == PPC32::CALLpcrel) {
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O << TII.getName(MI->getOpcode()) << " ";
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O << TII.getName(Opcode) << " ";
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printOp(MI->getOperand(0));
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O << "\n";
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return;
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} else if (Opcode == PPC32::CALLindirect) {
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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O << TII.getName(Opcode) << " ";
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printImmOp(MI->getOperand(0), ArgType[0]);
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O << ", ";
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printOp(MI->getOperand(1));
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printImmOp(MI->getOperand(1), ArgType[0]);
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O << "\n";
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return;
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} else if (Opcode == PPC32::MovePCtoLR) {
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@ -537,7 +546,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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return;
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}
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O << TII.getName(MI->getOpcode()) << " ";
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O << TII.getName(Opcode) << " ";
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if (Opcode == PPC32::LOADLoDirect || Opcode == PPC32::LOADLoIndirect) {
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printOp(MI->getOperand(0));
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O << ", lo16(";
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@ -562,7 +571,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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} else if (ArgCount == 3 && ArgType[1] == PPC32II::Disimm16) {
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printOp(MI->getOperand(0));
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O << ", ";
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printOp(MI->getOperand(1));
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printImmOp(MI->getOperand(1), ArgType[1]);
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O << "(";
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if (MI->getOperand(2).hasAllocatedReg() &&
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MI->getOperand(2).getReg() == PPC32::R0)
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@ -584,6 +593,8 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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assert(8 == MI->getOperand(i).getImmedValue()
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&& "branch off PC not to pc+8?");
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//printOp(MI->getOperand(i));
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} else if (MI->getOperand(i).isImmediate()) {
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printImmOp(MI->getOperand(i), ArgType[i]);
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} else {
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printOp(MI->getOperand(i));
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}
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