forked from OSchip/llvm-project
[X86] Move the information about the feature bits used by compiler-rt and shared by Host.cpp to a .def file and TargetParser.h so clang can make use of it.
Since we keep Host.cpp and compiler-rt relatively in sync, clang can use this information as a proxy. llvm-svn: 318814
This commit is contained in:
Craig Topper
parent
21fadadbf3
commit
47c8739b08
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@ -244,6 +244,15 @@ enum ProcessorSubtypes : unsigned {
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CPU_SUBTYPE_MAX
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};
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// This should be kept in sync with libcc/compiler-rt as it should be used
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// by clang as a proxy for what's in libgcc/compiler-rt.
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enum ProcessorFeatures {
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#define X86_FEATURE(VAL, ENUM) \
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ENUM = VAL,
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#include "llvm/Support/X86TargetParser.def"
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};
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} // namespace X86
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} // namespace llvm
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@ -104,3 +104,52 @@ X86_CPU_SUBTYPE ("k6-3", AMDPENTIUM_K63)
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X86_CPU_SUBTYPE ("geode", AMDPENTIUM_GEODE)
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#undef X86_CPU_SUBTYPE_COMPAT
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#undef X86_CPU_SUBTYPE
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// This macro is used for cpu types present in compiler-rt/libgcc.
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#ifndef X86_FEATURE_COMPAT
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#define X86_FEATURE_COMPAT(VAL, ENUM, STR) X86_FEATURE(VAL, ENUM)
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#endif
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#ifndef X86_FEATURE
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#define X86_FEATURE(VAL, ENUM)
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#endif
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X86_FEATURE_COMPAT( 0, FEATURE_CMOV, "cmov")
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X86_FEATURE_COMPAT( 1, FEATURE_MMX, "mmx")
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X86_FEATURE_COMPAT( 2, FEATURE_POPCNT, "popcnt")
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X86_FEATURE_COMPAT( 3, FEATURE_SSE, "sse")
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X86_FEATURE_COMPAT( 4, FEATURE_SSE2, "sse2")
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X86_FEATURE_COMPAT( 5, FEATURE_SSE3, "sse3")
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X86_FEATURE_COMPAT( 6, FEATURE_SSSE3, "ssse3")
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X86_FEATURE_COMPAT( 7, FEATURE_SSE4_1, "sse4.1")
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X86_FEATURE_COMPAT( 8, FEATURE_SSE4_2, "sse4.2")
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X86_FEATURE_COMPAT( 9, FEATURE_AVX, "avx")
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X86_FEATURE_COMPAT(10, FEATURE_AVX2, "avx2")
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X86_FEATURE_COMPAT(11, FEATURE_SSE4_A, "sse4a")
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X86_FEATURE_COMPAT(12, FEATURE_FMA4, "fma4")
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X86_FEATURE_COMPAT(13, FEATURE_XOP, "xop")
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X86_FEATURE_COMPAT(14, FEATURE_FMA, "fma")
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X86_FEATURE_COMPAT(15, FEATURE_AVX512F, "avx512f")
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X86_FEATURE_COMPAT(16, FEATURE_BMI, "bmi")
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X86_FEATURE_COMPAT(17, FEATURE_BMI2, "bmi2")
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X86_FEATURE_COMPAT(18, FEATURE_AES, "aes")
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X86_FEATURE_COMPAT(19, FEATURE_PCLMUL, "pclmul")
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X86_FEATURE_COMPAT(20, FEATURE_AVX512VL, "avx512vl")
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X86_FEATURE_COMPAT(21, FEATURE_AVX512BW, "avx512bw")
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X86_FEATURE_COMPAT(22, FEATURE_AVX512DQ, "avx512dq")
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X86_FEATURE_COMPAT(23, FEATURE_AVX512CD, "avx512cd")
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X86_FEATURE_COMPAT(24, FEATURE_AVX512ER, "avx512er")
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X86_FEATURE_COMPAT(25, FEATURE_AVX512PF, "avx512pf")
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X86_FEATURE_COMPAT(26, FEATURE_AVX512VBMI, "avx512vbmi")
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X86_FEATURE_COMPAT(27, FEATURE_AVX512IFMA, "avx512ifma")
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X86_FEATURE_COMPAT(28, FEATURE_AVX5124VNNIW, "avx5124vnniw")
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X86_FEATURE_COMPAT(29, FEATURE_AVX5124FMAPS, "avx5124fmaps")
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X86_FEATURE_COMPAT(30, FEATURE_AVX512VPOPCNTDQ, "avx512vpopcntdq")
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// Features below here are not in libgcc/compiler-rt.
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X86_FEATURE (32, FEATURE_MOVBE)
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X86_FEATURE (33, FEATURE_ADX)
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X86_FEATURE (34, FEATURE_EM64T)
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X86_FEATURE (35, FEATURE_CLFLUSHOPT)
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X86_FEATURE (36, FEATURE_SHA)
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#undef X86_FEATURE_COMPAT
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#undef X86_FEATURE
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@ -322,49 +322,6 @@ enum VendorSignatures {
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SIG_AMD = 0x68747541 /* Auth */
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};
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// This should be kept in sync with libcc/compiler-rt as it should be used
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// by clang as a proxy for what's in libgcc/compiler-rt.
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enum ProcessorFeatures {
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FEATURE_CMOV = 0,
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FEATURE_MMX,
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FEATURE_POPCNT,
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FEATURE_SSE,
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FEATURE_SSE2,
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FEATURE_SSE3,
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FEATURE_SSSE3,
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FEATURE_SSE4_1,
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FEATURE_SSE4_2,
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FEATURE_AVX,
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FEATURE_AVX2,
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FEATURE_SSE4_A,
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FEATURE_FMA4,
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FEATURE_XOP,
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FEATURE_FMA,
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FEATURE_AVX512F,
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FEATURE_BMI,
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FEATURE_BMI2,
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FEATURE_AES,
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FEATURE_PCLMUL,
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FEATURE_AVX512VL,
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FEATURE_AVX512BW,
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FEATURE_AVX512DQ,
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FEATURE_AVX512CD,
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FEATURE_AVX512ER,
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FEATURE_AVX512PF,
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FEATURE_AVX512VBMI,
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FEATURE_AVX512IFMA,
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FEATURE_AVX5124VNNIW,
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FEATURE_AVX5124FMAPS,
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FEATURE_AVX512VPOPCNTDQ,
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// One bit free here.
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// Features below here are not in libgcc/compiler-rt.
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FEATURE_MOVBE = 32,
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FEATURE_ADX,
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FEATURE_EM64T,
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FEATURE_CLFLUSHOPT,
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FEATURE_SHA,
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};
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// The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
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// Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
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// support. Consequently, for i386, the presence of CPUID is checked first
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@ -523,7 +480,7 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
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*Type = X86::INTEL_i486;
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break;
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case 5:
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if (Features & (1 << FEATURE_MMX)) {
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if (Features & (1 << X86::FEATURE_MMX)) {
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*Type = X86::INTEL_PENTIUM_MMX;
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break;
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}
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@ -677,25 +634,25 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
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break;
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default: // Unknown family 6 CPU, try to guess.
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if (Features & (1 << FEATURE_AVX512VBMI)) {
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if (Features & (1 << X86::FEATURE_AVX512VBMI)) {
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*Type = X86::INTEL_COREI7;
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*Subtype = X86::INTEL_COREI7_CANNONLAKE;
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break;
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}
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if (Features & (1 << FEATURE_AVX512VL)) {
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if (Features & (1 << X86::FEATURE_AVX512VL)) {
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*Type = X86::INTEL_COREI7;
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*Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
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break;
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}
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if (Features & (1 << FEATURE_AVX512ER)) {
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if (Features & (1 << X86::FEATURE_AVX512ER)) {
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*Type = X86::INTEL_KNL; // knl
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break;
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}
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if (Features2 & (1 << (FEATURE_CLFLUSHOPT - 32))) {
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if (Features2 & (1 << (FEATURE_SHA - 32))) {
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if (Features2 & (1 << (X86::FEATURE_CLFLUSHOPT - 32))) {
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if (Features2 & (1 << (X86::FEATURE_SHA - 32))) {
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*Type = X86::INTEL_GOLDMONT;
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} else {
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*Type = X86::INTEL_COREI7;
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@ -703,23 +660,23 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
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}
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break;
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}
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if (Features2 & (1 << (FEATURE_ADX - 32))) {
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if (Features2 & (1 << (X86::FEATURE_ADX - 32))) {
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*Type = X86::INTEL_COREI7;
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*Subtype = X86::INTEL_COREI7_BROADWELL;
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break;
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}
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if (Features & (1 << FEATURE_AVX2)) {
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if (Features & (1 << X86::FEATURE_AVX2)) {
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*Type = X86::INTEL_COREI7;
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*Subtype = X86::INTEL_COREI7_HASWELL;
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break;
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}
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if (Features & (1 << FEATURE_AVX)) {
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if (Features & (1 << X86::FEATURE_AVX)) {
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*Type = X86::INTEL_COREI7;
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*Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
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break;
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}
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if (Features & (1 << FEATURE_SSE4_2)) {
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if (Features2 & (1 << (FEATURE_MOVBE - 32))) {
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if (Features & (1 << X86::FEATURE_SSE4_2)) {
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if (Features2 & (1 << (X86::FEATURE_MOVBE - 32))) {
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*Type = X86::INTEL_SILVERMONT;
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} else {
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*Type = X86::INTEL_COREI7;
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@ -727,13 +684,13 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
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}
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break;
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}
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if (Features & (1 << FEATURE_SSE4_1)) {
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if (Features & (1 << X86::FEATURE_SSE4_1)) {
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*Type = X86::INTEL_CORE2; // "penryn"
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*Subtype = X86::INTEL_CORE2_45;
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break;
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}
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if (Features & (1 << FEATURE_SSSE3)) {
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if (Features2 & (1 << (FEATURE_MOVBE - 32))) {
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if (Features & (1 << X86::FEATURE_SSSE3)) {
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if (Features2 & (1 << (X86::FEATURE_MOVBE - 32))) {
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*Type = X86::INTEL_BONNELL; // "bonnell"
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} else {
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*Type = X86::INTEL_CORE2; // "core2"
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@ -741,24 +698,24 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
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}
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break;
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}
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if (Features2 & (1 << (FEATURE_EM64T - 32))) {
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if (Features2 & (1 << (X86::FEATURE_EM64T - 32))) {
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*Type = X86::INTEL_CORE2; // "core2"
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*Subtype = X86::INTEL_CORE2_65;
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break;
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}
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if (Features & (1 << FEATURE_SSE3)) {
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if (Features & (1 << X86::FEATURE_SSE3)) {
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*Type = X86::INTEL_CORE_DUO;
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break;
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}
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if (Features & (1 << FEATURE_SSE2)) {
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if (Features & (1 << X86::FEATURE_SSE2)) {
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*Type = X86::INTEL_PENTIUM_M;
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break;
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}
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if (Features & (1 << FEATURE_SSE)) {
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if (Features & (1 << X86::FEATURE_SSE)) {
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*Type = X86::INTEL_PENTIUM_III;
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break;
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}
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if (Features & (1 << FEATURE_MMX)) {
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if (Features & (1 << X86::FEATURE_MMX)) {
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*Type = X86::INTEL_PENTIUM_II;
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break;
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}
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@ -767,11 +724,11 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
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}
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break;
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case 15: {
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if (Features2 & (1 << (FEATURE_EM64T - 32))) {
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if (Features2 & (1 << (X86::FEATURE_EM64T - 32))) {
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*Type = X86::INTEL_NOCONA;
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break;
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}
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if (Features & (1 << FEATURE_SSE3)) {
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if (Features & (1 << X86::FEATURE_SSE3)) {
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*Type = X86::INTEL_PRESCOTT;
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break;
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}
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@ -813,14 +770,14 @@ static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
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}
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break;
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case 6:
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if (Features & (1 << FEATURE_SSE)) {
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if (Features & (1 << X86::FEATURE_SSE)) {
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*Type = X86::AMD_ATHLON_XP;
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break; // "athlon-xp"
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}
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*Type = X86::AMD_ATHLON;
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break; // "athlon"
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case 15:
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if (Features & (1 << FEATURE_SSE3)) {
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if (Features & (1 << X86::FEATURE_SSE3)) {
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*Type = X86::AMD_K8SSE3;
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break; // "k8-sse3"
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}
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@ -882,33 +839,33 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
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unsigned EAX, EBX;
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if ((EDX >> 15) & 1)
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Features |= 1 << FEATURE_CMOV;
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Features |= 1 << X86::FEATURE_CMOV;
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if ((EDX >> 23) & 1)
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Features |= 1 << FEATURE_MMX;
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Features |= 1 << X86::FEATURE_MMX;
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if ((EDX >> 25) & 1)
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Features |= 1 << FEATURE_SSE;
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Features |= 1 << X86::FEATURE_SSE;
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if ((EDX >> 26) & 1)
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Features |= 1 << FEATURE_SSE2;
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Features |= 1 << X86::FEATURE_SSE2;
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if ((ECX >> 0) & 1)
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Features |= 1 << FEATURE_SSE3;
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Features |= 1 << X86::FEATURE_SSE3;
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if ((ECX >> 1) & 1)
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Features |= 1 << FEATURE_PCLMUL;
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Features |= 1 << X86::FEATURE_PCLMUL;
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if ((ECX >> 9) & 1)
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Features |= 1 << FEATURE_SSSE3;
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Features |= 1 << X86::FEATURE_SSSE3;
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if ((ECX >> 12) & 1)
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Features |= 1 << FEATURE_FMA;
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Features |= 1 << X86::FEATURE_FMA;
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if ((ECX >> 19) & 1)
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Features |= 1 << FEATURE_SSE4_1;
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Features |= 1 << X86::FEATURE_SSE4_1;
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if ((ECX >> 20) & 1)
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Features |= 1 << FEATURE_SSE4_2;
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Features |= 1 << X86::FEATURE_SSE4_2;
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if ((ECX >> 23) & 1)
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Features |= 1 << FEATURE_POPCNT;
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Features |= 1 << X86::FEATURE_POPCNT;
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if ((ECX >> 25) & 1)
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Features |= 1 << FEATURE_AES;
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Features |= 1 << X86::FEATURE_AES;
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if ((ECX >> 22) & 1)
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Features2 |= 1 << (FEATURE_MOVBE - 32);
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Features2 |= 1 << (X86::FEATURE_MOVBE - 32);
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// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
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// indicates that the AVX registers will be saved and restored on context
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@ -919,49 +876,49 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
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bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
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if (HasAVX)
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Features |= 1 << FEATURE_AVX;
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Features |= 1 << X86::FEATURE_AVX;
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bool HasLeaf7 =
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MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
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if (HasLeaf7 && ((EBX >> 3) & 1))
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Features |= 1 << FEATURE_BMI;
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Features |= 1 << X86::FEATURE_BMI;
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if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
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Features |= 1 << FEATURE_AVX2;
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Features |= 1 << X86::FEATURE_AVX2;
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if (HasLeaf7 && ((EBX >> 9) & 1))
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Features |= 1 << FEATURE_BMI2;
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Features |= 1 << X86::FEATURE_BMI2;
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if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX512F;
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Features |= 1 << X86::FEATURE_AVX512F;
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if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX512DQ;
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Features |= 1 << X86::FEATURE_AVX512DQ;
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if (HasLeaf7 && ((EBX >> 19) & 1))
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Features2 |= 1 << (FEATURE_ADX - 32);
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Features2 |= 1 << (X86::FEATURE_ADX - 32);
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if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX512IFMA;
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Features |= 1 << X86::FEATURE_AVX512IFMA;
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if (HasLeaf7 && ((EBX >> 23) & 1))
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Features2 |= 1 << (FEATURE_CLFLUSHOPT - 32);
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Features2 |= 1 << (X86::FEATURE_CLFLUSHOPT - 32);
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if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX512PF;
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Features |= 1 << X86::FEATURE_AVX512PF;
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if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX512ER;
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Features |= 1 << X86::FEATURE_AVX512ER;
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if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX512CD;
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Features |= 1 << X86::FEATURE_AVX512CD;
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if (HasLeaf7 && ((EBX >> 29) & 1))
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Features2 |= 1 << (FEATURE_SHA - 32);
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Features2 |= 1 << (X86::FEATURE_SHA - 32);
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if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX512BW;
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Features |= 1 << X86::FEATURE_AVX512BW;
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if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX512VL;
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Features |= 1 << X86::FEATURE_AVX512VL;
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if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX512VBMI;
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Features |= 1 << X86::FEATURE_AVX512VBMI;
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if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX512VPOPCNTDQ;
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Features |= 1 << X86::FEATURE_AVX512VPOPCNTDQ;
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if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
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Features |= 1 << FEATURE_AVX5124VNNIW;
|
||||
Features |= 1 << X86::FEATURE_AVX5124VNNIW;
|
||||
if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
|
||||
Features |= 1 << FEATURE_AVX5124FMAPS;
|
||||
Features |= 1 << X86::FEATURE_AVX5124FMAPS;
|
||||
|
||||
unsigned MaxExtLevel;
|
||||
getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
|
||||
|
|
@ -969,14 +926,14 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
|
|||
bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
|
||||
!getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
|
||||
if (HasExtLeaf1 && ((ECX >> 6) & 1))
|
||||
Features |= 1 << FEATURE_SSE4_A;
|
||||
Features |= 1 << X86::FEATURE_SSE4_A;
|
||||
if (HasExtLeaf1 && ((ECX >> 11) & 1))
|
||||
Features |= 1 << FEATURE_XOP;
|
||||
Features |= 1 << X86::FEATURE_XOP;
|
||||
if (HasExtLeaf1 && ((ECX >> 16) & 1))
|
||||
Features |= 1 << FEATURE_FMA4;
|
||||
Features |= 1 << X86::FEATURE_FMA4;
|
||||
|
||||
if (HasExtLeaf1 && ((EDX >> 29) & 1))
|
||||
Features2 |= 1 << (FEATURE_EM64T - 32);
|
||||
Features2 |= 1 << (X86::FEATURE_EM64T - 32);
|
||||
|
||||
*FeaturesOut = Features;
|
||||
*Features2Out = Features2;
|
||||
|
|
|
|||
Loading…
Reference in New Issue