forked from OSchip/llvm-project
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
Prior to this patch, libcalls inserted by the SelectionDAG legalizer could never be tailcalled. The eligibility of libcalls for tail calling is is partly determined by checking TargetLowering::isInTailCallPosition and comparing the return type of the libcall and the calleer. isInTailCallPosition in turn calls TargetLowering::isUsedByReturnOnly (which always returns false if not implemented by the target). This patch provides a minimal implementation of TargetLowering::isUsedByReturnOnly - enough to support tail calling libcalls on hard float ABIs. Soft-float ABIs are left for a follow on patch. libcall-tail-calls.ll also shows missed opportunities to tail call integer libcalls, but this is due to issues outside of the isUsedByReturnOnly hook. Differential Revision: https://reviews.llvm.org/D131087
This commit is contained in:
Alex Bradbury
parent
8d6f61b6ad
commit
47b1f8362a
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@ -11812,6 +11812,40 @@ void RISCVTargetLowering::validateCCReservedRegs(
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F, "Argument register required, but has been reserved."});
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}
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// Check if the result of the node is only used as a return value, as
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// otherwise we can't perform a tail-call.
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bool RISCVTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
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if (N->getNumValues() != 1)
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return false;
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if (!N->hasNUsesOfValue(1, 0))
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return false;
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SDNode *Copy = *N->use_begin();
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// TODO: Handle additional opcodes in order to support tail-calling libcalls
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// with soft float ABIs.
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if (Copy->getOpcode() != ISD::CopyToReg) {
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return false;
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}
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// If the ISD::CopyToReg has a glue operand, we conservatively assume it
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// isn't safe to perform a tail call.
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if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() == MVT::Glue)
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return false;
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// The copy must be used by a RISCVISD::RET_FLAG, and nothing else.
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bool HasRet = false;
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for (SDNode *Node : Copy->uses()) {
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if (Node->getOpcode() != RISCVISD::RET_FLAG)
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return false;
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HasRet = true;
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}
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if (!HasRet)
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return false;
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Chain = Copy->getOperand(0);
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return true;
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}
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bool RISCVTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
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return CI->isTailCall();
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}
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@ -528,6 +528,7 @@ public:
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override;
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bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
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bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
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bool shouldConsiderGEPOffsetSplit() const override { return true; }
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@ -11,12 +11,7 @@
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define i32 @udiv(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: udiv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __udivsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: tail __udivsi3@plt
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;
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; RV32IM-LABEL: udiv:
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; RV32IM: # %bb.0:
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@ -47,13 +42,8 @@ define i32 @udiv(i32 %a, i32 %b) nounwind {
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define i32 @udiv_constant(i32 %a) nounwind {
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; RV32I-LABEL: udiv_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: li a1, 5
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; RV32I-NEXT: call __udivsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: tail __udivsi3@plt
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;
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; RV32IM-LABEL: udiv_constant:
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; RV32IM: # %bb.0:
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@ -115,14 +105,9 @@ define i32 @udiv_pow2(i32 %a) nounwind {
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define i32 @udiv_constant_lhs(i32 %a) nounwind {
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; RV32I-LABEL: udiv_constant_lhs:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: li a0, 10
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; RV32I-NEXT: call __udivsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: tail __udivsi3@plt
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;
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; RV32IM-LABEL: udiv_constant_lhs:
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; RV32IM: # %bb.0:
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@ -172,12 +157,7 @@ define i64 @udiv64(i64 %a, i64 %b) nounwind {
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;
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; RV64I-LABEL: udiv64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __udivdi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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; RV64I-NEXT: tail __udivdi3@plt
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;
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; RV64IM-LABEL: udiv64:
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; RV64IM: # %bb.0:
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@ -212,13 +192,8 @@ define i64 @udiv64_constant(i64 %a) nounwind {
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;
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; RV64I-LABEL: udiv64_constant:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: li a1, 5
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; RV64I-NEXT: call __udivdi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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; RV64I-NEXT: tail __udivdi3@plt
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;
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; RV64IM-LABEL: udiv64_constant:
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; RV64IM: # %bb.0:
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@ -260,14 +235,9 @@ define i64 @udiv64_constant_lhs(i64 %a) nounwind {
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;
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; RV64I-LABEL: udiv64_constant_lhs:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: mv a1, a0
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; RV64I-NEXT: li a0, 10
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; RV64I-NEXT: call __udivdi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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; RV64I-NEXT: tail __udivdi3@plt
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;
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; RV64IM-LABEL: udiv64_constant_lhs:
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; RV64IM: # %bb.0:
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@ -596,12 +566,7 @@ define i16 @udiv16_constant_lhs(i16 %a) nounwind {
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define i32 @sdiv(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sdiv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: call __divsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: tail __divsi3@plt
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;
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; RV32IM-LABEL: sdiv:
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; RV32IM: # %bb.0:
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@ -630,13 +595,8 @@ define i32 @sdiv(i32 %a, i32 %b) nounwind {
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define i32 @sdiv_constant(i32 %a) nounwind {
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; RV32I-LABEL: sdiv_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: li a1, 5
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; RV32I-NEXT: call __divsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: tail __divsi3@plt
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;
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; RV32IM-LABEL: sdiv_constant:
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; RV32IM: # %bb.0:
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@ -748,14 +708,9 @@ define i32 @sdiv_pow2_2(i32 %a) nounwind {
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define i32 @sdiv_constant_lhs(i32 %a) nounwind {
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; RV32I-LABEL: sdiv_constant_lhs:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: li a0, -10
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; RV32I-NEXT: call __divsi3@plt
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: tail __divsi3@plt
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;
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; RV32IM-LABEL: sdiv_constant_lhs:
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; RV32IM: # %bb.0:
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@ -804,12 +759,7 @@ define i64 @sdiv64(i64 %a, i64 %b) nounwind {
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;
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; RV64I-LABEL: sdiv64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __divdi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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; RV64I-NEXT: tail __divdi3@plt
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;
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; RV64IM-LABEL: sdiv64:
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; RV64IM: # %bb.0:
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@ -844,13 +794,8 @@ define i64 @sdiv64_constant(i64 %a) nounwind {
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;
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; RV64I-LABEL: sdiv64_constant:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: li a1, 5
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; RV64I-NEXT: call __divdi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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; RV64I-NEXT: tail __divdi3@plt
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;
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; RV64IM-LABEL: sdiv64_constant:
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; RV64IM: # %bb.0:
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@ -894,14 +839,9 @@ define i64 @sdiv64_constant_lhs(i64 %a) nounwind {
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;
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; RV64I-LABEL: sdiv64_constant_lhs:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: mv a1, a0
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; RV64I-NEXT: li a0, 10
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; RV64I-NEXT: call __divdi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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; RV64I-NEXT: tail __divdi3@plt
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;
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; RV64IM-LABEL: sdiv64_constant_lhs:
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; RV64IM: # %bb.0:
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@ -942,14 +882,9 @@ define i64 @sdiv64_sext_operands(i32 %a, i32 %b) nounwind {
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;
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; RV64I-LABEL: sdiv64_sext_operands:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: call __divdi3@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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; RV64I-NEXT: tail __divdi3@plt
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;
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; RV64IM-LABEL: sdiv64_sext_operands:
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; RV64IM: # %bb.0:
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@ -7,21 +7,11 @@
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define double @frem_f64(double %a, double %b) nounwind {
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; RV32IFD-LABEL: frem_f64:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IFD-NEXT: call fmod@plt
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; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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; RV32IFD-NEXT: tail fmod@plt
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;
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; RV64IFD-LABEL: frem_f64:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: addi sp, sp, -16
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; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IFD-NEXT: call fmod@plt
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; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IFD-NEXT: addi sp, sp, 16
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; RV64IFD-NEXT: ret
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; RV64IFD-NEXT: tail fmod@plt
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%1 = frem double %a, %b
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ret double %1
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}
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@ -44,12 +44,7 @@ declare double @llvm.powi.f64.i32(double, i32)
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define double @powi_f64(double %a, i32 %b) nounwind {
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; RV32IFD-LABEL: powi_f64:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IFD-NEXT: call __powidf2@plt
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; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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; RV32IFD-NEXT: tail __powidf2@plt
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;
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; RV64IFD-LABEL: powi_f64:
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; RV64IFD: # %bb.0:
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@ -86,23 +81,9 @@ define double @powi_f64(double %a, i32 %b) nounwind {
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declare double @llvm.sin.f64(double)
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define double @sin_f64(double %a) nounwind {
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; RV32IFD-LABEL: sin_f64:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IFD-NEXT: call sin@plt
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; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: sin_f64:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: addi sp, sp, -16
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; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IFD-NEXT: call sin@plt
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; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IFD-NEXT: addi sp, sp, 16
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; RV64IFD-NEXT: ret
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; CHECKIFD-LABEL: sin_f64:
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; CHECKIFD: # %bb.0:
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; CHECKIFD-NEXT: tail sin@plt
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;
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; RV32I-LABEL: sin_f64:
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; RV32I: # %bb.0:
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@ -128,23 +109,9 @@ define double @sin_f64(double %a) nounwind {
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declare double @llvm.cos.f64(double)
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define double @cos_f64(double %a) nounwind {
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; RV32IFD-LABEL: cos_f64:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IFD-NEXT: call cos@plt
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; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: cos_f64:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: addi sp, sp, -16
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; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IFD-NEXT: call cos@plt
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; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IFD-NEXT: addi sp, sp, 16
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; RV64IFD-NEXT: ret
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; CHECKIFD-LABEL: cos_f64:
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; CHECKIFD: # %bb.0:
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; CHECKIFD-NEXT: tail cos@plt
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;
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; RV32I-LABEL: cos_f64:
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; RV32I: # %bb.0:
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@ -262,23 +229,9 @@ define double @sincos_f64(double %a) nounwind {
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declare double @llvm.pow.f64(double, double)
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define double @pow_f64(double %a, double %b) nounwind {
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; RV32IFD-LABEL: pow_f64:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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||||
; RV32IFD-NEXT: call pow@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: pow_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call pow@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: pow_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail pow@plt
|
||||
;
|
||||
; RV32I-LABEL: pow_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -304,23 +257,9 @@ define double @pow_f64(double %a, double %b) nounwind {
|
|||
declare double @llvm.exp.f64(double)
|
||||
|
||||
define double @exp_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: exp_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call exp@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: exp_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call exp@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: exp_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail exp@plt
|
||||
;
|
||||
; RV32I-LABEL: exp_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -346,23 +285,9 @@ define double @exp_f64(double %a) nounwind {
|
|||
declare double @llvm.exp2.f64(double)
|
||||
|
||||
define double @exp2_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: exp2_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call exp2@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: exp2_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call exp2@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: exp2_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail exp2@plt
|
||||
;
|
||||
; RV32I-LABEL: exp2_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -388,23 +313,9 @@ define double @exp2_f64(double %a) nounwind {
|
|||
declare double @llvm.log.f64(double)
|
||||
|
||||
define double @log_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: log_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call log@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: log_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call log@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: log_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail log@plt
|
||||
;
|
||||
; RV32I-LABEL: log_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -430,23 +341,9 @@ define double @log_f64(double %a) nounwind {
|
|||
declare double @llvm.log10.f64(double)
|
||||
|
||||
define double @log10_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: log10_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call log10@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: log10_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call log10@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: log10_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail log10@plt
|
||||
;
|
||||
; RV32I-LABEL: log10_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -472,23 +369,9 @@ define double @log10_f64(double %a) nounwind {
|
|||
declare double @llvm.log2.f64(double)
|
||||
|
||||
define double @log2_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: log2_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call log2@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: log2_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call log2@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: log2_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail log2@plt
|
||||
;
|
||||
; RV32I-LABEL: log2_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -713,23 +596,9 @@ define double @copysign_f64(double %a, double %b) nounwind {
|
|||
declare double @llvm.floor.f64(double)
|
||||
|
||||
define double @floor_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: floor_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call floor@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: floor_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call floor@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: floor_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail floor@plt
|
||||
;
|
||||
; RV32I-LABEL: floor_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -755,23 +624,9 @@ define double @floor_f64(double %a) nounwind {
|
|||
declare double @llvm.ceil.f64(double)
|
||||
|
||||
define double @ceil_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: ceil_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call ceil@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: ceil_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call ceil@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: ceil_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail ceil@plt
|
||||
;
|
||||
; RV32I-LABEL: ceil_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -797,23 +652,9 @@ define double @ceil_f64(double %a) nounwind {
|
|||
declare double @llvm.trunc.f64(double)
|
||||
|
||||
define double @trunc_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: trunc_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call trunc@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: trunc_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call trunc@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: trunc_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail trunc@plt
|
||||
;
|
||||
; RV32I-LABEL: trunc_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -839,23 +680,9 @@ define double @trunc_f64(double %a) nounwind {
|
|||
declare double @llvm.rint.f64(double)
|
||||
|
||||
define double @rint_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: rint_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call rint@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: rint_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call rint@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: rint_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail rint@plt
|
||||
;
|
||||
; RV32I-LABEL: rint_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -881,23 +708,9 @@ define double @rint_f64(double %a) nounwind {
|
|||
declare double @llvm.nearbyint.f64(double)
|
||||
|
||||
define double @nearbyint_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: nearbyint_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call nearbyint@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: nearbyint_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call nearbyint@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: nearbyint_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail nearbyint@plt
|
||||
;
|
||||
; RV32I-LABEL: nearbyint_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -923,23 +736,9 @@ define double @nearbyint_f64(double %a) nounwind {
|
|||
declare double @llvm.round.f64(double)
|
||||
|
||||
define double @round_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: round_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call round@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: round_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call round@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: round_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail round@plt
|
||||
;
|
||||
; RV32I-LABEL: round_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -965,23 +764,9 @@ define double @round_f64(double %a) nounwind {
|
|||
declare double @llvm.roundeven.f64(double)
|
||||
|
||||
define double @roundeven_f64(double %a) nounwind {
|
||||
; RV32IFD-LABEL: roundeven_f64:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: call roundeven@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: roundeven_f64:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: call roundeven@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: roundeven_f64:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail roundeven@plt
|
||||
;
|
||||
; RV32I-LABEL: roundeven_f64:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
|
|||
|
|
@ -625,131 +625,41 @@ define i64 @test_roundeven_ui64(double %x) {
|
|||
}
|
||||
|
||||
define double @test_floor_double(double %x) {
|
||||
; RV32IFD-LABEL: test_floor_double:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: .cfi_offset ra, -4
|
||||
; RV32IFD-NEXT: call floor@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: test_floor_double:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: .cfi_offset ra, -8
|
||||
; RV64IFD-NEXT: call floor@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: test_floor_double:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail floor@plt
|
||||
%a = call double @llvm.floor.f64(double %x)
|
||||
ret double %a
|
||||
}
|
||||
|
||||
define double @test_ceil_double(double %x) {
|
||||
; RV32IFD-LABEL: test_ceil_double:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: .cfi_offset ra, -4
|
||||
; RV32IFD-NEXT: call ceil@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: test_ceil_double:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: .cfi_offset ra, -8
|
||||
; RV64IFD-NEXT: call ceil@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: test_ceil_double:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail ceil@plt
|
||||
%a = call double @llvm.ceil.f64(double %x)
|
||||
ret double %a
|
||||
}
|
||||
|
||||
define double @test_trunc_double(double %x) {
|
||||
; RV32IFD-LABEL: test_trunc_double:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: .cfi_offset ra, -4
|
||||
; RV32IFD-NEXT: call trunc@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: test_trunc_double:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: .cfi_offset ra, -8
|
||||
; RV64IFD-NEXT: call trunc@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: test_trunc_double:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail trunc@plt
|
||||
%a = call double @llvm.trunc.f64(double %x)
|
||||
ret double %a
|
||||
}
|
||||
|
||||
define double @test_round_double(double %x) {
|
||||
; RV32IFD-LABEL: test_round_double:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: .cfi_offset ra, -4
|
||||
; RV32IFD-NEXT: call round@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: test_round_double:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: .cfi_offset ra, -8
|
||||
; RV64IFD-NEXT: call round@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: test_round_double:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail round@plt
|
||||
%a = call double @llvm.round.f64(double %x)
|
||||
ret double %a
|
||||
}
|
||||
|
||||
define double @test_roundeven_double(double %x) {
|
||||
; RV32IFD-LABEL: test_roundeven_double:
|
||||
; RV32IFD: # %bb.0:
|
||||
; RV32IFD-NEXT: addi sp, sp, -16
|
||||
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IFD-NEXT: .cfi_offset ra, -4
|
||||
; RV32IFD-NEXT: call roundeven@plt
|
||||
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IFD-NEXT: addi sp, sp, 16
|
||||
; RV32IFD-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LABEL: test_roundeven_double:
|
||||
; RV64IFD: # %bb.0:
|
||||
; RV64IFD-NEXT: addi sp, sp, -16
|
||||
; RV64IFD-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IFD-NEXT: .cfi_offset ra, -8
|
||||
; RV64IFD-NEXT: call roundeven@plt
|
||||
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IFD-NEXT: addi sp, sp, 16
|
||||
; RV64IFD-NEXT: ret
|
||||
; CHECKIFD-LABEL: test_roundeven_double:
|
||||
; CHECKIFD: # %bb.0:
|
||||
; CHECKIFD-NEXT: tail roundeven@plt
|
||||
%a = call double @llvm.roundeven.f64(double %x)
|
||||
ret double %a
|
||||
}
|
||||
|
|
|
|||
|
|
@ -55,12 +55,7 @@ declare float @llvm.powi.f32.i32(float, i32)
|
|||
define float @powi_f32(float %a, i32 %b) nounwind {
|
||||
; RV32IF-LABEL: powi_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call __powisf2@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail __powisf2@plt
|
||||
;
|
||||
; RV64IF-LABEL: powi_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
|
|
@ -99,21 +94,11 @@ declare float @llvm.sin.f32(float)
|
|||
define float @sin_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: sin_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call sinf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail sinf@plt
|
||||
;
|
||||
; RV64IF-LABEL: sin_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call sinf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail sinf@plt
|
||||
;
|
||||
; RV32I-LABEL: sin_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -141,21 +126,11 @@ declare float @llvm.cos.f32(float)
|
|||
define float @cos_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: cos_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call cosf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail cosf@plt
|
||||
;
|
||||
; RV64IF-LABEL: cos_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call cosf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail cosf@plt
|
||||
;
|
||||
; RV32I-LABEL: cos_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -248,21 +223,11 @@ declare float @llvm.pow.f32(float, float)
|
|||
define float @pow_f32(float %a, float %b) nounwind {
|
||||
; RV32IF-LABEL: pow_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call powf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail powf@plt
|
||||
;
|
||||
; RV64IF-LABEL: pow_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call powf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail powf@plt
|
||||
;
|
||||
; RV32I-LABEL: pow_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -290,21 +255,11 @@ declare float @llvm.exp.f32(float)
|
|||
define float @exp_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: exp_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call expf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail expf@plt
|
||||
;
|
||||
; RV64IF-LABEL: exp_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call expf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail expf@plt
|
||||
;
|
||||
; RV32I-LABEL: exp_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -332,21 +287,11 @@ declare float @llvm.exp2.f32(float)
|
|||
define float @exp2_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: exp2_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call exp2f@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail exp2f@plt
|
||||
;
|
||||
; RV64IF-LABEL: exp2_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call exp2f@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail exp2f@plt
|
||||
;
|
||||
; RV32I-LABEL: exp2_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -374,21 +319,11 @@ declare float @llvm.log.f32(float)
|
|||
define float @log_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: log_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call logf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail logf@plt
|
||||
;
|
||||
; RV64IF-LABEL: log_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call logf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail logf@plt
|
||||
;
|
||||
; RV32I-LABEL: log_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -416,21 +351,11 @@ declare float @llvm.log10.f32(float)
|
|||
define float @log10_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: log10_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call log10f@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail log10f@plt
|
||||
;
|
||||
; RV64IF-LABEL: log10_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call log10f@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail log10f@plt
|
||||
;
|
||||
; RV32I-LABEL: log10_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -458,21 +383,11 @@ declare float @llvm.log2.f32(float)
|
|||
define float @log2_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: log2_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call log2f@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail log2f@plt
|
||||
;
|
||||
; RV64IF-LABEL: log2_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call log2f@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail log2f@plt
|
||||
;
|
||||
; RV32I-LABEL: log2_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -725,21 +640,11 @@ declare float @llvm.floor.f32(float)
|
|||
define float @floor_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: floor_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call floorf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail floorf@plt
|
||||
;
|
||||
; RV64IF-LABEL: floor_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call floorf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail floorf@plt
|
||||
;
|
||||
; RV32I-LABEL: floor_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -767,21 +672,11 @@ declare float @llvm.ceil.f32(float)
|
|||
define float @ceil_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: ceil_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call ceilf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail ceilf@plt
|
||||
;
|
||||
; RV64IF-LABEL: ceil_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call ceilf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail ceilf@plt
|
||||
;
|
||||
; RV32I-LABEL: ceil_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -809,21 +704,11 @@ declare float @llvm.trunc.f32(float)
|
|||
define float @trunc_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: trunc_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call truncf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail truncf@plt
|
||||
;
|
||||
; RV64IF-LABEL: trunc_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call truncf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail truncf@plt
|
||||
;
|
||||
; RV32I-LABEL: trunc_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -851,21 +736,11 @@ declare float @llvm.rint.f32(float)
|
|||
define float @rint_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: rint_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call rintf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail rintf@plt
|
||||
;
|
||||
; RV64IF-LABEL: rint_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call rintf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail rintf@plt
|
||||
;
|
||||
; RV32I-LABEL: rint_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -893,21 +768,11 @@ declare float @llvm.nearbyint.f32(float)
|
|||
define float @nearbyint_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: nearbyint_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call nearbyintf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail nearbyintf@plt
|
||||
;
|
||||
; RV64IF-LABEL: nearbyint_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call nearbyintf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail nearbyintf@plt
|
||||
;
|
||||
; RV32I-LABEL: nearbyint_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -935,21 +800,11 @@ declare float @llvm.round.f32(float)
|
|||
define float @round_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: round_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call roundf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail roundf@plt
|
||||
;
|
||||
; RV64IF-LABEL: round_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call roundf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail roundf@plt
|
||||
;
|
||||
; RV32I-LABEL: round_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
@ -977,21 +832,11 @@ declare float @llvm.roundeven.f32(float)
|
|||
define float @roundeven_f32(float %a) nounwind {
|
||||
; RV32IF-LABEL: roundeven_f32:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: call roundevenf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail roundevenf@plt
|
||||
;
|
||||
; RV64IF-LABEL: roundeven_f32:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: call roundevenf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail roundevenf@plt
|
||||
;
|
||||
; RV32I-LABEL: roundeven_f32:
|
||||
; RV32I: # %bb.0:
|
||||
|
|
|
|||
|
|
@ -698,25 +698,11 @@ define float @test_floor_float(float %x) {
|
|||
; RV64IFD-NEXT: ret
|
||||
; RV32IF-LABEL: test_floor_float:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: .cfi_offset ra, -4
|
||||
; RV32IF-NEXT: call floorf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail floorf@plt
|
||||
;
|
||||
; RV64IF-LABEL: test_floor_float:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: .cfi_offset ra, -8
|
||||
; RV64IF-NEXT: call floorf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail floorf@plt
|
||||
%a = call float @llvm.floor.f32(float %x)
|
||||
ret float %a
|
||||
}
|
||||
|
|
@ -745,25 +731,11 @@ define float @test_ceil_float(float %x) {
|
|||
; RV64IFD-NEXT: ret
|
||||
; RV32IF-LABEL: test_ceil_float:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: .cfi_offset ra, -4
|
||||
; RV32IF-NEXT: call ceilf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail ceilf@plt
|
||||
;
|
||||
; RV64IF-LABEL: test_ceil_float:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: .cfi_offset ra, -8
|
||||
; RV64IF-NEXT: call ceilf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail ceilf@plt
|
||||
%a = call float @llvm.ceil.f32(float %x)
|
||||
ret float %a
|
||||
}
|
||||
|
|
@ -792,25 +764,11 @@ define float @test_trunc_float(float %x) {
|
|||
; RV64IFD-NEXT: ret
|
||||
; RV32IF-LABEL: test_trunc_float:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: .cfi_offset ra, -4
|
||||
; RV32IF-NEXT: call truncf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail truncf@plt
|
||||
;
|
||||
; RV64IF-LABEL: test_trunc_float:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: .cfi_offset ra, -8
|
||||
; RV64IF-NEXT: call truncf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail truncf@plt
|
||||
%a = call float @llvm.trunc.f32(float %x)
|
||||
ret float %a
|
||||
}
|
||||
|
|
@ -839,25 +797,11 @@ define float @test_round_float(float %x) {
|
|||
; RV64IFD-NEXT: ret
|
||||
; RV32IF-LABEL: test_round_float:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: .cfi_offset ra, -4
|
||||
; RV32IF-NEXT: call roundf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail roundf@plt
|
||||
;
|
||||
; RV64IF-LABEL: test_round_float:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: .cfi_offset ra, -8
|
||||
; RV64IF-NEXT: call roundf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail roundf@plt
|
||||
%a = call float @llvm.round.f32(float %x)
|
||||
ret float %a
|
||||
}
|
||||
|
|
@ -886,25 +830,11 @@ define float @test_roundeven_float(float %x) {
|
|||
; RV64IFD-NEXT: ret
|
||||
; RV32IF-LABEL: test_roundeven_float:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: addi sp, sp, -16
|
||||
; RV32IF-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-NEXT: .cfi_offset ra, -4
|
||||
; RV32IF-NEXT: call roundevenf@plt
|
||||
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-NEXT: addi sp, sp, 16
|
||||
; RV32IF-NEXT: ret
|
||||
; RV32IF-NEXT: tail roundevenf@plt
|
||||
;
|
||||
; RV64IF-LABEL: test_roundeven_float:
|
||||
; RV64IF: # %bb.0:
|
||||
; RV64IF-NEXT: addi sp, sp, -16
|
||||
; RV64IF-NEXT: .cfi_def_cfa_offset 16
|
||||
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-NEXT: .cfi_offset ra, -8
|
||||
; RV64IF-NEXT: call roundevenf@plt
|
||||
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-NEXT: addi sp, sp, 16
|
||||
; RV64IF-NEXT: ret
|
||||
; RV64IF-NEXT: tail roundevenf@plt
|
||||
%a = call float @llvm.roundeven.f32(float %x)
|
||||
ret float %a
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,13 +15,8 @@ define void @test_load_store(half* %p, half* %q) nounwind {
|
|||
define float @test_fpextend_float(half* %p) nounwind {
|
||||
; CHECK-LABEL: test_fpextend_float:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi sp, sp, -16
|
||||
; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; CHECK-NEXT: lhu a0, 0(a0)
|
||||
; CHECK-NEXT: call __extendhfsf2@plt
|
||||
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; CHECK-NEXT: addi sp, sp, 16
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-NEXT: tail __extendhfsf2@plt
|
||||
%a = load half, half* %p
|
||||
%r = fpext half %a to float
|
||||
ret float %r
|
||||
|
|
|
|||
|
|
@ -106,12 +106,7 @@ define i64 @mul64(i64 %a, i64 %b) nounwind {
|
|||
;
|
||||
; RV64-ALL-LABEL: mul64:
|
||||
; RV64-ALL: # %bb.0:
|
||||
; RV64-ALL-NEXT: addi sp, sp, -16
|
||||
; RV64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64-ALL-NEXT: call __muldi3@plt
|
||||
; RV64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64-ALL-NEXT: addi sp, sp, 16
|
||||
; RV64-ALL-NEXT: ret
|
||||
; RV64-ALL-NEXT: tail __muldi3@plt
|
||||
%1 = mul i64 %a, %b
|
||||
ret i64 %1
|
||||
}
|
||||
|
|
@ -241,23 +236,27 @@ define half @sin_f16(half %a) nounwind {
|
|||
declare float @llvm.sin.f32(float)
|
||||
|
||||
define float @sin_f32(float %a) nounwind {
|
||||
; RV32-ALL-LABEL: sin_f32:
|
||||
; RV32-ALL: # %bb.0:
|
||||
; RV32-ALL-NEXT: addi sp, sp, -16
|
||||
; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32-ALL-NEXT: call sinf@plt
|
||||
; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32-ALL-NEXT: addi sp, sp, 16
|
||||
; RV32-ALL-NEXT: ret
|
||||
; F-ABI-ALL-LABEL: sin_f32:
|
||||
; F-ABI-ALL: # %bb.0:
|
||||
; F-ABI-ALL-NEXT: tail sinf@plt
|
||||
;
|
||||
; RV64-ALL-LABEL: sin_f32:
|
||||
; RV64-ALL: # %bb.0:
|
||||
; RV64-ALL-NEXT: addi sp, sp, -16
|
||||
; RV64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64-ALL-NEXT: call sinf@plt
|
||||
; RV64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64-ALL-NEXT: addi sp, sp, 16
|
||||
; RV64-ALL-NEXT: ret
|
||||
; RV32-ILP32-ALL-LABEL: sin_f32:
|
||||
; RV32-ILP32-ALL: # %bb.0:
|
||||
; RV32-ILP32-ALL-NEXT: addi sp, sp, -16
|
||||
; RV32-ILP32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32-ILP32-ALL-NEXT: call sinf@plt
|
||||
; RV32-ILP32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32-ILP32-ALL-NEXT: addi sp, sp, 16
|
||||
; RV32-ILP32-ALL-NEXT: ret
|
||||
;
|
||||
; RV64-LP64-ALL-LABEL: sin_f32:
|
||||
; RV64-LP64-ALL: # %bb.0:
|
||||
; RV64-LP64-ALL-NEXT: addi sp, sp, -16
|
||||
; RV64-LP64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64-LP64-ALL-NEXT: call sinf@plt
|
||||
; RV64-LP64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64-LP64-ALL-NEXT: addi sp, sp, 16
|
||||
; RV64-LP64-ALL-NEXT: ret
|
||||
%1 = call float @llvm.sin.f32(float %a)
|
||||
ret float %1
|
||||
}
|
||||
|
|
@ -265,14 +264,22 @@ define float @sin_f32(float %a) nounwind {
|
|||
declare float @llvm.powi.f32.i32(float, i32)
|
||||
|
||||
define float @powi_f32(float %a, i32 %b) nounwind {
|
||||
; RV32-ALL-LABEL: powi_f32:
|
||||
; RV32-ALL: # %bb.0:
|
||||
; RV32-ALL-NEXT: addi sp, sp, -16
|
||||
; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32-ALL-NEXT: call __powisf2@plt
|
||||
; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32-ALL-NEXT: addi sp, sp, 16
|
||||
; RV32-ALL-NEXT: ret
|
||||
; RV32IFD-ILP32D-LABEL: powi_f32:
|
||||
; RV32IFD-ILP32D: # %bb.0:
|
||||
; RV32IFD-ILP32D-NEXT: tail __powisf2@plt
|
||||
;
|
||||
; RV32IF-ILP32F-LABEL: powi_f32:
|
||||
; RV32IF-ILP32F: # %bb.0:
|
||||
; RV32IF-ILP32F-NEXT: tail __powisf2@plt
|
||||
;
|
||||
; RV32-ILP32-ALL-LABEL: powi_f32:
|
||||
; RV32-ILP32-ALL: # %bb.0:
|
||||
; RV32-ILP32-ALL-NEXT: addi sp, sp, -16
|
||||
; RV32-ILP32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32-ILP32-ALL-NEXT: call __powisf2@plt
|
||||
; RV32-ILP32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32-ILP32-ALL-NEXT: addi sp, sp, 16
|
||||
; RV32-ILP32-ALL-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LP64D-LABEL: powi_f32:
|
||||
; RV64IFD-LP64D: # %bb.0:
|
||||
|
|
@ -352,23 +359,45 @@ define i64 @llround_f32(float %a) nounwind {
|
|||
declare double @llvm.sin.f64(double)
|
||||
|
||||
define double @sin_f64(double %a) nounwind {
|
||||
; RV32-ALL-LABEL: sin_f64:
|
||||
; RV32-ALL: # %bb.0:
|
||||
; RV32-ALL-NEXT: addi sp, sp, -16
|
||||
; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32-ALL-NEXT: call sin@plt
|
||||
; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32-ALL-NEXT: addi sp, sp, 16
|
||||
; RV32-ALL-NEXT: ret
|
||||
; D-ABI-ALL-LABEL: sin_f64:
|
||||
; D-ABI-ALL: # %bb.0:
|
||||
; D-ABI-ALL-NEXT: tail sin@plt
|
||||
;
|
||||
; RV64-ALL-LABEL: sin_f64:
|
||||
; RV64-ALL: # %bb.0:
|
||||
; RV64-ALL-NEXT: addi sp, sp, -16
|
||||
; RV64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64-ALL-NEXT: call sin@plt
|
||||
; RV64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64-ALL-NEXT: addi sp, sp, 16
|
||||
; RV64-ALL-NEXT: ret
|
||||
; RV32IF-ILP32F-LABEL: sin_f64:
|
||||
; RV32IF-ILP32F: # %bb.0:
|
||||
; RV32IF-ILP32F-NEXT: addi sp, sp, -16
|
||||
; RV32IF-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-ILP32F-NEXT: call sin@plt
|
||||
; RV32IF-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-ILP32F-NEXT: addi sp, sp, 16
|
||||
; RV32IF-ILP32F-NEXT: ret
|
||||
;
|
||||
; RV32-ILP32-ALL-LABEL: sin_f64:
|
||||
; RV32-ILP32-ALL: # %bb.0:
|
||||
; RV32-ILP32-ALL-NEXT: addi sp, sp, -16
|
||||
; RV32-ILP32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32-ILP32-ALL-NEXT: call sin@plt
|
||||
; RV32-ILP32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32-ILP32-ALL-NEXT: addi sp, sp, 16
|
||||
; RV32-ILP32-ALL-NEXT: ret
|
||||
;
|
||||
; RV64IF-LP64F-LABEL: sin_f64:
|
||||
; RV64IF-LP64F: # %bb.0:
|
||||
; RV64IF-LP64F-NEXT: addi sp, sp, -16
|
||||
; RV64IF-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IF-LP64F-NEXT: call sin@plt
|
||||
; RV64IF-LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IF-LP64F-NEXT: addi sp, sp, 16
|
||||
; RV64IF-LP64F-NEXT: ret
|
||||
;
|
||||
; RV64-LP64-ALL-LABEL: sin_f64:
|
||||
; RV64-LP64-ALL: # %bb.0:
|
||||
; RV64-LP64-ALL-NEXT: addi sp, sp, -16
|
||||
; RV64-LP64-ALL-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64-LP64-ALL-NEXT: call sin@plt
|
||||
; RV64-LP64-ALL-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64-LP64-ALL-NEXT: addi sp, sp, 16
|
||||
; RV64-LP64-ALL-NEXT: ret
|
||||
%1 = call double @llvm.sin.f64(double %a)
|
||||
ret double %1
|
||||
}
|
||||
|
|
@ -376,14 +405,27 @@ define double @sin_f64(double %a) nounwind {
|
|||
declare double @llvm.powi.f64.i32(double, i32)
|
||||
|
||||
define double @powi_f64(double %a, i32 %b) nounwind {
|
||||
; RV32-ALL-LABEL: powi_f64:
|
||||
; RV32-ALL: # %bb.0:
|
||||
; RV32-ALL-NEXT: addi sp, sp, -16
|
||||
; RV32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32-ALL-NEXT: call __powidf2@plt
|
||||
; RV32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32-ALL-NEXT: addi sp, sp, 16
|
||||
; RV32-ALL-NEXT: ret
|
||||
; RV32IFD-ILP32D-LABEL: powi_f64:
|
||||
; RV32IFD-ILP32D: # %bb.0:
|
||||
; RV32IFD-ILP32D-NEXT: tail __powidf2@plt
|
||||
;
|
||||
; RV32IF-ILP32F-LABEL: powi_f64:
|
||||
; RV32IF-ILP32F: # %bb.0:
|
||||
; RV32IF-ILP32F-NEXT: addi sp, sp, -16
|
||||
; RV32IF-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IF-ILP32F-NEXT: call __powidf2@plt
|
||||
; RV32IF-ILP32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IF-ILP32F-NEXT: addi sp, sp, 16
|
||||
; RV32IF-ILP32F-NEXT: ret
|
||||
;
|
||||
; RV32-ILP32-ALL-LABEL: powi_f64:
|
||||
; RV32-ILP32-ALL: # %bb.0:
|
||||
; RV32-ILP32-ALL-NEXT: addi sp, sp, -16
|
||||
; RV32-ILP32-ALL-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32-ILP32-ALL-NEXT: call __powidf2@plt
|
||||
; RV32-ILP32-ALL-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32-ILP32-ALL-NEXT: addi sp, sp, 16
|
||||
; RV32-ILP32-ALL-NEXT: ret
|
||||
;
|
||||
; RV64IFD-LP64D-LABEL: powi_f64:
|
||||
; RV64IFD-LP64D: # %bb.0:
|
||||
|
|
@ -561,6 +603,3 @@ define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind {
|
|||
}
|
||||
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||||
; ALL: {{.*}}
|
||||
; D-ABI-ALL: {{.*}}
|
||||
; F-ABI-ALL: {{.*}}
|
||||
; RV32-ILP32-ALL: {{.*}}
|
||||
|
|
|
|||
|
|
@ -150,12 +150,7 @@ define i64 @mul64(i64 %a, i64 %b) nounwind {
|
|||
;
|
||||
; RV64I-LABEL: mul64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: call __muldi3@plt
|
||||
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: tail __muldi3@plt
|
||||
;
|
||||
; RV64IM-LABEL: mul64:
|
||||
; RV64IM: # %bb.0:
|
||||
|
|
@ -755,13 +750,8 @@ define i64 @muli64_m65(i64 %a) nounwind {
|
|||
define i32 @muli32_p384(i32 %a) nounwind {
|
||||
; RV32I-LABEL: muli32_p384:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: li a1, 384
|
||||
; RV32I-NEXT: call __mulsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __mulsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: muli32_p384:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -791,13 +781,8 @@ define i32 @muli32_p384(i32 %a) nounwind {
|
|||
define i32 @muli32_p12288(i32 %a) nounwind {
|
||||
; RV32I-LABEL: muli32_p12288:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: lui a1, 3
|
||||
; RV32I-NEXT: call __mulsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __mulsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: muli32_p12288:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -923,14 +908,9 @@ define i32 @muli32_m3840(i32 %a) nounwind {
|
|||
define i32 @muli32_m4352(i32 %a) nounwind {
|
||||
; RV32I-LABEL: muli32_m4352:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: lui a1, 1048575
|
||||
; RV32I-NEXT: addi a1, a1, -256
|
||||
; RV32I-NEXT: call __mulsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __mulsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: muli32_m4352:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -1074,14 +1054,9 @@ define i64 @muli64_m4352(i64 %a) nounwind {
|
|||
;
|
||||
; RV64I-LABEL: muli64_m4352:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: lui a1, 1048575
|
||||
; RV64I-NEXT: addiw a1, a1, -256
|
||||
; RV64I-NEXT: call __muldi3@plt
|
||||
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: tail __muldi3@plt
|
||||
;
|
||||
; RV64IM-LABEL: muli64_m4352:
|
||||
; RV64IM: # %bb.0:
|
||||
|
|
|
|||
|
|
@ -11,12 +11,7 @@
|
|||
define i32 @urem(i32 %a, i32 %b) nounwind {
|
||||
; RV32I-LABEL: urem:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: call __umodsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __umodsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: urem:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -47,14 +42,9 @@ define i32 @urem(i32 %a, i32 %b) nounwind {
|
|||
define i32 @urem_constant_lhs(i32 %a) nounwind {
|
||||
; RV32I-LABEL: urem_constant_lhs:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: mv a1, a0
|
||||
; RV32I-NEXT: li a0, 10
|
||||
; RV32I-NEXT: call __umodsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __umodsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: urem_constant_lhs:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -86,12 +76,7 @@ define i32 @urem_constant_lhs(i32 %a) nounwind {
|
|||
define i32 @srem(i32 %a, i32 %b) nounwind {
|
||||
; RV32I-LABEL: srem:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: call __modsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __modsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: srem:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -204,14 +189,9 @@ define i32 @srem_pow2_2(i32 %a) nounwind {
|
|||
define i32 @srem_constant_lhs(i32 %a) nounwind {
|
||||
; RV32I-LABEL: srem_constant_lhs:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: mv a1, a0
|
||||
; RV32I-NEXT: li a0, -10
|
||||
; RV32I-NEXT: call __modsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __modsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: srem_constant_lhs:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -260,12 +240,7 @@ define i64 @urem64(i64 %a, i64 %b) nounwind {
|
|||
;
|
||||
; RV64I-LABEL: urem64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: call __umoddi3@plt
|
||||
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: tail __umoddi3@plt
|
||||
;
|
||||
; RV64IM-LABEL: urem64:
|
||||
; RV64IM: # %bb.0:
|
||||
|
|
@ -304,14 +279,9 @@ define i64 @urem64_constant_lhs(i64 %a) nounwind {
|
|||
;
|
||||
; RV64I-LABEL: urem64_constant_lhs:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: mv a1, a0
|
||||
; RV64I-NEXT: li a0, 10
|
||||
; RV64I-NEXT: call __umoddi3@plt
|
||||
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: tail __umoddi3@plt
|
||||
;
|
||||
; RV64IM-LABEL: urem64_constant_lhs:
|
||||
; RV64IM: # %bb.0:
|
||||
|
|
@ -343,12 +313,7 @@ define i64 @srem64(i64 %a, i64 %b) nounwind {
|
|||
;
|
||||
; RV64I-LABEL: srem64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: call __moddi3@plt
|
||||
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: tail __moddi3@plt
|
||||
;
|
||||
; RV64IM-LABEL: srem64:
|
||||
; RV64IM: # %bb.0:
|
||||
|
|
@ -387,14 +352,9 @@ define i64 @srem64_constant_lhs(i64 %a) nounwind {
|
|||
;
|
||||
; RV64I-LABEL: srem64_constant_lhs:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: mv a1, a0
|
||||
; RV64I-NEXT: li a0, -10
|
||||
; RV64I-NEXT: call __moddi3@plt
|
||||
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: tail __moddi3@plt
|
||||
;
|
||||
; RV64IM-LABEL: srem64_constant_lhs:
|
||||
; RV64IM: # %bb.0:
|
||||
|
|
|
|||
|
|
@ -11,13 +11,8 @@
|
|||
define i32 @fold_srem_positive_odd(i32 %x) nounwind {
|
||||
; RV32I-LABEL: fold_srem_positive_odd:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: li a1, 95
|
||||
; RV32I-NEXT: call __modsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __modsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: fold_srem_positive_odd:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -67,13 +62,8 @@ define i32 @fold_srem_positive_odd(i32 %x) nounwind {
|
|||
define i32 @fold_srem_positive_even(i32 %x) nounwind {
|
||||
; RV32I-LABEL: fold_srem_positive_even:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: li a1, 1060
|
||||
; RV32I-NEXT: call __modsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __modsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: fold_srem_positive_even:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -120,13 +110,8 @@ define i32 @fold_srem_positive_even(i32 %x) nounwind {
|
|||
define i32 @fold_srem_negative_odd(i32 %x) nounwind {
|
||||
; RV32I-LABEL: fold_srem_negative_odd:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: li a1, -723
|
||||
; RV32I-NEXT: call __modsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __modsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: fold_srem_negative_odd:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -173,14 +158,9 @@ define i32 @fold_srem_negative_odd(i32 %x) nounwind {
|
|||
define i32 @fold_srem_negative_even(i32 %x) nounwind {
|
||||
; RV32I-LABEL: fold_srem_negative_even:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: lui a1, 1048570
|
||||
; RV32I-NEXT: addi a1, a1, 1595
|
||||
; RV32I-NEXT: call __modsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __modsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: fold_srem_negative_even:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -429,13 +409,8 @@ define i64 @dont_fold_srem_i64(i64 %x) nounwind {
|
|||
;
|
||||
; RV64I-LABEL: dont_fold_srem_i64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: li a1, 98
|
||||
; RV64I-NEXT: call __moddi3@plt
|
||||
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: tail __moddi3@plt
|
||||
;
|
||||
; RV64IM-LABEL: dont_fold_srem_i64:
|
||||
; RV64IM: # %bb.0:
|
||||
|
|
|
|||
|
|
@ -11,13 +11,8 @@
|
|||
define i32 @fold_urem_positive_odd(i32 %x) nounwind {
|
||||
; RV32I-LABEL: fold_urem_positive_odd:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: li a1, 95
|
||||
; RV32I-NEXT: call __umodsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __umodsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: fold_urem_positive_odd:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -69,13 +64,8 @@ define i32 @fold_urem_positive_odd(i32 %x) nounwind {
|
|||
define i32 @fold_urem_positive_even(i32 %x) nounwind {
|
||||
; RV32I-LABEL: fold_urem_positive_even:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32I-NEXT: li a1, 1060
|
||||
; RV32I-NEXT: call __umodsi3@plt
|
||||
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
; RV32I-NEXT: tail __umodsi3@plt
|
||||
;
|
||||
; RV32IM-LABEL: fold_urem_positive_even:
|
||||
; RV32IM: # %bb.0:
|
||||
|
|
@ -254,13 +244,8 @@ define i64 @dont_fold_urem_i64(i64 %x) nounwind {
|
|||
;
|
||||
; RV64I-LABEL: dont_fold_urem_i64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64I-NEXT: li a1, 98
|
||||
; RV64I-NEXT: call __umoddi3@plt
|
||||
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: tail __umoddi3@plt
|
||||
;
|
||||
; RV64IM-LABEL: dont_fold_urem_i64:
|
||||
; RV64IM: # %bb.0:
|
||||
|
|
|
|||
Loading…
Reference in New Issue