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support more relocations for stores also 

llvm-svn: 22306
This commit is contained in:
Andrew Lenharth 2005-06-29 00:39:17 +00:00
parent 1ef3c0c798
commit 47a9c4715a
2 changed files with 36 additions and 1 deletions
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26
llvm/lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -855,6 +855,13 @@ static unsigned GetRelVersion(unsigned opcode)
case Alpha::LDL: return Alpha::LDLr;
case Alpha::LDBU: return Alpha::LDBUr;
case Alpha::LDWU: return Alpha::LDWUr;
case Alpha::STB: return Alpha::STBr;
case Alpha::STW: return Alpha::STWr;
case Alpha::STL: return Alpha::STLr;
case Alpha::STQ: return Alpha::STQr;
case Alpha::STS: return Alpha::STSr;
case Alpha::STT: return Alpha::STTr;
}
}
@ -2302,7 +2309,24 @@ void AlphaISel::Select(SDOperand N) {
j = getFunctionOffset(BB->getParent()->getFunction());
}
if(Address.getOpcode() == ISD::FrameIndex) {
if (GlobalAddressSDNode *GASD =
dyn_cast<GlobalAddressSDNode>(Address)) {
if (GASD->getGlobal()->isExternal()) {
Tmp2 = SelectExpr(Address);
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(0).addReg(Tmp2);
} else {
Tmp2 = MakeReg(MVT::i64);
AlphaLowering.restoreGP(BB);
BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
.addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
}
} else if(Address.getOpcode() == ISD::FrameIndex) {
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
BuildMI(BB, Opc, 3).addReg(Tmp1)

11
llvm/lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -350,6 +350,17 @@ def LDAHr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP(
//Load quad, rellocated literal form
def LDQl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
//Stores, int
def STBr : MForm<0x0E, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stb $RA,$DISP($RB) !gprellow">; // Store byte
def STWr : MForm<0x0D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stw $RA,$DISP($RB) !gprellow">; // Store word
def STLr : MForm<0x2C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stl $RA,$DISP($RB) !gprellow">; // Store longword
def STQr : MForm<0x2D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stq $RA,$DISP($RB) !gprellow">; //Store quadword
//Stores, float
def STSr : MForm<0x26, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "sts $RA,$DISP($RB) !gprellow">; //Store S_floating
def STTr : MForm<0x27, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "stt $RA,$DISP($RB) !gprellow">; //Store T_floating
//Branches, int
def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero
def BGE : BForm<0x3E, (ops GPRC:$RA, s21imm:$DISP), "bge $RA,$DISP">; //Branch if >= zero