forked from OSchip/llvm-project
[mlir][amx] add doc to AMX dialect
Making sure the AMX dialect webpage reads better with a short introduction on the purpose of this dialect. Reviewed By: grosul1, bondhugula Differential Revision: https://reviews.llvm.org/D107419
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@ -8,7 +8,7 @@
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//
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// This file defines the basic operations for the AMX dialect.
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//
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// The Intel Advanced Matrix Extensions (AMX) provides a tile matrix
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// The Intel Advanced Matrix Extensions (AMX) provide a tile matrix
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// multiply unit (TMUL), a tile control register (TILECFG), and eight
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// tile registers TMM0 through TMM7 (TILEDATA).
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//
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@ -38,6 +38,23 @@ include "mlir/Interfaces/SideEffectInterfaces.td"
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def AMX_Dialect : Dialect {
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let name = "amx";
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let cppNamespace = "::mlir::amx";
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let description = [{
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The Intel Advanced Matrix Extensions (AMX) provide a tile matrix
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multiply unit (TMUL), a tile control register (TILECFG), and eight
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tile registers TMM0 through TMM7 (TILEDATA).
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This `AMX` dialect provides a bridge between MLIR concepts such as
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vectors and memrefs and the lower level LLVM IR support of AMX.
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The dialect is split into user-facing AMX ops (AMX_Op) and
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backend-facing intrinsic ops (AMX_IntrOp).
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Note that since configuration changes (implicit at dialect level) are
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costly, it is highly recommended to use the AMX dialect on same-shaped
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vectors, at least within a single method.
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For details, see the Intel documentation:
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https://software.intel.com/content/www/us/en/develop/articles/intel-sdm.html
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}];
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}
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//===----------------------------------------------------------------------===//
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@ -203,7 +220,7 @@ def TileMulIOp : AMX_Op<"tile_muli", [NoSideEffect, AllTypesMatch<["acc", "res"]
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Example:
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```mlir
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%0 = amx.tile_muli %a zext, %b zext, %c
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%0 = amx.tile_muli %a zext, %b zext, %c
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: vector<16x64xi8>, vector<16x64xi8>, vector<16x16xi32>
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```
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}];
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