diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp index d8546c7b89ae..01b1f4cdf3ca 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -1166,6 +1166,13 @@ static Instruction *foldSelectShuffles(ShuffleVectorInst &Shuf) { if (isa(X)) return nullptr; + // Constant operands must be on the same side of each binop. We can't fold: + // shuffle (sdiv X, C0), (sdiv C1, X). + bool B00IsConst = isa(B0->getOperand(0)); + bool B10IsConst = isa(B1->getOperand(0)); + if (B00IsConst != B10IsConst) + return nullptr; + // Remove a binop and the shuffle by rearranging the constant: // shuffle (op X, C0), (op X, C1), M --> op X, C' // shuffle (op C0, X), (op C1, X), M --> op C', X @@ -1178,8 +1185,7 @@ static Instruction *foldSelectShuffles(ShuffleVectorInst &Shuf) { NewC = getSafeVectorConstantForIntDivRem(NewC); BinaryOperator::BinaryOps Opc = B0->getOpcode(); - bool Op0IsConst = isa(B0->getOperand(0)); - Instruction *NewBO = Op0IsConst ? BinaryOperator::Create(Opc, NewC, X) : + Instruction *NewBO = B00IsConst ? BinaryOperator::Create(Opc, NewC, X) : BinaryOperator::Create(Opc, X, NewC); // Flags are intersected from the 2 source binops. diff --git a/llvm/test/Transforms/InstCombine/shuffle_select.ll b/llvm/test/Transforms/InstCombine/shuffle_select.ll index e3e2dde0915f..ed9266a84595 100644 --- a/llvm/test/Transforms/InstCombine/shuffle_select.ll +++ b/llvm/test/Transforms/InstCombine/shuffle_select.ll @@ -224,12 +224,13 @@ define <4 x double> @fdiv(<4 x double> %v0) { ret <4 x double> %t3 } -; FIXME: ; The variable operand must be either the first operand or second operand in both binops. define <4 x double> @frem(<4 x double> %v0) { ; CHECK-LABEL: @frem( -; CHECK-NEXT: [[T3:%.*]] = frem <4 x double> , [[V0:%.*]] +; CHECK-NEXT: [[T1:%.*]] = frem <4 x double> , [[V0:%.*]] +; CHECK-NEXT: [[T2:%.*]] = frem <4 x double> [[V0]], +; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x double> [[T1]], <4 x double> [[T2]], <4 x i32> ; CHECK-NEXT: ret <4 x double> [[T3]] ; %t1 = frem <4 x double> , %v0