forked from OSchip/llvm-project
[InstCombine] fix shuffle-of-binops bug
With non-commutative binops, we could be using the same variable value as operand 0 in 1 binop and operand 1 in the other, so we have to check for that possibility and bail out. llvm-svn: 335312
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@ -1166,6 +1166,13 @@ static Instruction *foldSelectShuffles(ShuffleVectorInst &Shuf) {
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if (isa<Constant>(X))
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return nullptr;
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// Constant operands must be on the same side of each binop. We can't fold:
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// shuffle (sdiv X, C0), (sdiv C1, X).
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bool B00IsConst = isa<Constant>(B0->getOperand(0));
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bool B10IsConst = isa<Constant>(B1->getOperand(0));
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if (B00IsConst != B10IsConst)
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return nullptr;
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// Remove a binop and the shuffle by rearranging the constant:
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// shuffle (op X, C0), (op X, C1), M --> op X, C'
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// shuffle (op C0, X), (op C1, X), M --> op C', X
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@ -1178,8 +1185,7 @@ static Instruction *foldSelectShuffles(ShuffleVectorInst &Shuf) {
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NewC = getSafeVectorConstantForIntDivRem(NewC);
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BinaryOperator::BinaryOps Opc = B0->getOpcode();
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bool Op0IsConst = isa<Constant>(B0->getOperand(0));
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Instruction *NewBO = Op0IsConst ? BinaryOperator::Create(Opc, NewC, X) :
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Instruction *NewBO = B00IsConst ? BinaryOperator::Create(Opc, NewC, X) :
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BinaryOperator::Create(Opc, X, NewC);
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// Flags are intersected from the 2 source binops.
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@ -224,12 +224,13 @@ define <4 x double> @fdiv(<4 x double> %v0) {
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ret <4 x double> %t3
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}
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; FIXME:
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; The variable operand must be either the first operand or second operand in both binops.
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define <4 x double> @frem(<4 x double> %v0) {
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; CHECK-LABEL: @frem(
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; CHECK-NEXT: [[T3:%.*]] = frem <4 x double> <double 1.000000e+00, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = frem <4 x double> <double 1.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00>, [[V0:%.*]]
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; CHECK-NEXT: [[T2:%.*]] = frem <4 x double> [[V0]], <double 5.000000e+00, double 6.000000e+00, double 7.000000e+00, double 8.000000e+00>
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; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x double> [[T1]], <4 x double> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x double> [[T3]]
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;
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%t1 = frem <4 x double> <double 1.0, double 2.0, double 3.0, double 4.0>, %v0
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