forked from OSchip/llvm-project
[AMDGPU][MC] Parser cleanup and refactoring
Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D60767 llvm-svn: 359096
This commit is contained in:
Dmitry Preobrazhensky
parent
b1b3368907
commit
47621d7c89
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@ -178,6 +178,7 @@ public:
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ImmTyHigh
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};
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private:
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struct TokOp {
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const char *Data;
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unsigned Length;
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@ -192,7 +193,6 @@ public:
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struct RegOp {
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unsigned RegNo;
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bool IsForcedVOP3;
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Modifiers Mods;
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};
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@ -203,6 +203,7 @@ public:
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const MCExpr *Expr;
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};
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public:
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bool isToken() const override {
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if (Kind == Token)
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return true;
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@ -548,6 +549,7 @@ public:
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}
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unsigned getReg() const override {
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assert(isRegKind());
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return Reg.RegNo;
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}
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@ -764,12 +766,10 @@ public:
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static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser,
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unsigned RegNo, SMLoc S,
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SMLoc E,
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bool ForceVOP3) {
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SMLoc E) {
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auto Op = llvm::make_unique<AMDGPUOperand>(Register, AsmParser);
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Op->Reg.RegNo = RegNo;
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Op->Reg.Mods = Modifiers();
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Op->Reg.IsForcedVOP3 = ForceVOP3;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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@ -1083,7 +1083,7 @@ public:
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bool parseSP3NegModifier();
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OperandMatchResultTy parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false);
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OperandMatchResultTy parseReg(OperandVector &Operands);
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OperandMatchResultTy parseRegOrImm(OperandVector &Operands, bool AbsMod = false);
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OperandMatchResultTy parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false);
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OperandMatchResultTy parseRegOrImmWithFPInputMods(OperandVector &Operands, bool AllowImm = true);
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OperandMatchResultTy parseRegOrImmWithIntInputMods(OperandVector &Operands, bool AllowImm = true);
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OperandMatchResultTy parseRegWithFPInputMods(OperandVector &Operands);
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@ -2000,7 +2000,7 @@ std::unique_ptr<AMDGPUOperand> AMDGPUAsmParser::parseRegister() {
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return nullptr;
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} else
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KernelScope.usesRegister(RegKind, DwordRegIndex, RegWidth);
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return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc, false);
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return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc);
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}
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bool
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@ -2091,7 +2091,6 @@ AMDGPUAsmParser::parseReg(OperandVector &Operands) {
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if (auto R = parseRegister()) {
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assert(R->isReg());
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R->Reg.IsForcedVOP3 = isForcedVOP3();
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Operands.push_back(std::move(R));
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return MatchOperand_Success;
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}
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@ -2099,10 +2098,10 @@ AMDGPUAsmParser::parseReg(OperandVector &Operands) {
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}
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OperandMatchResultTy
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AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands, bool AbsMod) {
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AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod) {
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auto res = parseReg(Operands);
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return (res == MatchOperand_NoMatch)?
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parseImm(Operands, AbsMod) :
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parseImm(Operands, HasSP3AbsMod) :
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res;
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}
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@ -2148,7 +2147,9 @@ AMDGPUAsmParser::parseSP3NegModifier() {
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OperandMatchResultTy
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AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
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bool AllowImm) {
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bool Negate, Negate2 = false, Abs = false, Abs2 = false;
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bool Neg, SP3Neg;
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bool Abs, SP3Abs;
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SMLoc Loc;
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// Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead.
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if (isToken(AsmToken::Minus) && peekToken().is(AsmToken::Minus)) {
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@ -2156,81 +2157,48 @@ AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
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return MatchOperand_ParseFail;
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}
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Negate = parseSP3NegModifier();
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SP3Neg = parseSP3NegModifier();
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if (getLexer().getKind() == AsmToken::Identifier &&
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Parser.getTok().getString() == "neg") {
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if (Negate) {
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Error(Parser.getTok().getLoc(), "expected register or immediate");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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Negate2 = true;
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if (getLexer().isNot(AsmToken::LParen)) {
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Error(Parser.getTok().getLoc(), "expected left paren after neg");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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Loc = getLoc();
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Neg = trySkipId("neg");
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if (Neg && SP3Neg) {
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Error(Loc, "expected register or immediate");
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return MatchOperand_ParseFail;
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}
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if (Neg && !skipToken(AsmToken::LParen, "expected left paren after neg"))
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return MatchOperand_ParseFail;
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if (getLexer().getKind() == AsmToken::Identifier &&
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Parser.getTok().getString() == "abs") {
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Parser.Lex();
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Abs2 = true;
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if (getLexer().isNot(AsmToken::LParen)) {
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Error(Parser.getTok().getLoc(), "expected left paren after abs");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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}
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Abs = trySkipId("abs");
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if (Abs && !skipToken(AsmToken::LParen, "expected left paren after abs"))
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return MatchOperand_ParseFail;
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if (getLexer().getKind() == AsmToken::Pipe) {
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if (Abs2) {
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Error(Parser.getTok().getLoc(), "expected register or immediate");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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Abs = true;
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Loc = getLoc();
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SP3Abs = trySkipToken(AsmToken::Pipe);
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if (Abs && SP3Abs) {
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Error(Loc, "expected register or immediate");
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return MatchOperand_ParseFail;
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}
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OperandMatchResultTy Res;
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if (AllowImm) {
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Res = parseRegOrImm(Operands, Abs);
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Res = parseRegOrImm(Operands, SP3Abs);
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} else {
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Res = parseReg(Operands);
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}
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if (Res != MatchOperand_Success) {
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return (Negate || Negate2 || Abs || Abs2)? MatchOperand_ParseFail : Res;
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return (SP3Neg || Neg || SP3Abs || Abs)? MatchOperand_ParseFail : Res;
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}
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if (SP3Abs && !skipToken(AsmToken::Pipe, "expected vertical bar"))
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return MatchOperand_ParseFail;
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if (Abs && !skipToken(AsmToken::RParen, "expected closing parentheses"))
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return MatchOperand_ParseFail;
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if (Neg && !skipToken(AsmToken::RParen, "expected closing parentheses"))
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return MatchOperand_ParseFail;
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AMDGPUOperand::Modifiers Mods;
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if (Abs) {
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if (getLexer().getKind() != AsmToken::Pipe) {
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Error(Parser.getTok().getLoc(), "expected vertical bar");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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Mods.Abs = true;
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}
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if (Abs2) {
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if (getLexer().isNot(AsmToken::RParen)) {
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Error(Parser.getTok().getLoc(), "expected closing parentheses");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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Mods.Abs = true;
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}
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if (Negate) {
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Mods.Neg = true;
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} else if (Negate2) {
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if (getLexer().isNot(AsmToken::RParen)) {
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Error(Parser.getTok().getLoc(), "expected closing parentheses");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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Mods.Neg = true;
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}
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Mods.Abs = Abs || SP3Abs;
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Mods.Neg = Neg || SP3Neg;
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if (Mods.hasFPModifiers()) {
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AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
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@ -2242,18 +2210,9 @@ AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
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OperandMatchResultTy
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AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,
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bool AllowImm) {
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bool Sext = false;
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if (getLexer().getKind() == AsmToken::Identifier &&
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Parser.getTok().getString() == "sext") {
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Parser.Lex();
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Sext = true;
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if (getLexer().isNot(AsmToken::LParen)) {
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Error(Parser.getTok().getLoc(), "expected left paren after sext");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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}
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bool Sext = trySkipId("sext");
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if (Sext && !skipToken(AsmToken::LParen, "expected left paren after sext"))
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return MatchOperand_ParseFail;
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OperandMatchResultTy Res;
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if (AllowImm) {
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@ -2265,15 +2224,11 @@ AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,
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return Sext? MatchOperand_ParseFail : Res;
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}
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if (Sext && !skipToken(AsmToken::RParen, "expected closing parentheses"))
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return MatchOperand_ParseFail;
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AMDGPUOperand::Modifiers Mods;
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if (Sext) {
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if (getLexer().isNot(AsmToken::RParen)) {
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Error(Parser.getTok().getLoc(), "expected closing parentheses");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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Mods.Sext = true;
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}
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Mods.Sext = Sext;
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if (Mods.hasIntModifiers()) {
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AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
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@ -5462,7 +5417,7 @@ void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
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} else if (Op.isInterpSlot() ||
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Op.isInterpAttr() ||
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Op.isAttrChan()) {
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Inst.addOperand(MCOperand::createImm(Op.Imm.Val));
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Inst.addOperand(MCOperand::createImm(Op.getImm()));
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} else if (Op.isImmModifier()) {
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OptionalIdx[Op.getImmTy()] = I;
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} else {
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@ -5801,7 +5756,7 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands) {
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}
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
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// Add the register arguments
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if (Op.isReg() && Op.Reg.RegNo == AMDGPU::VCC) {
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if (Op.isReg() && Op.getReg() == AMDGPU::VCC) {
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// VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.
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// Skip it.
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continue;
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@ -5920,7 +5875,7 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
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for (unsigned E = Operands.size(); I != E; ++I) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
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if (skipVcc && !skippedVcc && Op.isReg() && Op.Reg.RegNo == AMDGPU::VCC) {
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if (skipVcc && !skippedVcc && Op.isReg() && Op.getReg() == AMDGPU::VCC) {
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// VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst.
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// Skip it if it's 2nd (e.g. v_add_i32_sdwa v1, vcc, v2, v3)
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// or 4th (v_addc_u32_sdwa v1, vcc, v2, v3, vcc) operand.
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