From 47363a148f1d3003f0dd1cce234b60cdc8cc48bd Mon Sep 17 00:00:00 2001 From: Cameron McInally Date: Wed, 9 Oct 2019 21:52:15 +0000 Subject: [PATCH] [IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator Also update Clang to call Builder.CreateFNeg(...) for UnaryMinus. Differential Revision: https://reviews.llvm.org/D61675 llvm-svn: 374240 --- clang/lib/CodeGen/CGExprScalar.cpp | 14 +- clang/test/CodeGen/aarch64-neon-2velem.c | 34 +-- clang/test/CodeGen/aarch64-neon-fma.c | 2 +- clang/test/CodeGen/aarch64-neon-intrinsics.c | 10 +- clang/test/CodeGen/aarch64-neon-misc.c | 6 +- .../aarch64-neon-scalar-x-indexed-elem.c | 6 +- .../CodeGen/aarch64-v8.2a-fp16-intrinsics.c | 2 +- .../CodeGen/aarch64-v8.2a-neon-intrinsics.c | 24 +- .../test/CodeGen/arm-v8.2a-neon-intrinsics.c | 8 +- clang/test/CodeGen/arm_neon_intrinsics.c | 8 +- clang/test/CodeGen/avx512f-builtins.c | 288 +++++++++--------- clang/test/CodeGen/avx512vl-builtins.c | 144 ++++----- clang/test/CodeGen/builtins-ppc-vsx.c | 12 +- clang/test/CodeGen/complex-math.c | 6 +- clang/test/CodeGen/exprs.c | 2 +- clang/test/CodeGen/fma-builtins.c | 64 ++-- clang/test/CodeGen/fma4-builtins.c | 64 ++-- clang/test/CodeGen/fp16-ops.c | 4 +- clang/test/CodeGen/zvector.c | 2 +- clang/test/CodeGen/zvector2.c | 2 +- llvm/include/llvm/IR/IRBuilder.h | 6 +- .../AMDGPU/amdgpu-codegenprepare-idiv.ll | 104 +++---- llvm/test/CodeGen/AMDGPU/divrem24-assume.ll | 2 +- llvm/test/Transforms/InstCombine/cos-1.ll | 20 +- llvm/test/Transforms/InstCombine/fast-math.ll | 2 +- llvm/test/Transforms/InstCombine/fmul.ll | 8 +- .../Transforms/InstCombine/select-crash.ll | 4 +- llvm/unittests/IR/InstructionsTest.cpp | 15 + 28 files changed, 439 insertions(+), 424 deletions(-) diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index bff88b2feca2..19b1cedf32e4 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -2577,14 +2577,16 @@ ScalarExprEmitter::EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV, Value *ScalarExprEmitter::VisitUnaryMinus(const UnaryOperator *E) { TestAndClearIgnoreResultAssign(); + Value *Op = Visit(E->getSubExpr()); + + // Generate a unary FNeg for FP ops. + if (Op->getType()->isFPOrFPVectorTy()) + return Builder.CreateFNeg(Op, "fneg"); + // Emit unary minus with EmitSub so we handle overflow cases etc. BinOpInfo BinOp; - BinOp.RHS = Visit(E->getSubExpr()); - - if (BinOp.RHS->getType()->isFPOrFPVectorTy()) - BinOp.LHS = llvm::ConstantFP::getZeroValueForNegation(BinOp.RHS->getType()); - else - BinOp.LHS = llvm::Constant::getNullValue(BinOp.RHS->getType()); + BinOp.RHS = Op; + BinOp.LHS = llvm::Constant::getNullValue(BinOp.RHS->getType()); BinOp.Ty = E->getType(); BinOp.Opcode = BO_Sub; // FIXME: once UnaryOperator carries FPFeatures, copy it here. diff --git a/clang/test/CodeGen/aarch64-neon-2velem.c b/clang/test/CodeGen/aarch64-neon-2velem.c index d8eae760b4a8..5db29344a000 100644 --- a/clang/test/CodeGen/aarch64-neon-2velem.c +++ b/clang/test/CodeGen/aarch64-neon-2velem.c @@ -333,7 +333,7 @@ float32x4_t test_vfmaq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) { } // CHECK-LABEL: @test_vfms_lane_f32( -// CHECK: [[SUB:%.*]] = fsub <2 x float> , %b +// CHECK: [[SUB:%.*]] = fneg <2 x float> %b // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> @@ -348,7 +348,7 @@ float32x2_t test_vfms_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) { } // CHECK-LABEL: @test_vfmsq_lane_f32( -// CHECK: [[SUB:%.*]] = fsub <4 x float> , %b +// CHECK: [[SUB:%.*]] = fneg <4 x float> %b // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> @@ -363,7 +363,7 @@ float32x4_t test_vfmsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) { } // CHECK-LABEL: @test_vfms_laneq_f32( -// CHECK: [[SUB:%.*]] = fsub <2 x float> , %b +// CHECK: [[SUB:%.*]] = fneg <2 x float> %b // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> @@ -378,7 +378,7 @@ float32x2_t test_vfms_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) { } // CHECK-LABEL: @test_vfmsq_laneq_f32( -// CHECK: [[SUB:%.*]] = fsub <4 x float> , %b +// CHECK: [[SUB:%.*]] = fneg <4 x float> %b // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> @@ -421,7 +421,7 @@ float64x2_t test_vfmaq_laneq_f64(float64x2_t a, float64x2_t b, float64x2_t v) { } // CHECK-LABEL: @test_vfmsq_lane_f64( -// CHECK: [[SUB:%.*]] = fsub <2 x double> , %b +// CHECK: [[SUB:%.*]] = fneg <2 x double> %b // CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SUB]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <1 x double> %v to <8 x i8> @@ -436,7 +436,7 @@ float64x2_t test_vfmsq_lane_f64(float64x2_t a, float64x2_t b, float64x1_t v) { } // CHECK-LABEL: @test_vfmsq_laneq_f64( -// CHECK: [[SUB:%.*]] = fsub <2 x double> , %b +// CHECK: [[SUB:%.*]] = fneg <2 x double> %b // CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SUB]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v to <16 x i8> @@ -459,7 +459,7 @@ float32_t test_vfmas_laneq_f32(float32_t a, float32_t b, float32x4_t v) { } // CHECK-LABEL: @test_vfmsd_lane_f64( -// CHECK: [[SUB:%.*]] = fsub double -0.000000e+00, %b +// CHECK: [[SUB:%.*]] = fneg double %b // CHECK: [[EXTRACT:%.*]] = extractelement <1 x double> %v, i32 0 // CHECK: [[TMP2:%.*]] = call double @llvm.fma.f64(double [[SUB]], double [[EXTRACT]], double %a) // CHECK: ret double [[TMP2]] @@ -468,7 +468,7 @@ float64_t test_vfmsd_lane_f64(float64_t a, float64_t b, float64x1_t v) { } // CHECK-LABEL: @test_vfmss_laneq_f32( -// CHECK: [[SUB:%.*]] = fsub float -0.000000e+00, %b +// CHECK: [[SUB:%.*]] = fneg float %b // CHECK: [[EXTRACT:%.*]] = extractelement <4 x float> %v, i32 3 // CHECK: [[TMP2:%.*]] = call float @llvm.fma.f32(float [[SUB]], float [[EXTRACT]], float %a) // CHECK: ret float [[TMP2]] @@ -477,7 +477,7 @@ float32_t test_vfmss_laneq_f32(float32_t a, float32_t b, float32x4_t v) { } // CHECK-LABEL: @test_vfmsd_laneq_f64( -// CHECK: [[SUB:%.*]] = fsub double -0.000000e+00, %b +// CHECK: [[SUB:%.*]] = fneg double %b // CHECK: [[EXTRACT:%.*]] = extractelement <2 x double> %v, i32 1 // CHECK: [[TMP2:%.*]] = call double @llvm.fma.f64(double [[SUB]], double [[EXTRACT]], double %a) // CHECK: ret double [[TMP2]] @@ -1767,7 +1767,7 @@ float32x4_t test_vfmaq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v) } // CHECK-LABEL: @test_vfms_lane_f32_0( -// CHECK: [[SUB:%.*]] = fsub <2 x float> , %b +// CHECK: [[SUB:%.*]] = fneg <2 x float> %b // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> @@ -1782,7 +1782,7 @@ float32x2_t test_vfms_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) { } // CHECK-LABEL: @test_vfmsq_lane_f32_0( -// CHECK: [[SUB:%.*]] = fsub <4 x float> , %b +// CHECK: [[SUB:%.*]] = fneg <4 x float> %b // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8> @@ -1797,7 +1797,7 @@ float32x4_t test_vfmsq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) { } // CHECK-LABEL: @test_vfms_laneq_f32_0( -// CHECK: [[SUB:%.*]] = fsub <2 x float> , %b +// CHECK: [[SUB:%.*]] = fneg <2 x float> %b // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> @@ -1812,7 +1812,7 @@ float32x2_t test_vfms_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) { } // CHECK-LABEL: @test_vfmsq_laneq_f32_0( -// CHECK: [[SUB:%.*]] = fsub <4 x float> , %b +// CHECK: [[SUB:%.*]] = fneg <4 x float> %b // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8> @@ -1841,7 +1841,7 @@ float64x2_t test_vfmaq_laneq_f64_0(float64x2_t a, float64x2_t b, float64x2_t v) } // CHECK-LABEL: @test_vfmsq_laneq_f64_0( -// CHECK: [[SUB:%.*]] = fsub <2 x double> , %b +// CHECK: [[SUB:%.*]] = fneg <2 x double> %b // CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SUB]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v to <16 x i8> @@ -3101,7 +3101,7 @@ float32x4_t test_vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n) { } // CHECK-LABEL: @test_vfms_n_f32( -// CHECK: [[SUB_I:%.*]] = fsub <2 x float> , %b +// CHECK: [[SUB_I:%.*]] = fneg <2 x float> %b // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %n, i32 1 // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> @@ -3114,7 +3114,7 @@ float32x2_t test_vfms_n_f32(float32x2_t a, float32x2_t b, float32_t n) { } // CHECK-LABEL: @test_vfms_n_f64( -// CHECK: [[SUB_I:%.*]] = fsub <1 x double> , %b +// CHECK: [[SUB_I:%.*]] = fneg <1 x double> %b // CHECK: [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, i32 0 // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x double> [[SUB_I]] to <8 x i8> @@ -3126,7 +3126,7 @@ float64x1_t test_vfms_n_f64(float64x1_t a, float64x1_t b, float64_t n) { } // CHECK-LABEL: @test_vfmsq_n_f32( -// CHECK: [[SUB_I:%.*]] = fsub <4 x float> , %b +// CHECK: [[SUB_I:%.*]] = fneg <4 x float> %b // CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1 // CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %n, i32 2 diff --git a/clang/test/CodeGen/aarch64-neon-fma.c b/clang/test/CodeGen/aarch64-neon-fma.c index 564bd37e7895..ae02bfbffb98 100644 --- a/clang/test/CodeGen/aarch64-neon-fma.c +++ b/clang/test/CodeGen/aarch64-neon-fma.c @@ -221,7 +221,7 @@ float64x2_t test_vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) { } // CHECK-LABEL: define <2 x double> @test_vfmsq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 { -// CHECK: [[SUB_I:%.*]] = fsub <2 x double> , %b +// CHECK: [[SUB_I:%.*]] = fneg <2 x double> %b // CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0 // CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1 // CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[SUB_I]], <2 x double> [[VECINIT1_I]], <2 x double> %a) #3 diff --git a/clang/test/CodeGen/aarch64-neon-intrinsics.c b/clang/test/CodeGen/aarch64-neon-intrinsics.c index 2eddd03786a5..dcb48b05262f 100644 --- a/clang/test/CodeGen/aarch64-neon-intrinsics.c +++ b/clang/test/CodeGen/aarch64-neon-intrinsics.c @@ -665,7 +665,7 @@ float64x2_t test_vfmaq_f64(float64x2_t v1, float64x2_t v2, float64x2_t v3) { } // CHECK-LABEL: @test_vfms_f32( -// CHECK: [[SUB_I:%.*]] = fsub <2 x float> , %v2 +// CHECK: [[SUB_I:%.*]] = fneg <2 x float> %v2 // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %v1 to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB_I]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v3 to <8 x i8> @@ -676,7 +676,7 @@ float32x2_t test_vfms_f32(float32x2_t v1, float32x2_t v2, float32x2_t v3) { } // CHECK-LABEL: @test_vfmsq_f32( -// CHECK: [[SUB_I:%.*]] = fsub <4 x float> , %v2 +// CHECK: [[SUB_I:%.*]] = fneg <4 x float> %v2 // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %v1 to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB_I]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v3 to <16 x i8> @@ -687,7 +687,7 @@ float32x4_t test_vfmsq_f32(float32x4_t v1, float32x4_t v2, float32x4_t v3) { } // CHECK-LABEL: @test_vfmsq_f64( -// CHECK: [[SUB_I:%.*]] = fsub <2 x double> , %v2 +// CHECK: [[SUB_I:%.*]] = fneg <2 x double> %v2 // CHECK: [[TMP0:%.*]] = bitcast <2 x double> %v1 to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SUB_I]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v3 to <16 x i8> @@ -17844,7 +17844,7 @@ float64x1_t test_vfma_f64(float64x1_t a, float64x1_t b, float64x1_t c) { } // CHECK-LABEL: @test_vfms_f64( -// CHECK: [[SUB_I:%.*]] = fsub <1 x double> , %b +// CHECK: [[SUB_I:%.*]] = fneg <1 x double> %b // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x double> [[SUB_I]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <1 x double> %c to <8 x i8> @@ -17915,7 +17915,7 @@ float64x1_t test_vabs_f64(float64x1_t a) { } // CHECK-LABEL: @test_vneg_f64( -// CHECK: [[SUB_I:%.*]] = fsub <1 x double> , %a +// CHECK: [[SUB_I:%.*]] = fneg <1 x double> %a // CHECK: ret <1 x double> [[SUB_I]] float64x1_t test_vneg_f64(float64x1_t a) { return vneg_f64(a); diff --git a/clang/test/CodeGen/aarch64-neon-misc.c b/clang/test/CodeGen/aarch64-neon-misc.c index f8ba7ee7121b..acc3c0b7d2d4 100644 --- a/clang/test/CodeGen/aarch64-neon-misc.c +++ b/clang/test/CodeGen/aarch64-neon-misc.c @@ -1286,21 +1286,21 @@ int64x2_t test_vnegq_s64(int64x2_t a) { } // CHECK-LABEL: @test_vneg_f32( -// CHECK: [[SUB_I:%.*]] = fsub <2 x float> , %a +// CHECK: [[SUB_I:%.*]] = fneg <2 x float> %a // CHECK: ret <2 x float> [[SUB_I]] float32x2_t test_vneg_f32(float32x2_t a) { return vneg_f32(a); } // CHECK-LABEL: @test_vnegq_f32( -// CHECK: [[SUB_I:%.*]] = fsub <4 x float> , %a +// CHECK: [[SUB_I:%.*]] = fneg <4 x float> %a // CHECK: ret <4 x float> [[SUB_I]] float32x4_t test_vnegq_f32(float32x4_t a) { return vnegq_f32(a); } // CHECK-LABEL: @test_vnegq_f64( -// CHECK: [[SUB_I:%.*]] = fsub <2 x double> , %a +// CHECK: [[SUB_I:%.*]] = fneg <2 x double> %a // CHECK: ret <2 x double> [[SUB_I]] float64x2_t test_vnegq_f64(float64x2_t a) { return vnegq_f64(a); diff --git a/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c b/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c index 5ec2555055b2..836e4dbd9917 100644 --- a/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c +++ b/clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c @@ -136,7 +136,7 @@ float64_t test_vfmad_laneq_f64(float64_t a, float64_t b, float64x2_t c) { } // CHECK-LABEL: define float @test_vfmss_lane_f32(float %a, float %b, <2 x float> %c) #0 { -// CHECK: [[SUB:%.*]] = fsub float -0.000000e+00, %b +// CHECK: [[SUB:%.*]] = fneg float %b // CHECK: [[EXTRACT:%.*]] = extractelement <2 x float> %c, i32 1 // CHECK: [[TMP2:%.*]] = call float @llvm.fma.f32(float [[SUB]], float [[EXTRACT]], float %a) // CHECK: ret float [[TMP2]] @@ -159,7 +159,7 @@ float64x1_t test_vfma_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v) { } // CHECK-LABEL: define <1 x double> @test_vfms_lane_f64(<1 x double> %a, <1 x double> %b, <1 x double> %v) #0 { -// CHECK: [[SUB:%.*]] = fsub <1 x double> , %b +// CHECK: [[SUB:%.*]] = fneg <1 x double> %b // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x double> [[SUB]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <1 x double> %v to <8 x i8> @@ -189,7 +189,7 @@ float64x1_t test_vfma_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v) { } // CHECK-LABEL: define <1 x double> @test_vfms_laneq_f64(<1 x double> %a, <1 x double> %b, <2 x double> %v) #1 { -// CHECK: [[SUB:%.*]] = fsub <1 x double> , %b +// CHECK: [[SUB:%.*]] = fneg <1 x double> %b // CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <1 x double> [[SUB]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v to <16 x i8> diff --git a/clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c b/clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c index b8e1f92a2579..45b18453b89d 100644 --- a/clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c +++ b/clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c @@ -315,7 +315,7 @@ uint64_t test_vcvtph_u64_f16 (float16_t a) { } // CHECK-LABEL: test_vnegh_f16 -// CHECK: [[NEG:%.*]] = fsub half 0xH8000, %a +// CHECK: [[NEG:%.*]] = fneg half %a // CHECK: ret half [[NEG]] float16_t test_vnegh_f16(float16_t a) { return vnegh_f16(a); diff --git a/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c b/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c index de1dd4a05977..47e2fafd1ad3 100644 --- a/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c +++ b/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c @@ -264,14 +264,14 @@ uint16x8_t test_vcvtpq_u16_f16 (float16x8_t a) { // FIXME: Fix the zero constant when fp16 non-storage-only type becomes available. // CHECK-LABEL: test_vneg_f16 -// CHECK: [[NEG:%.*]] = fsub <4 x half> , %a +// CHECK: [[NEG:%.*]] = fneg <4 x half> %a // CHECK: ret <4 x half> [[NEG]] float16x4_t test_vneg_f16(float16x4_t a) { return vneg_f16(a); } // CHECK-LABEL: test_vnegq_f16 -// CHECK: [[NEG:%.*]] = fsub <8 x half> , %a +// CHECK: [[NEG:%.*]] = fneg <8 x half> %a // CHECK: ret <8 x half> [[NEG]] float16x8_t test_vnegq_f16(float16x8_t a) { return vnegq_f16(a); @@ -862,7 +862,7 @@ float16x8_t test_vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c) { } // CHECK-LABEL: test_vfms_f16 -// CHECK: [[SUB:%.*]] = fsub <4 x half> , %b +// CHECK: [[SUB:%.*]] = fneg <4 x half> %b // CHECK: [[ADD:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[SUB]], <4 x half> %c, <4 x half> %a) // CHECK: ret <4 x half> [[ADD]] float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) { @@ -870,7 +870,7 @@ float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) { } // CHECK-LABEL: test_vfmsq_f16 -// CHECK: [[SUB:%.*]] = fsub <8 x half> , %b +// CHECK: [[SUB:%.*]] = fneg <8 x half> %b // CHECK: [[ADD:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[SUB]], <8 x half> %c, <8 x half> %a) // CHECK: ret <8 x half> [[ADD]] float16x8_t test_vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c) { @@ -976,7 +976,7 @@ float16_t test_vfmah_laneq_f16(float16_t a, float16_t b, float16x8_t c) { } // CHECK-LABEL: test_vfms_lane_f16 -// CHECK: [[SUB:%.*]] = fsub <4 x half> , %b +// CHECK: [[SUB:%.*]] = fneg <4 x half> %b // CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x half> [[SUB]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8> @@ -991,7 +991,7 @@ float16x4_t test_vfms_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) { } // CHECK-LABEL: test_vfmsq_lane_f16 -// CHECK: [[SUB:%.*]] = fsub <8 x half> , %b +// CHECK: [[SUB:%.*]] = fneg <8 x half> %b // CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x half> [[SUB]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8> @@ -1006,7 +1006,7 @@ float16x8_t test_vfmsq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) { } // CHECK-LABEL: test_vfms_laneq_f16 -// CHECK: [[SUB:%.*]] = fsub <4 x half> , %b +// CHECK: [[SUB:%.*]] = fneg <4 x half> %b // CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x half> [[SUB]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8> @@ -1021,7 +1021,7 @@ float16x4_t test_vfms_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) { } // CHECK-LABEL: test_vfmsq_laneq_f16 -// CHECK: [[SUB:%.*]] = fsub <8 x half> , %b +// CHECK: [[SUB:%.*]] = fneg <8 x half> %b // CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <8 x half> [[SUB]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8> @@ -1036,7 +1036,7 @@ float16x8_t test_vfmsq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) { } // CHECK-LABEL: test_vfms_n_f16 -// CHECK: [[SUB:%.*]] = fsub <4 x half> , %b +// CHECK: [[SUB:%.*]] = fneg <4 x half> %b // CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %c, i32 0 // CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %c, i32 1 // CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %c, i32 2 @@ -1048,7 +1048,7 @@ float16x4_t test_vfms_n_f16(float16x4_t a, float16x4_t b, float16_t c) { } // CHECK-LABEL: test_vfmsq_n_f16 -// CHECK: [[SUB:%.*]] = fsub <8 x half> , %b +// CHECK: [[SUB:%.*]] = fneg <8 x half> %b // CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %c, i32 0 // CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %c, i32 1 // CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %c, i32 2 @@ -1065,7 +1065,7 @@ float16x8_t test_vfmsq_n_f16(float16x8_t a, float16x8_t b, float16_t c) { // CHECK-LABEL: test_vfmsh_lane_f16 // CHECK: [[TMP0:%.*]] = fpext half %b to float -// CHECK: [[TMP1:%.*]] = fsub float -0.000000e+00, [[TMP0]] +// CHECK: [[TMP1:%.*]] = fneg float [[TMP0]] // CHECK: [[SUB:%.*]] = fptrunc float [[TMP1]] to half // CHECK: [[EXTR:%.*]] = extractelement <4 x half> %c, i32 3 // CHECK: [[FMA:%.*]] = call half @llvm.fma.f16(half [[SUB]], half [[EXTR]], half %a) @@ -1076,7 +1076,7 @@ float16_t test_vfmsh_lane_f16(float16_t a, float16_t b, float16x4_t c) { // CHECK-LABEL: test_vfmsh_laneq_f16 // CHECK: [[TMP0:%.*]] = fpext half %b to float -// CHECK: [[TMP1:%.*]] = fsub float -0.000000e+00, [[TMP0]] +// CHECK: [[TMP1:%.*]] = fneg float [[TMP0]] // CHECK: [[SUB:%.*]] = fptrunc float [[TMP1]] to half // CHECK: [[EXTR:%.*]] = extractelement <8 x half> %c, i32 7 // CHECK: [[FMA:%.*]] = call half @llvm.fma.f16(half [[SUB]], half [[EXTR]], half %a) diff --git a/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c b/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c index 58d911d3ff70..4b48ba01c4bc 100644 --- a/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c +++ b/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c @@ -264,14 +264,14 @@ uint16x8_t test_vcvtpq_u16_f16 (float16x8_t a) { // FIXME: Fix the zero constant when fp16 non-storage-only type becomes available. // CHECK-LABEL: test_vneg_f16 -// CHECK: [[NEG:%.*]] = fsub <4 x half> , %a +// CHECK: [[NEG:%.*]] = fneg <4 x half> %a // CHECK: ret <4 x half> [[NEG]] float16x4_t test_vneg_f16(float16x4_t a) { return vneg_f16(a); } // CHECK-LABEL: test_vnegq_f16 -// CHECK: [[NEG:%.*]] = fsub <8 x half> , %a +// CHECK: [[NEG:%.*]] = fneg <8 x half> %a // CHECK: ret <8 x half> [[NEG]] float16x8_t test_vnegq_f16(float16x8_t a) { return vnegq_f16(a); @@ -757,7 +757,7 @@ float16x8_t test_vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c) { } // CHECK-LABEL: test_vfms_f16 -// CHECK: [[SUB:%.*]] = fsub <4 x half> , %b +// CHECK: [[SUB:%.*]] = fneg <4 x half> %b // CHECK: [[ADD:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[SUB]], <4 x half> %c, <4 x half> %a) // CHECK: ret <4 x half> [[ADD]] float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) { @@ -765,7 +765,7 @@ float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) { } // CHECK-LABEL: test_vfmsq_f16 -// CHECK: [[SUB:%.*]] = fsub <8 x half> , %b +// CHECK: [[SUB:%.*]] = fneg <8 x half> %b // CHECK: [[ADD:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[SUB]], <8 x half> %c, <8 x half> %a) // CHECK: ret <8 x half> [[ADD]] float16x8_t test_vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c) { diff --git a/clang/test/CodeGen/arm_neon_intrinsics.c b/clang/test/CodeGen/arm_neon_intrinsics.c index b09e63883e26..0c1c03800a70 100644 --- a/clang/test/CodeGen/arm_neon_intrinsics.c +++ b/clang/test/CodeGen/arm_neon_intrinsics.c @@ -3206,7 +3206,7 @@ float32x4_t test_vfmaq_f32(float32x4_t a, float32x4_t b, float32x4_t c) { } // CHECK-LABEL: @test_vfms_f32( -// CHECK: [[SUB_I:%.*]] = fsub <2 x float> , %b +// CHECK: [[SUB_I:%.*]] = fneg <2 x float> %b // CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8> // CHECK: [[TMP1:%.*]] = bitcast <2 x float> [[SUB_I]] to <8 x i8> // CHECK: [[TMP2:%.*]] = bitcast <2 x float> %c to <8 x i8> @@ -3217,7 +3217,7 @@ float32x2_t test_vfms_f32(float32x2_t a, float32x2_t b, float32x2_t c) { } // CHECK-LABEL: @test_vfmsq_f32( -// CHECK: [[SUB_I:%.*]] = fsub <4 x float> , %b +// CHECK: [[SUB_I:%.*]] = fneg <4 x float> %b // CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8> // CHECK: [[TMP1:%.*]] = bitcast <4 x float> [[SUB_I]] to <16 x i8> // CHECK: [[TMP2:%.*]] = bitcast <4 x float> %c to <16 x i8> @@ -8809,7 +8809,7 @@ int32x2_t test_vneg_s32(int32x2_t a) { } // CHECK-LABEL: @test_vneg_f32( -// CHECK: [[SUB_I:%.*]] = fsub <2 x float> , %a +// CHECK: [[SUB_I:%.*]] = fneg <2 x float> %a // CHECK: ret <2 x float> [[SUB_I]] float32x2_t test_vneg_f32(float32x2_t a) { return vneg_f32(a); @@ -8837,7 +8837,7 @@ int32x4_t test_vnegq_s32(int32x4_t a) { } // CHECK-LABEL: @test_vnegq_f32( -// CHECK: [[SUB_I:%.*]] = fsub <4 x float> , %a +// CHECK: [[SUB_I:%.*]] = fneg <4 x float> %a // CHECK: ret <4 x float> [[SUB_I]] float32x4_t test_vnegq_f32(float32x4_t a) { return vnegq_f32(a); diff --git a/clang/test/CodeGen/avx512f-builtins.c b/clang/test/CodeGen/avx512f-builtins.c index 73a093c54683..9296108f01b1 100644 --- a/clang/test/CodeGen/avx512f-builtins.c +++ b/clang/test/CodeGen/avx512f-builtins.c @@ -523,13 +523,13 @@ __m512d test_mm512_maskz_fmadd_round_pd(__mmask8 __U, __m512d __A, __m512d __B, } __m512d test_mm512_fmsub_round_pd(__m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_fmsub_round_pd - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 return _mm512_fmsub_round_pd(__A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); } __m512d test_mm512_mask_fmsub_round_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_mask_fmsub_round_pd - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -537,7 +537,7 @@ __m512d test_mm512_mask_fmsub_round_pd(__m512d __A, __mmask8 __U, __m512d __B, _ } __m512d test_mm512_maskz_fmsub_round_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_maskz_fmsub_round_pd - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer @@ -545,13 +545,13 @@ __m512d test_mm512_maskz_fmsub_round_pd(__mmask8 __U, __m512d __A, __m512d __B, } __m512d test_mm512_fnmadd_round_pd(__m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_fnmadd_round_pd - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 return _mm512_fnmadd_round_pd(__A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); } __m512d test_mm512_mask3_fnmadd_round_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmadd_round_pd - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -559,7 +559,7 @@ __m512d test_mm512_mask3_fnmadd_round_pd(__m512d __A, __m512d __B, __m512d __C, } __m512d test_mm512_maskz_fnmadd_round_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_maskz_fnmadd_round_pd - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer @@ -567,15 +567,15 @@ __m512d test_mm512_maskz_fnmadd_round_pd(__mmask8 __U, __m512d __A, __m512d __B, } __m512d test_mm512_fnmsub_round_pd(__m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_fnmsub_round_pd - // CHECK: fsub <8 x double> - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 return _mm512_fnmsub_round_pd(__A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); } __m512d test_mm512_maskz_fnmsub_round_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_maskz_fnmsub_round_pd - // CHECK: fsub <8 x double> - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer @@ -609,13 +609,13 @@ __m512d test_mm512_maskz_fmadd_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512 } __m512d test_mm512_fmsub_pd(__m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_fmsub_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) return _mm512_fmsub_pd(__A, __B, __C); } __m512d test_mm512_mask_fmsub_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_mask_fmsub_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -623,7 +623,7 @@ __m512d test_mm512_mask_fmsub_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d } __m512d test_mm512_maskz_fmsub_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_maskz_fmsub_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer @@ -631,13 +631,13 @@ __m512d test_mm512_maskz_fmsub_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512 } __m512d test_mm512_fnmadd_pd(__m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_fnmadd_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) return _mm512_fnmadd_pd(__A, __B, __C); } __m512d test_mm512_mask3_fnmadd_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmadd_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -645,7 +645,7 @@ __m512d test_mm512_mask3_fnmadd_pd(__m512d __A, __m512d __B, __m512d __C, __mmas } __m512d test_mm512_maskz_fnmadd_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_maskz_fnmadd_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer @@ -653,15 +653,15 @@ __m512d test_mm512_maskz_fnmadd_pd(__mmask8 __U, __m512d __A, __m512d __B, __m51 } __m512d test_mm512_fnmsub_pd(__m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_fnmsub_pd - // CHECK: fsub <8 x double> , %{{.*}} - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) return _mm512_fnmsub_pd(__A, __B, __C); } __m512d test_mm512_maskz_fnmsub_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_maskz_fnmsub_pd - // CHECK: fsub <8 x double> , %{{.*}} - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer @@ -695,13 +695,13 @@ __m512 test_mm512_maskz_fmadd_round_ps(__mmask16 __U, __m512 __A, __m512 __B, __ } __m512 test_mm512_fmsub_round_ps(__m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_fmsub_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 return _mm512_fmsub_round_ps(__A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); } __m512 test_mm512_mask_fmsub_round_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_mask_fmsub_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -709,7 +709,7 @@ __m512 test_mm512_mask_fmsub_round_ps(__m512 __A, __mmask16 __U, __m512 __B, __m } __m512 test_mm512_maskz_fmsub_round_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_maskz_fmsub_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer @@ -717,13 +717,13 @@ __m512 test_mm512_maskz_fmsub_round_ps(__mmask16 __U, __m512 __A, __m512 __B, __ } __m512 test_mm512_fnmadd_round_ps(__m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_fnmadd_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 return _mm512_fnmadd_round_ps(__A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); } __m512 test_mm512_mask3_fnmadd_round_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmadd_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -731,7 +731,7 @@ __m512 test_mm512_mask3_fnmadd_round_ps(__m512 __A, __m512 __B, __m512 __C, __mm } __m512 test_mm512_maskz_fnmadd_round_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_maskz_fnmadd_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer @@ -739,15 +739,15 @@ __m512 test_mm512_maskz_fnmadd_round_ps(__mmask16 __U, __m512 __A, __m512 __B, _ } __m512 test_mm512_fnmsub_round_ps(__m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_fnmsub_round_ps - // CHECK: fsub <16 x float> , %{{.*}} - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 return _mm512_fnmsub_round_ps(__A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); } __m512 test_mm512_maskz_fnmsub_round_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_maskz_fnmsub_round_ps - // CHECK: fsub <16 x float> , %{{.*}} - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer @@ -779,13 +779,13 @@ __m512 test_mm512_maskz_fmadd_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 _ } __m512 test_mm512_fmsub_ps(__m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_fmsub_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) return _mm512_fmsub_ps(__A, __B, __C); } __m512 test_mm512_mask_fmsub_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_mask_fmsub_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -793,7 +793,7 @@ __m512 test_mm512_mask_fmsub_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __ } __m512 test_mm512_maskz_fmsub_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_maskz_fmsub_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer @@ -801,13 +801,13 @@ __m512 test_mm512_maskz_fmsub_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 _ } __m512 test_mm512_fnmadd_ps(__m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_fnmadd_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) return _mm512_fnmadd_ps(__A, __B, __C); } __m512 test_mm512_mask3_fnmadd_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmadd_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -815,7 +815,7 @@ __m512 test_mm512_mask3_fnmadd_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 } __m512 test_mm512_maskz_fnmadd_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_maskz_fnmadd_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer @@ -823,15 +823,15 @@ __m512 test_mm512_maskz_fnmadd_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 } __m512 test_mm512_fnmsub_ps(__m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_fnmsub_ps - // CHECK: fsub <16 x float> , %{{.*}} - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) return _mm512_fnmsub_ps(__A, __B, __C); } __m512 test_mm512_maskz_fnmsub_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_maskz_fnmsub_ps - // CHECK: fsub <16 x float> , %{{.*}} - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer @@ -865,13 +865,13 @@ __m512d test_mm512_maskz_fmaddsub_round_pd(__mmask8 __U, __m512d __A, __m512d __ } __m512d test_mm512_fmsubadd_round_pd(__m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_fmsubadd_round_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: @llvm.x86.avx512.vfmaddsub.pd.512 return _mm512_fmsubadd_round_pd(__A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); } __m512d test_mm512_mask_fmsubadd_round_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_mask_fmsubadd_round_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: @llvm.x86.avx512.vfmaddsub.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -879,7 +879,7 @@ __m512d test_mm512_mask_fmsubadd_round_pd(__m512d __A, __mmask8 __U, __m512d __B } __m512d test_mm512_maskz_fmsubadd_round_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_maskz_fmsubadd_round_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: @llvm.x86.avx512.vfmaddsub.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer @@ -888,7 +888,7 @@ __m512d test_mm512_maskz_fmsubadd_round_pd(__mmask8 __U, __m512d __A, __m512d __ __m512d test_mm512_fmaddsub_pd(__m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: shufflevector <8 x double> [[SUB]], <8 x double> [[ADD]], <8 x i32> return _mm512_fmaddsub_pd(__A, __B, __C); @@ -896,7 +896,7 @@ __m512d test_mm512_fmaddsub_pd(__m512d __A, __m512d __B, __m512d __C) { __m512d test_mm512_mask_fmaddsub_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_mask_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: shufflevector <8 x double> [[SUB]], <8 x double> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -906,7 +906,7 @@ __m512d test_mm512_mask_fmaddsub_pd(__m512d __A, __mmask8 __U, __m512d __B, __m5 __m512d test_mm512_mask3_fmaddsub_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: shufflevector <8 x double> [[SUB]], <8 x double> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -916,7 +916,7 @@ __m512d test_mm512_mask3_fmaddsub_pd(__m512d __A, __m512d __B, __m512d __C, __mm __m512d test_mm512_maskz_fmaddsub_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_maskz_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: shufflevector <8 x double> [[SUB]], <8 x double> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -925,7 +925,7 @@ __m512d test_mm512_maskz_fmaddsub_pd(__mmask8 __U, __m512d __A, __m512d __B, __m } __m512d test_mm512_fmsubadd_pd(__m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: shufflevector <8 x double> [[ADD]], <8 x double> [[SUB]], <8 x i32> @@ -933,7 +933,7 @@ __m512d test_mm512_fmsubadd_pd(__m512d __A, __m512d __B, __m512d __C) { } __m512d test_mm512_mask_fmsubadd_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_mask_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: shufflevector <8 x double> [[ADD]], <8 x double> [[SUB]], <8 x i32> @@ -943,7 +943,7 @@ __m512d test_mm512_mask_fmsubadd_pd(__m512d __A, __mmask8 __U, __m512d __B, __m5 } __m512d test_mm512_maskz_fmsubadd_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_maskz_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: shufflevector <8 x double> [[ADD]], <8 x double> [[SUB]], <8 x i32> @@ -979,13 +979,13 @@ __m512 test_mm512_maskz_fmaddsub_round_ps(__mmask16 __U, __m512 __A, __m512 __B, } __m512 test_mm512_fmsubadd_round_ps(__m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_fmsubadd_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmaddsub.ps.512 return _mm512_fmsubadd_round_ps(__A, __B, __C, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC); } __m512 test_mm512_mask_fmsubadd_round_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_mask_fmsubadd_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmaddsub.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -993,7 +993,7 @@ __m512 test_mm512_mask_fmsubadd_round_ps(__m512 __A, __mmask16 __U, __m512 __B, } __m512 test_mm512_maskz_fmsubadd_round_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_maskz_fmsubadd_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmaddsub.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer @@ -1002,7 +1002,7 @@ __m512 test_mm512_maskz_fmsubadd_round_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 test_mm512_fmaddsub_ps(__m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: shufflevector <16 x float> [[SUB]], <16 x float> [[ADD]], <16 x i32> return _mm512_fmaddsub_ps(__A, __B, __C); @@ -1010,7 +1010,7 @@ __m512 test_mm512_fmaddsub_ps(__m512 __A, __m512 __B, __m512 __C) { __m512 test_mm512_mask_fmaddsub_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_mask_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: shufflevector <16 x float> [[SUB]], <16 x float> [[ADD]], <16 x i32> // CHECK: bitcast i16 %{{.*}} to <16 x i1> @@ -1020,7 +1020,7 @@ __m512 test_mm512_mask_fmaddsub_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __m512 test_mm512_mask3_fmaddsub_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: shufflevector <16 x float> [[SUB]], <16 x float> [[ADD]], <16 x i32> // CHECK: bitcast i16 %{{.*}} to <16 x i1> @@ -1030,7 +1030,7 @@ __m512 test_mm512_mask3_fmaddsub_ps(__m512 __A, __m512 __B, __m512 __C, __mmask1 __m512 test_mm512_maskz_fmaddsub_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_maskz_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: shufflevector <16 x float> [[SUB]], <16 x float> [[ADD]], <16 x i32> // CHECK: bitcast i16 %{{.*}} to <16 x i1> @@ -1039,7 +1039,7 @@ __m512 test_mm512_maskz_fmaddsub_ps(__mmask16 __U, __m512 __A, __m512 __B, __m51 } __m512 test_mm512_fmsubadd_ps(__m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: shufflevector <16 x float> [[ADD]], <16 x float> [[SUB]], <16 x i32> @@ -1047,7 +1047,7 @@ __m512 test_mm512_fmsubadd_ps(__m512 __A, __m512 __B, __m512 __C) { } __m512 test_mm512_mask_fmsubadd_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_mask_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: shufflevector <16 x float> [[ADD]], <16 x float> [[SUB]], <16 x i32> @@ -1057,7 +1057,7 @@ __m512 test_mm512_mask_fmsubadd_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 } __m512 test_mm512_maskz_fmsubadd_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_maskz_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: shufflevector <16 x float> [[ADD]], <16 x float> [[SUB]], <16 x i32> @@ -1067,7 +1067,7 @@ __m512 test_mm512_maskz_fmsubadd_ps(__mmask16 __U, __m512 __A, __m512 __B, __m51 } __m512d test_mm512_mask3_fmsub_round_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsub_round_pd - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1075,7 +1075,7 @@ __m512d test_mm512_mask3_fmsub_round_pd(__m512d __A, __m512d __B, __m512d __C, _ } __m512d test_mm512_mask3_fmsub_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsub_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1083,7 +1083,7 @@ __m512d test_mm512_mask3_fmsub_pd(__m512d __A, __m512d __B, __m512d __C, __mmask } __m512 test_mm512_mask3_fmsub_round_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsub_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1091,7 +1091,7 @@ __m512 test_mm512_mask3_fmsub_round_ps(__m512 __A, __m512 __B, __m512 __C, __mma } __m512 test_mm512_mask3_fmsub_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsub_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1099,7 +1099,7 @@ __m512 test_mm512_mask3_fmsub_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 _ } __m512d test_mm512_mask3_fmsubadd_round_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsubadd_round_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: @llvm.x86.avx512.vfmaddsub.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1107,7 +1107,7 @@ __m512d test_mm512_mask3_fmsubadd_round_pd(__m512d __A, __m512d __B, __m512d __C } __m512d test_mm512_mask3_fmsubadd_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <8 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x double> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: shufflevector <8 x double> [[ADD]], <8 x double> [[SUB]], <8 x i32> @@ -1117,7 +1117,7 @@ __m512d test_mm512_mask3_fmsubadd_pd(__m512d __A, __m512d __B, __m512d __C, __mm } __m512 test_mm512_mask3_fmsubadd_round_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsubadd_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmaddsub.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1125,7 +1125,7 @@ __m512 test_mm512_mask3_fmsubadd_round_ps(__m512 __A, __m512 __B, __m512 __C, __ } __m512 test_mm512_mask3_fmsubadd_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <16 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <16 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: shufflevector <16 x float> [[ADD]], <16 x float> [[SUB]], <16 x i32> @@ -1135,7 +1135,7 @@ __m512 test_mm512_mask3_fmsubadd_ps(__m512 __A, __m512 __B, __m512 __C, __mmask1 } __m512d test_mm512_mask_fnmadd_round_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_mask_fnmadd_round_pd - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1143,7 +1143,7 @@ __m512d test_mm512_mask_fnmadd_round_pd(__m512d __A, __mmask8 __U, __m512d __B, } __m512d test_mm512_mask_fnmadd_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_mask_fnmadd_pd - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1151,7 +1151,7 @@ __m512d test_mm512_mask_fnmadd_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512 } __m512 test_mm512_mask_fnmadd_round_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_mask_fnmadd_round_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1159,7 +1159,7 @@ __m512 test_mm512_mask_fnmadd_round_ps(__m512 __A, __mmask16 __U, __m512 __B, __ } __m512 test_mm512_mask_fnmadd_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_mask_fnmadd_ps - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1167,8 +1167,8 @@ __m512 test_mm512_mask_fnmadd_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 _ } __m512d test_mm512_mask_fnmsub_round_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_mask_fnmsub_round_pd - // CHECK: fsub <8 x double> - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1176,8 +1176,8 @@ __m512d test_mm512_mask_fnmsub_round_pd(__m512d __A, __mmask8 __U, __m512d __B, } __m512d test_mm512_mask3_fnmsub_round_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmsub_round_pd - // CHECK: fsub <8 x double> - // CHECK: fsub <8 x double> + // CHECK: fneg <8 x double> + // CHECK: fneg <8 x double> // CHECK: @llvm.x86.avx512.vfmadd.pd.512 // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1185,8 +1185,8 @@ __m512d test_mm512_mask3_fnmsub_round_pd(__m512d __A, __m512d __B, __m512d __C, } __m512d test_mm512_mask_fnmsub_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512d __C) { // CHECK-LABEL: @test_mm512_mask_fnmsub_pd - // CHECK: fsub <8 x double> , %{{.*}} - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1194,8 +1194,8 @@ __m512d test_mm512_mask_fnmsub_pd(__m512d __A, __mmask8 __U, __m512d __B, __m512 } __m512d test_mm512_mask3_fnmsub_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmsub_pd - // CHECK: fsub <8 x double> , %{{.*}} - // CHECK: fsub <8 x double> , %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} + // CHECK: fneg <8 x double> %{{.*}} // CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}} @@ -1203,8 +1203,8 @@ __m512d test_mm512_mask3_fnmsub_pd(__m512d __A, __m512d __B, __m512d __C, __mmas } __m512 test_mm512_mask_fnmsub_round_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_mask_fnmsub_round_ps - // CHECK: fsub <16 x float> , %{{.*}} - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1212,8 +1212,8 @@ __m512 test_mm512_mask_fnmsub_round_ps(__m512 __A, __mmask16 __U, __m512 __B, __ } __m512 test_mm512_mask3_fnmsub_round_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmsub_round_ps - // CHECK: fsub <16 x float> , %{{.*}} - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: @llvm.x86.avx512.vfmadd.ps.512 // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1221,8 +1221,8 @@ __m512 test_mm512_mask3_fnmsub_round_ps(__m512 __A, __m512 __B, __m512 __C, __mm } __m512 test_mm512_mask_fnmsub_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 __C) { // CHECK-LABEL: @test_mm512_mask_fnmsub_ps - // CHECK: fsub <16 x float> , %{{.*}} - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -1230,8 +1230,8 @@ __m512 test_mm512_mask_fnmsub_ps(__m512 __A, __mmask16 __U, __m512 __B, __m512 _ } __m512 test_mm512_mask3_fnmsub_ps(__m512 __A, __m512 __B, __m512 __C, __mmask16 __U) { // CHECK-LABEL: @test_mm512_mask3_fnmsub_ps - // CHECK: fsub <16 x float> , %{{.*}} - // CHECK: fsub <16 x float> , %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} + // CHECK: fneg <16 x float> %{{.*}} // CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}) // CHECK: bitcast i16 %{{.*}} to <16 x i1> // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}} @@ -7521,7 +7521,7 @@ __m128 test_mm_mask3_fmadd_round_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __m128 test_mm_mask_fmsub_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){ // CHECK-LABEL: @test_mm_mask_fmsub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0 @@ -7535,7 +7535,7 @@ __m128 test_mm_mask_fmsub_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){ __m128 test_mm_fmsub_round_ss(__m128 __A, __m128 __B, __m128 __C){ // CHECK-LABEL: @test_mm_fmsub_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0 @@ -7546,7 +7546,7 @@ __m128 test_mm_fmsub_round_ss(__m128 __A, __m128 __B, __m128 __C){ __m128 test_mm_mask_fmsub_round_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){ // CHECK-LABEL: @test_mm_mask_fmsub_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0 @@ -7560,7 +7560,7 @@ __m128 test_mm_mask_fmsub_round_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __m128 test_mm_maskz_fmsub_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){ // CHECK-LABEL: @test_mm_maskz_fmsub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0 @@ -7574,7 +7574,7 @@ __m128 test_mm_maskz_fmsub_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){ __m128 test_mm_maskz_fmsub_round_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){ // CHECK-LABEL: @test_mm_maskz_fmsub_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0 @@ -7588,7 +7588,7 @@ __m128 test_mm_maskz_fmsub_round_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __m128 test_mm_mask3_fmsub_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fmsub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <4 x float> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0 @@ -7603,7 +7603,7 @@ __m128 test_mm_mask3_fmsub_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ __m128 test_mm_mask3_fmsub_round_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fmsub_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <4 x float> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0 @@ -7618,7 +7618,7 @@ __m128 test_mm_mask3_fmsub_round_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __m128 test_mm_mask_fnmadd_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){ // CHECK-LABEL: @test_mm_mask_fnmadd_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 @@ -7632,7 +7632,7 @@ __m128 test_mm_mask_fnmadd_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){ __m128 test_mm_fnmadd_round_ss(__m128 __A, __m128 __B, __m128 __C){ // CHECK-LABEL: @test_mm_fnmadd_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 @@ -7643,7 +7643,7 @@ __m128 test_mm_fnmadd_round_ss(__m128 __A, __m128 __B, __m128 __C){ __m128 test_mm_mask_fnmadd_round_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){ // CHECK-LABEL: @test_mm_mask_fnmadd_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 @@ -7657,7 +7657,7 @@ __m128 test_mm_mask_fnmadd_round_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __m128 test_mm_maskz_fnmadd_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){ // CHECK-LABEL: @test_mm_maskz_fnmadd_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 @@ -7671,7 +7671,7 @@ __m128 test_mm_maskz_fnmadd_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) __m128 test_mm_maskz_fnmadd_round_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){ // CHECK-LABEL: @test_mm_maskz_fnmadd_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 @@ -7685,7 +7685,7 @@ __m128 test_mm_maskz_fnmadd_round_ss(__mmask8 __U, __m128 __A, __m128 __B, __m12 __m128 test_mm_mask3_fnmadd_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmadd_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[ORIGC:%.+]], i64 0 @@ -7699,7 +7699,7 @@ __m128 test_mm_mask3_fnmadd_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U) __m128 test_mm_mask3_fnmadd_round_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmadd_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[ORIGC:%.+]], i64 0 @@ -7713,8 +7713,8 @@ __m128 test_mm_mask3_fnmadd_round_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask __m128 test_mm_mask_fnmsub_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){ // CHECK-LABEL: @test_mm_mask_fnmsub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0 @@ -7728,8 +7728,8 @@ __m128 test_mm_mask_fnmsub_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){ __m128 test_mm_fnmsub_round_ss(__m128 __A, __m128 __B, __m128 __C){ // CHECK-LABEL: @test_mm_fnmsub_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0 @@ -7740,8 +7740,8 @@ __m128 test_mm_fnmsub_round_ss(__m128 __A, __m128 __B, __m128 __C){ __m128 test_mm_mask_fnmsub_round_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){ // CHECK-LABEL: @test_mm_mask_fnmsub_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0 @@ -7755,8 +7755,8 @@ __m128 test_mm_mask_fnmsub_round_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __m128 test_mm_maskz_fnmsub_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){ // CHECK-LABEL: @test_mm_maskz_fnmsub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0 @@ -7770,8 +7770,8 @@ __m128 test_mm_maskz_fnmsub_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) __m128 test_mm_maskz_fnmsub_round_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){ // CHECK-LABEL: @test_mm_maskz_fnmsub_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> %{{.*}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0 @@ -7785,8 +7785,8 @@ __m128 test_mm_maskz_fnmsub_round_ss(__mmask8 __U, __m128 __A, __m128 __B, __m12 __m128 test_mm_mask3_fnmsub_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmsub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0 @@ -7801,8 +7801,8 @@ __m128 test_mm_mask3_fnmsub_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U) __m128 test_mm_mask3_fnmsub_round_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmsub_round_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0 @@ -7905,7 +7905,7 @@ __m128d test_mm_mask3_fmadd_round_sd(__m128d __W, __m128d __X, __m128d __Y, __mm __m128d test_mm_mask_fmsub_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B){ // CHECK-LABEL: @test_mm_mask_fmsub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0 @@ -7919,7 +7919,7 @@ __m128d test_mm_mask_fmsub_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __ __m128d test_mm_fmsub_round_sd(__m128d __A, __m128d __B, __m128d __C){ // CHECK-LABEL: @test_mm_fmsub_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0 @@ -7930,7 +7930,7 @@ __m128d test_mm_fmsub_round_sd(__m128d __A, __m128d __B, __m128d __C){ __m128d test_mm_mask_fmsub_round_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B){ // CHECK-LABEL: @test_mm_mask_fmsub_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0 @@ -7944,7 +7944,7 @@ __m128d test_mm_mask_fmsub_round_sd(__m128d __W, __mmask8 __U, __m128d __A, __m1 __m128d test_mm_maskz_fmsub_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C){ // CHECK-LABEL: @test_mm_maskz_fmsub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0 @@ -7958,7 +7958,7 @@ __m128d test_mm_maskz_fmsub_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d _ __m128d test_mm_maskz_fmsub_round_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C){ // CHECK-LABEL: @test_mm_maskz_fmsub_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0 @@ -7972,7 +7972,7 @@ __m128d test_mm_maskz_fmsub_round_sd(__mmask8 __U, __m128d __A, __m128d __B, __m __m128d test_mm_mask3_fmsub_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fmsub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <2 x double> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0 @@ -7987,7 +7987,7 @@ __m128d test_mm_mask3_fmsub_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 _ __m128d test_mm_mask3_fmsub_round_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fmsub_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <2 x double> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0 @@ -8002,7 +8002,7 @@ __m128d test_mm_mask3_fmsub_round_sd(__m128d __W, __m128d __X, __m128d __Y, __mm __m128d test_mm_mask_fnmadd_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B){ // CHECK-LABEL: @test_mm_mask_fnmadd_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 @@ -8016,7 +8016,7 @@ __m128d test_mm_mask_fnmadd_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d _ __m128d test_mm_fnmadd_round_sd(__m128d __A, __m128d __B, __m128d __C){ // CHECK-LABEL: @test_mm_fnmadd_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 @@ -8027,7 +8027,7 @@ __m128d test_mm_fnmadd_round_sd(__m128d __A, __m128d __B, __m128d __C){ __m128d test_mm_mask_fnmadd_round_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B){ // CHECK-LABEL: @test_mm_mask_fnmadd_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 @@ -8041,7 +8041,7 @@ __m128d test_mm_mask_fnmadd_round_sd(__m128d __W, __mmask8 __U, __m128d __A, __m __m128d test_mm_maskz_fnmadd_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C){ // CHECK-LABEL: @test_mm_maskz_fnmadd_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 @@ -8055,7 +8055,7 @@ __m128d test_mm_maskz_fnmadd_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __m128d test_mm_maskz_fnmadd_round_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C){ // CHECK-LABEL: @test_mm_maskz_fnmadd_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 @@ -8069,7 +8069,7 @@ __m128d test_mm_maskz_fnmadd_round_sd(__mmask8 __U, __m128d __A, __m128d __B, __ __m128d test_mm_mask3_fnmadd_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmadd_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[ORIGC:%.+]], i64 0 @@ -8083,7 +8083,7 @@ __m128d test_mm_mask3_fnmadd_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __m128d test_mm_mask3_fnmadd_round_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmadd_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[ORIGC:%.+]], i64 0 @@ -8097,8 +8097,8 @@ __m128d test_mm_mask3_fnmadd_round_sd(__m128d __W, __m128d __X, __m128d __Y, __m __m128d test_mm_mask_fnmsub_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B){ // CHECK-LABEL: @test_mm_mask_fnmsub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0 @@ -8112,8 +8112,8 @@ __m128d test_mm_mask_fnmsub_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d _ __m128d test_mm_fnmsub_round_sd(__m128d __A, __m128d __B, __m128d __C){ // CHECK-LABEL: @test_mm_fnmsub_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0 @@ -8124,8 +8124,8 @@ __m128d test_mm_fnmsub_round_sd(__m128d __A, __m128d __B, __m128d __C){ __m128d test_mm_mask_fnmsub_round_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B){ // CHECK-LABEL: @test_mm_mask_fnmsub_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0 @@ -8139,8 +8139,8 @@ __m128d test_mm_mask_fnmsub_round_sd(__m128d __W, __mmask8 __U, __m128d __A, __m __m128d test_mm_maskz_fnmsub_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C){ // CHECK-LABEL: @test_mm_maskz_fnmsub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0 @@ -8154,8 +8154,8 @@ __m128d test_mm_maskz_fnmsub_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __m128d test_mm_maskz_fnmsub_round_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C){ // CHECK-LABEL: @test_mm_maskz_fnmsub_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> %{{.*}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.]], i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0 @@ -8169,8 +8169,8 @@ __m128d test_mm_maskz_fnmsub_round_sd(__mmask8 __U, __m128d __A, __m128d __B, __ __m128d test_mm_mask3_fnmsub_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmsub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0 @@ -8185,8 +8185,8 @@ __m128d test_mm_mask3_fnmsub_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __m128d test_mm_mask3_fnmsub_round_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){ // CHECK-LABEL: @test_mm_mask3_fnmsub_round_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , [[ORIGC:%.+]] + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> [[ORIGC:%.+]] // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0 // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0 diff --git a/clang/test/CodeGen/avx512vl-builtins.c b/clang/test/CodeGen/avx512vl-builtins.c index 7f2064c2a3d3..81a689fff1f7 100644 --- a/clang/test/CodeGen/avx512vl-builtins.c +++ b/clang/test/CodeGen/avx512vl-builtins.c @@ -2845,7 +2845,7 @@ __m128d test_mm_mask_fmadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __ __m128d test_mm_mask_fmsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_mask_fmsub_pd - // CHECK: fsub <2 x double> , %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <2 x i32> @@ -2864,7 +2864,7 @@ __m128d test_mm_mask3_fmadd_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 _ __m128d test_mm_mask3_fnmadd_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fnmadd_pd - // CHECK: fsub <2 x double> , %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <2 x i32> @@ -2883,7 +2883,7 @@ __m128d test_mm_maskz_fmadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d _ __m128d test_mm_maskz_fmsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_maskz_fmsub_pd - // CHECK: fsub <2 x double> , %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <2 x i32> @@ -2893,7 +2893,7 @@ __m128d test_mm_maskz_fmsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d _ __m128d test_mm_maskz_fnmadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_maskz_fnmadd_pd - // CHECK: fsub <2 x double> , %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <2 x i32> @@ -2903,8 +2903,8 @@ __m128d test_mm_maskz_fnmadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __m128d test_mm_maskz_fnmsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_maskz_fnmsub_pd - // CHECK: fsub <2 x double> , %{{.*}} - // CHECK: fsub <2 x double> , %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <2 x i32> @@ -2923,7 +2923,7 @@ __m256d test_mm256_mask_fmadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __m256d test_mm256_mask_fmsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_mask_fmsub_pd - // CHECK: fsub <4 x double> , %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -2942,7 +2942,7 @@ __m256d test_mm256_mask3_fmadd_pd(__m256d __A, __m256d __B, __m256d __C, __mmask __m256d test_mm256_mask3_fnmadd_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fnmadd_pd - // CHECK: fsub <4 x double> , %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -2961,7 +2961,7 @@ __m256d test_mm256_maskz_fmadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256 __m256d test_mm256_maskz_fmsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_maskz_fmsub_pd - // CHECK: fsub <4 x double> , %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -2971,7 +2971,7 @@ __m256d test_mm256_maskz_fmsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256 __m256d test_mm256_maskz_fnmadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_maskz_fnmadd_pd - // CHECK: fsub <4 x double> , %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -2981,8 +2981,8 @@ __m256d test_mm256_maskz_fnmadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m25 __m256d test_mm256_maskz_fnmsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_maskz_fnmsub_pd - // CHECK: fsub <4 x double> , %{{.*}} - // CHECK: fsub <4 x double> , %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3001,7 +3001,7 @@ __m128 test_mm_mask_fmadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C) { __m128 test_mm_mask_fmsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_mask_fmsub_ps - // CHECK: fsub <4 x float> , %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3020,7 +3020,7 @@ __m128 test_mm_mask3_fmadd_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U) __m128 test_mm_mask3_fnmadd_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fnmadd_ps - // CHECK: fsub <4 x float> , %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3039,7 +3039,7 @@ __m128 test_mm_maskz_fmadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) __m128 test_mm_maskz_fmsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_maskz_fmsub_ps - // CHECK: fsub <4 x float> , %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3049,7 +3049,7 @@ __m128 test_mm_maskz_fmsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) __m128 test_mm_maskz_fnmadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_maskz_fnmadd_ps - // CHECK: fsub <4 x float> , %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3059,8 +3059,8 @@ __m128 test_mm_maskz_fnmadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) __m128 test_mm_maskz_fnmsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_maskz_fnmsub_ps - // CHECK: fsub <4 x float> , %{{.*}} - // CHECK: fsub <4 x float> , %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3078,7 +3078,7 @@ __m256 test_mm256_mask_fmadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C __m256 test_mm256_mask_fmsub_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_mask_fmsub_ps - // CHECK: fsub <8 x float> , %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}} @@ -3095,7 +3095,7 @@ __m256 test_mm256_mask3_fmadd_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __ __m256 test_mm256_mask3_fnmadd_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fnmadd_ps - // CHECK: fsub <8 x float> , %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}} @@ -3112,7 +3112,7 @@ __m256 test_mm256_maskz_fmadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __ __m256 test_mm256_maskz_fmsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_maskz_fmsub_ps - // CHECK: fsub <8 x float> , %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}} @@ -3121,7 +3121,7 @@ __m256 test_mm256_maskz_fmsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __ __m256 test_mm256_maskz_fnmadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_maskz_fnmadd_ps - // CHECK: fsub <8 x float> , %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}} @@ -3130,8 +3130,8 @@ __m256 test_mm256_maskz_fnmadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 _ __m256 test_mm256_maskz_fnmsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_maskz_fnmsub_ps - // CHECK: fsub <8 x float> , %{{.*}} - // CHECK: fsub <8 x float> , %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}} @@ -3141,7 +3141,7 @@ __m256 test_mm256_maskz_fnmsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 _ __m128d test_mm_mask_fmaddsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_mask_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3152,7 +3152,7 @@ __m128d test_mm_mask_fmaddsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __m128d test_mm_mask_fmsubadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_mask_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: shufflevector <2 x double> [[ADD]], <2 x double> [[SUB]], <2 x i32> @@ -3165,7 +3165,7 @@ __m128d test_mm_mask_fmsubadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __m128d test_mm_mask3_fmaddsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3177,7 +3177,7 @@ __m128d test_mm_mask3_fmaddsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask __m128d test_mm_maskz_fmaddsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_maskz_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3188,7 +3188,7 @@ __m128d test_mm_maskz_fmaddsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128 __m128d test_mm_maskz_fmsubadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_maskz_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: shufflevector <2 x double> [[ADD]], <2 x double> [[SUB]], <2 x i32> @@ -3201,7 +3201,7 @@ __m128d test_mm_maskz_fmsubadd_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128 __m256d test_mm256_mask_fmaddsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_mask_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3212,7 +3212,7 @@ __m256d test_mm256_mask_fmaddsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m2 __m256d test_mm256_mask_fmsubadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_mask_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[ADD]], <4 x double> [[SUB]], <4 x i32> @@ -3225,7 +3225,7 @@ __m256d test_mm256_mask_fmsubadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m2 __m256d test_mm256_mask3_fmaddsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3237,7 +3237,7 @@ __m256d test_mm256_mask3_fmaddsub_pd(__m256d __A, __m256d __B, __m256d __C, __mm __m256d test_mm256_maskz_fmaddsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_maskz_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3248,7 +3248,7 @@ __m256d test_mm256_maskz_fmaddsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m __m256d test_mm256_maskz_fmsubadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_maskz_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[ADD]], <4 x double> [[SUB]], <4 x i32> @@ -3261,7 +3261,7 @@ __m256d test_mm256_maskz_fmsubadd_pd(__mmask8 __U, __m256d __A, __m256d __B, __m __m128 test_mm_mask_fmaddsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_mask_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3272,7 +3272,7 @@ __m128 test_mm_mask_fmaddsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C __m128 test_mm_mask_fmsubadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_mask_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: shufflevector <4 x float> [[ADD]], <4 x float> [[SUB]], <4 x i32> @@ -3285,7 +3285,7 @@ __m128 test_mm_mask_fmsubadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C __m128 test_mm_mask3_fmaddsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3297,7 +3297,7 @@ __m128 test_mm_mask3_fmaddsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __ __m128 test_mm_maskz_fmaddsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_maskz_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3308,7 +3308,7 @@ __m128 test_mm_maskz_fmaddsub_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __ __m128 test_mm_maskz_fmsubadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_maskz_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: shufflevector <4 x float> [[ADD]], <4 x float> [[SUB]], <4 x i32> @@ -3321,7 +3321,7 @@ __m128 test_mm_maskz_fmsubadd_ps(__mmask8 __U, __m128 __A, __m128 __B, __m128 __ __m256 test_mm256_mask_fmaddsub_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_mask_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3331,7 +3331,7 @@ __m256 test_mm256_mask_fmaddsub_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __m256 test_mm256_mask_fmsubadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_mask_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: shufflevector <8 x float> [[ADD]], <8 x float> [[SUB]], <8 x i32> @@ -3343,7 +3343,7 @@ __m256 test_mm256_mask_fmsubadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __m256 test_mm256_mask3_fmaddsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3354,7 +3354,7 @@ __m256 test_mm256_mask3_fmaddsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __m256 test_mm256_maskz_fmaddsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_maskz_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> // CHECK: bitcast i8 %{{.*}} to <8 x i1> @@ -3364,7 +3364,7 @@ __m256 test_mm256_maskz_fmaddsub_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __m256 test_mm256_maskz_fmsubadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_maskz_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: shufflevector <8 x float> [[ADD]], <8 x float> [[SUB]], <8 x i32> @@ -3375,7 +3375,7 @@ __m256 test_mm256_maskz_fmsubadd_ps(__mmask8 __U, __m256 __A, __m256 __B, __m256 __m128d test_mm_mask3_fmsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fmsub_pd - // CHECK: fsub <2 x double> , %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <2 x i32> @@ -3385,7 +3385,7 @@ __m128d test_mm_mask3_fmsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 _ __m256d test_mm256_mask3_fmsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fmsub_pd - // CHECK: fsub <4 x double> , %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3395,7 +3395,7 @@ __m256d test_mm256_mask3_fmsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask __m128 test_mm_mask3_fmsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fmsub_ps - // CHECK: fsub <4 x float> , %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3405,7 +3405,7 @@ __m128 test_mm_mask3_fmsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U) __m256 test_mm256_mask3_fmsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fmsub_ps - // CHECK: fsub <8 x float> , %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}} @@ -3414,7 +3414,7 @@ __m256 test_mm256_mask3_fmsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __ __m128d test_mm_mask3_fmsubadd_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: shufflevector <2 x double> [[ADD]], <2 x double> [[SUB]], <2 x i32> @@ -3426,7 +3426,7 @@ __m128d test_mm_mask3_fmsubadd_pd(__m128d __A, __m128d __B, __m128d __C, __mmask __m256d test_mm256_mask3_fmsubadd_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[ADD]], <4 x double> [[SUB]], <4 x i32> @@ -3438,7 +3438,7 @@ __m256d test_mm256_mask3_fmsubadd_pd(__m256d __A, __m256d __B, __m256d __C, __mm __m128 test_mm_mask3_fmsubadd_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: shufflevector <4 x float> [[ADD]], <4 x float> [[SUB]], <4 x i32> @@ -3450,7 +3450,7 @@ __m128 test_mm_mask3_fmsubadd_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __ __m256 test_mm256_mask3_fmsubadd_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: shufflevector <8 x float> [[ADD]], <8 x float> [[SUB]], <8 x i32> @@ -3461,7 +3461,7 @@ __m256 test_mm256_mask3_fmsubadd_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __m128d test_mm_mask_fnmadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_mask_fnmadd_pd - // CHECK: fsub <2 x double> , %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <2 x i32> @@ -3471,7 +3471,7 @@ __m128d test_mm_mask_fnmadd_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d _ __m256d test_mm256_mask_fnmadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_mask_fnmadd_pd - // CHECK: fsub <4 x double> , %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3481,7 +3481,7 @@ __m256d test_mm256_mask_fnmadd_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256 __m128 test_mm_mask_fnmadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_mask_fnmadd_ps - // CHECK: fsub <4 x float> , %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3491,7 +3491,7 @@ __m128 test_mm_mask_fnmadd_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C) __m256 test_mm256_mask_fnmadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_mask_fnmadd_ps - // CHECK: fsub <8 x float> , %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}} @@ -3500,8 +3500,8 @@ __m256 test_mm256_mask_fnmadd_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __ __m128d test_mm_mask_fnmsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d __C) { // CHECK-LABEL: @test_mm_mask_fnmsub_pd - // CHECK: fsub <2 x double> , %{{.*}} - // CHECK: fsub <2 x double> , %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <2 x i32> @@ -3511,8 +3511,8 @@ __m128d test_mm_mask_fnmsub_pd(__m128d __A, __mmask8 __U, __m128d __B, __m128d _ __m128d test_mm_mask3_fnmsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fnmsub_pd - // CHECK: fsub <2 x double> , %{{.*}} - // CHECK: fsub <2 x double> , %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} + // CHECK: fneg <2 x double> %{{.*}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <2 x i32> @@ -3522,8 +3522,8 @@ __m128d test_mm_mask3_fnmsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __m256d test_mm256_mask_fnmsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256d __C) { // CHECK-LABEL: @test_mm256_mask_fnmsub_pd - // CHECK: fsub <4 x double> , %{{.*}} - // CHECK: fsub <4 x double> , %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3533,8 +3533,8 @@ __m256d test_mm256_mask_fnmsub_pd(__m256d __A, __mmask8 __U, __m256d __B, __m256 __m256d test_mm256_mask3_fnmsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fnmsub_pd - // CHECK: fsub <4 x double> , %{{.*}} - // CHECK: fsub <4 x double> , %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} + // CHECK: fneg <4 x double> %{{.*}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3544,8 +3544,8 @@ __m256d test_mm256_mask3_fnmsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmas __m128 test_mm_mask_fnmsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C) { // CHECK-LABEL: @test_mm_mask_fnmsub_ps - // CHECK: fsub <4 x float> , %{{.*}} - // CHECK: fsub <4 x float> , %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3555,8 +3555,8 @@ __m128 test_mm_mask_fnmsub_ps(__m128 __A, __mmask8 __U, __m128 __B, __m128 __C) __m128 test_mm_mask3_fnmsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm_mask3_fnmsub_ps - // CHECK: fsub <4 x float> , %{{.*}} - // CHECK: fsub <4 x float> , %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} + // CHECK: fneg <4 x float> %{{.*}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: shufflevector <8 x i1> %{{.*}}, <8 x i1> %{{.*}}, <4 x i32> @@ -3566,8 +3566,8 @@ __m128 test_mm_mask3_fnmsub_ps(__m128 __A, __m128 __B, __m128 __C, __mmask8 __U) __m256 test_mm256_mask_fnmsub_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __C) { // CHECK-LABEL: @test_mm256_mask_fnmsub_ps - // CHECK: fsub <8 x float> , %{{.*}} - // CHECK: fsub <8 x float> , %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}} @@ -3576,8 +3576,8 @@ __m256 test_mm256_mask_fnmsub_ps(__m256 __A, __mmask8 __U, __m256 __B, __m256 __ __m256 test_mm256_mask3_fnmsub_ps(__m256 __A, __m256 __B, __m256 __C, __mmask8 __U) { // CHECK-LABEL: @test_mm256_mask3_fnmsub_ps - // CHECK: fsub <8 x float> , %{{.*}} - // CHECK: fsub <8 x float> , %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} + // CHECK: fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: bitcast i8 %{{.*}} to <8 x i1> // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}} diff --git a/clang/test/CodeGen/builtins-ppc-vsx.c b/clang/test/CodeGen/builtins-ppc-vsx.c index 0c797a389b94..a19e75518a8d 100644 --- a/clang/test/CodeGen/builtins-ppc-vsx.c +++ b/clang/test/CodeGen/builtins-ppc-vsx.c @@ -77,11 +77,11 @@ void test1() { res_vf = vec_nabs(vf); // CHECK: [[VEC:%[0-9]+]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> %{{[0-9]*}}) -// CHECK-NEXT: fsub <4 x float> , [[VEC]] +// CHECK-NEXT: fneg <4 x float> [[VEC]] res_vd = vec_nabs(vd); // CHECK: [[VECD:%[0-9]+]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{[0-9]*}}) -// CHECK: fsub <2 x double> , [[VECD]] +// CHECK: fneg <2 x double> [[VECD]] dummy(); // CHECK: call void @dummy() @@ -1686,12 +1686,12 @@ vec_xst_be(vd, sll, ad); // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}}) res_vf = vec_neg(vf); -// CHECK: fsub <4 x float> , {{%[0-9]+}} -// CHECK-LE: fsub <4 x float> , {{%[0-9]+}} +// CHECK: fneg <4 x float> {{%[0-9]+}} +// CHECK-LE: fneg <4 x float> {{%[0-9]+}} res_vd = vec_neg(vd); -// CHECK: fsub <2 x double> , {{%[0-9]+}} -// CHECK-LE: fsub <2 x double> , {{%[0-9]+}} +// CHECK: fneg <2 x double> {{%[0-9]+}} +// CHECK-LE: fneg <2 x double> {{%[0-9]+}} res_vd = vec_xxpermdi(vd, vd, 0); // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> diff --git a/clang/test/CodeGen/complex-math.c b/clang/test/CodeGen/complex-math.c index 21cc5aebb1dd..e42418ad72c2 100644 --- a/clang/test/CodeGen/complex-math.c +++ b/clang/test/CodeGen/complex-math.c @@ -56,7 +56,7 @@ float _Complex sub_float_cr(float _Complex a, float b) { float _Complex sub_float_rc(float a, float _Complex b) { // X86-LABEL: @sub_float_rc( // X86: fsub - // X86: fsub float -0.{{0+}}e+00, + // X86: fneg // X86-NOT: fsub // X86: ret return a - b; @@ -234,7 +234,7 @@ double _Complex sub_double_cr(double _Complex a, double b) { double _Complex sub_double_rc(double a, double _Complex b) { // X86-LABEL: @sub_double_rc( // X86: fsub - // X86: fsub double -0.{{0+}}e+00, + // X86: fneg // X86-NOT: fsub // X86: ret return a - b; @@ -412,7 +412,7 @@ long double _Complex sub_long_double_cr(long double _Complex a, long double b) { long double _Complex sub_long_double_rc(long double a, long double _Complex b) { // X86-LABEL: @sub_long_double_rc( // X86: fsub - // X86: fsub x86_fp80 0xK8{{0+}}, + // X86: fneg // X86-NOT: fsub // X86: ret return a - b; diff --git a/clang/test/CodeGen/exprs.c b/clang/test/CodeGen/exprs.c index 14f58957bc3d..41b429cd3019 100644 --- a/clang/test/CodeGen/exprs.c +++ b/clang/test/CodeGen/exprs.c @@ -143,7 +143,7 @@ int f12() { // Make sure negate of fp uses -0.0 for proper -0 handling. double f13(double X) { // CHECK-LABEL: define double @f13 - // CHECK: fsub double -0.0 + // CHECK: fneg double return -X; } diff --git a/clang/test/CodeGen/fma-builtins.c b/clang/test/CodeGen/fma-builtins.c index ff047f3d8374..1118e0c58219 100644 --- a/clang/test/CodeGen/fma-builtins.c +++ b/clang/test/CodeGen/fma-builtins.c @@ -37,21 +37,21 @@ __m128d test_mm_fmadd_sd(__m128d a, __m128d b, __m128d c) { __m128 test_mm_fmsub_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_fmsub_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) return _mm_fmsub_ps(a, b, c); } __m128d test_mm_fmsub_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_fmsub_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) return _mm_fmsub_pd(a, b, c); } __m128 test_mm_fmsub_ss(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_fmsub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: extractelement <4 x float> %{{.*}}, i64 0 // CHECK: extractelement <4 x float> %{{.*}}, i64 0 // CHECK: extractelement <4 x float> %{{.*}}, i64 0 @@ -62,7 +62,7 @@ __m128 test_mm_fmsub_ss(__m128 a, __m128 b, __m128 c) { __m128d test_mm_fmsub_sd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_fmsub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: extractelement <2 x double> %{{.*}}, i64 0 // CHECK: extractelement <2 x double> %{{.*}}, i64 0 // CHECK: extractelement <2 x double> %{{.*}}, i64 0 @@ -73,21 +73,21 @@ __m128d test_mm_fmsub_sd(__m128d a, __m128d b, __m128d c) { __m128 test_mm_fnmadd_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_fnmadd_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) return _mm_fnmadd_ps(a, b, c); } __m128d test_mm_fnmadd_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_fnmadd_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) return _mm_fnmadd_pd(a, b, c); } __m128 test_mm_fnmadd_ss(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_fnmadd_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: extractelement <4 x float> %{{.*}}, i64 0 // CHECK: extractelement <4 x float> %{{.*}}, i64 0 // CHECK: extractelement <4 x float> %{{.*}}, i64 0 @@ -98,7 +98,7 @@ __m128 test_mm_fnmadd_ss(__m128 a, __m128 b, __m128 c) { __m128d test_mm_fnmadd_sd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_fnmadd_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: extractelement <2 x double> %{{.*}}, i64 0 // CHECK: extractelement <2 x double> %{{.*}}, i64 0 // CHECK: extractelement <2 x double> %{{.*}}, i64 0 @@ -109,24 +109,24 @@ __m128d test_mm_fnmadd_sd(__m128d a, __m128d b, __m128d c) { __m128 test_mm_fnmsub_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_fnmsub_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> %{{.+}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) return _mm_fnmsub_ps(a, b, c); } __m128d test_mm_fnmsub_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_fnmsub_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> %{{.+}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) return _mm_fnmsub_pd(a, b, c); } __m128 test_mm_fnmsub_ss(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_fnmsub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> %{{.+}} // CHECK: extractelement <4 x float> %{{.*}}, i64 0 // CHECK: extractelement <4 x float> %{{.*}}, i64 0 // CHECK: extractelement <4 x float> %{{.*}}, i64 0 @@ -137,8 +137,8 @@ __m128 test_mm_fnmsub_ss(__m128 a, __m128 b, __m128 c) { __m128d test_mm_fnmsub_sd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_fnmsub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> %{{.+}} // CHECK: extractelement <2 x double> %{{.*}}, i64 0 // CHECK: extractelement <2 x double> %{{.*}}, i64 0 // CHECK: extractelement <2 x double> %{{.*}}, i64 0 @@ -150,7 +150,7 @@ __m128d test_mm_fnmsub_sd(__m128d a, __m128d b, __m128d c) { __m128 test_mm_fmaddsub_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> return _mm_fmaddsub_ps(a, b, c); @@ -159,7 +159,7 @@ __m128 test_mm_fmaddsub_ps(__m128 a, __m128 b, __m128 c) { __m128d test_mm_fmaddsub_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> return _mm_fmaddsub_pd(a, b, c); @@ -167,7 +167,7 @@ __m128d test_mm_fmaddsub_pd(__m128d a, __m128d b, __m128d c) { __m128 test_mm_fmsubadd_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: shufflevector <4 x float> [[ADD]], <4 x float> [[SUB]], <4 x i32> @@ -176,7 +176,7 @@ __m128 test_mm_fmsubadd_ps(__m128 a, __m128 b, __m128 c) { __m128d test_mm_fmsubadd_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: shufflevector <2 x double> [[ADD]], <2 x double> [[SUB]], <2 x i32> @@ -197,44 +197,44 @@ __m256d test_mm256_fmadd_pd(__m256d a, __m256d b, __m256d c) { __m256 test_mm256_fmsub_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_fmsub_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) return _mm256_fmsub_ps(a, b, c); } __m256d test_mm256_fmsub_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_fmsub_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) return _mm256_fmsub_pd(a, b, c); } __m256 test_mm256_fnmadd_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_fnmadd_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) return _mm256_fnmadd_ps(a, b, c); } __m256d test_mm256_fnmadd_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_fnmadd_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) return _mm256_fnmadd_pd(a, b, c); } __m256 test_mm256_fnmsub_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_fnmsub_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) return _mm256_fnmsub_ps(a, b, c); } __m256d test_mm256_fnmsub_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_fnmsub_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} - // CHECK: [[NEG2:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} + // CHECK: [[NEG2:%.+]] = fneg <4 x double> %{{.+}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) return _mm256_fnmsub_pd(a, b, c); } @@ -242,7 +242,7 @@ __m256d test_mm256_fnmsub_pd(__m256d a, __m256d b, __m256d c) { __m256 test_mm256_fmaddsub_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_fmaddsub_ps // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> return _mm256_fmaddsub_ps(a, b, c); @@ -251,7 +251,7 @@ __m256 test_mm256_fmaddsub_ps(__m256 a, __m256 b, __m256 c) { __m256d test_mm256_fmaddsub_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_fmaddsub_pd // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> return _mm256_fmaddsub_pd(a, b, c); @@ -259,7 +259,7 @@ __m256d test_mm256_fmaddsub_pd(__m256d a, __m256d b, __m256d c) { __m256 test_mm256_fmsubadd_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_fmsubadd_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: shufflevector <8 x float> [[ADD]], <8 x float> [[SUB]], <8 x i32> @@ -268,7 +268,7 @@ __m256 test_mm256_fmsubadd_ps(__m256 a, __m256 b, __m256 c) { __m256d test_mm256_fmsubadd_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_fmsubadd_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[ADD]], <4 x double> [[SUB]], <4 x i32> diff --git a/clang/test/CodeGen/fma4-builtins.c b/clang/test/CodeGen/fma4-builtins.c index 8078a6ed69b2..e24a9b3adde4 100644 --- a/clang/test/CodeGen/fma4-builtins.c +++ b/clang/test/CodeGen/fma4-builtins.c @@ -37,21 +37,21 @@ __m128d test_mm_macc_sd(__m128d a, __m128d b, __m128d c) { __m128 test_mm_msub_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_msub_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) return _mm_msub_ps(a, b, c); } __m128d test_mm_msub_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_msub_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) return _mm_msub_pd(a, b, c); } __m128 test_mm_msub_ss(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_msub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: extractelement <4 x float> %{{.*}}, i64 0 // CHECK: extractelement <4 x float> %{{.*}}, i64 0 // CHECK: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0 @@ -62,7 +62,7 @@ __m128 test_mm_msub_ss(__m128 a, __m128 b, __m128 c) { __m128d test_mm_msub_sd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_msub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: extractelement <2 x double> %{{.*}}, i64 0 // CHECK: extractelement <2 x double> %{{.*}}, i64 0 // CHECK: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0 @@ -73,21 +73,21 @@ __m128d test_mm_msub_sd(__m128d a, __m128d b, __m128d c) { __m128 test_mm_nmacc_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_nmacc_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) return _mm_nmacc_ps(a, b, c); } __m128d test_mm_nmacc_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_nmacc_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) return _mm_nmacc_pd(a, b, c); } __m128 test_mm_nmacc_ss(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_nmacc_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK: extractelement <4 x float> %{{.*}}, i64 0 // CHECK: extractelement <4 x float> %{{.*}}, i64 0 @@ -98,7 +98,7 @@ __m128 test_mm_nmacc_ss(__m128 a, __m128 b, __m128 c) { __m128d test_mm_nmacc_sd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_nmacc_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK: extractelement <2 x double> %{{.*}}, i64 0 // CHECK: extractelement <2 x double> %{{.*}}, i64 0 @@ -109,24 +109,24 @@ __m128d test_mm_nmacc_sd(__m128d a, __m128d b, __m128d c) { __m128 test_mm_nmsub_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_nmsub_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> %{{.+}} // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) return _mm_nmsub_ps(a, b, c); } __m128d test_mm_nmsub_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_nmsub_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> %{{.+}} // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) return _mm_nmsub_pd(a, b, c); } __m128 test_mm_nmsub_ss(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_nmsub_ss - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} - // CHECK: [[NEG2:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} + // CHECK: [[NEG2:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[A:%.+]] = extractelement <4 x float> [[NEG]], i64 0 // CHECK: extractelement <4 x float> %{{.*}}, i64 0 // CHECK: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0 @@ -137,8 +137,8 @@ __m128 test_mm_nmsub_ss(__m128 a, __m128 b, __m128 c) { __m128d test_mm_nmsub_sd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_nmsub_sd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} - // CHECK: [[NEG2:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} + // CHECK: [[NEG2:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[A:%.+]] = extractelement <2 x double> [[NEG]], i64 0 // CHECK: extractelement <2 x double> %{{.*}}, i64 0 // CHECK: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0 @@ -150,7 +150,7 @@ __m128d test_mm_nmsub_sd(__m128d a, __m128d b, __m128d c) { __m128 test_mm_maddsub_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_maddsub_ps // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: shufflevector <4 x float> [[SUB]], <4 x float> [[ADD]], <4 x i32> return _mm_maddsub_ps(a, b, c); @@ -159,7 +159,7 @@ __m128 test_mm_maddsub_ps(__m128 a, __m128 b, __m128 c) { __m128d test_mm_maddsub_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_maddsub_pd // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: shufflevector <2 x double> [[SUB]], <2 x double> [[ADD]], <2 x i32> return _mm_maddsub_pd(a, b, c); @@ -167,7 +167,7 @@ __m128d test_mm_maddsub_pd(__m128d a, __m128d b, __m128d c) { __m128 test_mm_msubadd_ps(__m128 a, __m128 b, __m128 c) { // CHECK-LABEL: test_mm_msubadd_ps - // CHECK: [[NEG:%.+]] = fsub <4 x float> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x float> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}) // CHECK: shufflevector <4 x float> [[ADD]], <4 x float> [[SUB]], <4 x i32> @@ -176,7 +176,7 @@ __m128 test_mm_msubadd_ps(__m128 a, __m128 b, __m128 c) { __m128d test_mm_msubadd_pd(__m128d a, __m128d b, __m128d c) { // CHECK-LABEL: test_mm_msubadd_pd - // CHECK: [[NEG:%.+]] = fsub <2 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <2 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}) // CHECK: shufflevector <2 x double> [[ADD]], <2 x double> [[SUB]], <2 x i32> @@ -197,44 +197,44 @@ __m256d test_mm256_macc_pd(__m256d a, __m256d b, __m256d c) { __m256 test_mm256_msub_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_msub_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) return _mm256_msub_ps(a, b, c); } __m256d test_mm256_msub_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_msub_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) return _mm256_msub_pd(a, b, c); } __m256 test_mm256_nmacc_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_nmacc_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) return _mm256_nmacc_ps(a, b, c); } __m256d test_mm256_nmacc_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_nmacc_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) return _mm256_nmacc_pd(a, b, c); } __m256 test_mm256_nmsub_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_nmsub_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} - // CHECK: [[NEG2:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} + // CHECK: [[NEG2:%.+]] = fneg <8 x float> %{{.*}} // CHECK: call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) return _mm256_nmsub_ps(a, b, c); } __m256d test_mm256_nmsub_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_nmsub_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} - // CHECK: [[NEG2:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} + // CHECK: [[NEG2:%.+]] = fneg <4 x double> %{{.+}} // CHECK: call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) return _mm256_nmsub_pd(a, b, c); } @@ -242,7 +242,7 @@ __m256d test_mm256_nmsub_pd(__m256d a, __m256d b, __m256d c) { __m256 test_mm256_maddsub_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_maddsub_ps // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: shufflevector <8 x float> [[SUB]], <8 x float> [[ADD]], <8 x i32> return _mm256_maddsub_ps(a, b, c); @@ -251,7 +251,7 @@ __m256 test_mm256_maddsub_ps(__m256 a, __m256 b, __m256 c) { __m256d test_mm256_maddsub_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_maddsub_pd // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> %{{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[SUB]], <4 x double> [[ADD]], <4 x i32> return _mm256_maddsub_pd(a, b, c); @@ -259,7 +259,7 @@ __m256d test_mm256_maddsub_pd(__m256d a, __m256d b, __m256d c) { __m256 test_mm256_msubadd_ps(__m256 a, __m256 b, __m256 c) { // CHECK-LABEL: test_mm256_msubadd_ps - // CHECK: [[NEG:%.+]] = fsub <8 x float> , %{{.*}} + // CHECK: [[NEG:%.+]] = fneg <8 x float> %{{.*}} // CHECK: [[SUB:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> [[NEG]] // CHECK: [[ADD:%.+]] = call <8 x float> @llvm.fma.v8f32(<8 x float> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}) // CHECK: shufflevector <8 x float> [[ADD]], <8 x float> [[SUB]], <8 x i32> @@ -268,7 +268,7 @@ __m256 test_mm256_msubadd_ps(__m256 a, __m256 b, __m256 c) { __m256d test_mm256_msubadd_pd(__m256d a, __m256d b, __m256d c) { // CHECK-LABEL: test_mm256_msubadd_pd - // CHECK: [[NEG:%.+]] = fsub <4 x double> , %{{.+}} + // CHECK: [[NEG:%.+]] = fneg <4 x double> {{.+}} // CHECK: [[SUB:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> [[NEG]] // CHECK: [[ADD:%.+]] = call <4 x double> @llvm.fma.v4f64(<4 x double> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}) // CHECK: shufflevector <4 x double> [[ADD]], <4 x double> [[SUB]], <4 x i32> diff --git a/clang/test/CodeGen/fp16-ops.c b/clang/test/CodeGen/fp16-ops.c index f2ed667341bb..f74552b85921 100644 --- a/clang/test/CodeGen/fp16-ops.c +++ b/clang/test/CodeGen/fp16-ops.c @@ -37,9 +37,9 @@ void foo(void) { // NATIVE-HALF: fcmp une half test = (!h1); // CHECK: [[F16TOF32]] - // CHECK: fsub float + // CHECK: fneg float // NOTNATIVE: [[F32TOF16]] - // NATIVE-HALF: fsub half + // NATIVE-HALF: fneg half h1 = -h1; // CHECK: [[F16TOF32]] // CHECK: [[F32TOF16]] diff --git a/clang/test/CodeGen/zvector.c b/clang/test/CodeGen/zvector.c index a8405a78e92b..58fb60e9187f 100644 --- a/clang/test/CodeGen/zvector.c +++ b/clang/test/CodeGen/zvector.c @@ -108,7 +108,7 @@ void test_pos(void) { // CHECK: [[SUB3:%.*]] = sub <2 x i64> zeroinitializer, [[TMP3]] // CHECK: store volatile <2 x i64> [[SUB3]], <2 x i64>* @sl, align 8 // CHECK: [[TMP4:%.*]] = load volatile <2 x double>, <2 x double>* @fd2, align 8 -// CHECK: [[SUB4:%.*]] = fsub <2 x double> , [[TMP4]] +// CHECK: [[SUB4:%.*]] = fneg <2 x double> [[TMP4]] // CHECK: store volatile <2 x double> [[SUB4]], <2 x double>* @fd, align 8 // CHECK: ret void void test_neg(void) { diff --git a/clang/test/CodeGen/zvector2.c b/clang/test/CodeGen/zvector2.c index 909b3fd7650f..c085dc163c54 100644 --- a/clang/test/CodeGen/zvector2.c +++ b/clang/test/CodeGen/zvector2.c @@ -24,7 +24,7 @@ void test_neg (void) { // CHECK-LABEL: test_neg // CHECK: [[VAL:%[^ ]+]] = load volatile <4 x float>, <4 x float>* @ff2 -// CHECK: %{{.*}} = fsub <4 x float> , [[VAL]] +// CHECK: %{{.*}} = fneg <4 x float> [[VAL]] ff = -ff2; } diff --git a/llvm/include/llvm/IR/IRBuilder.h b/llvm/include/llvm/IR/IRBuilder.h index c69815066249..25febbfa1e23 100644 --- a/llvm/include/llvm/IR/IRBuilder.h +++ b/llvm/include/llvm/IR/IRBuilder.h @@ -1504,7 +1504,7 @@ public: MDNode *FPMathTag = nullptr) { if (auto *VC = dyn_cast(V)) return Insert(Folder.CreateFNeg(VC), Name); - return Insert(setFPAttrs(BinaryOperator::CreateFNeg(V), FPMathTag, FMF), + return Insert(setFPAttrs(UnaryOperator::CreateFNeg(V), FPMathTag, FMF), Name); } @@ -1514,9 +1514,7 @@ public: const Twine &Name = "") { if (auto *VC = dyn_cast(V)) return Insert(Folder.CreateFNeg(VC), Name); - // TODO: This should return UnaryOperator::CreateFNeg(...) once we are - // confident that they are optimized sufficiently. - return Insert(setFPAttrs(BinaryOperator::CreateFNeg(V), nullptr, + return Insert(setFPAttrs(UnaryOperator::CreateFNeg(V), nullptr, FMFSource->getFastMathFlags()), Name); } diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll index e76c706843ce..8d13354e104b 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -227,7 +227,7 @@ define amdgpu_kernel void @udiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -254,7 +254,7 @@ define amdgpu_kernel void @urem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -286,7 +286,7 @@ define amdgpu_kernel void @sdiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -317,7 +317,7 @@ define amdgpu_kernel void @srem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -347,7 +347,7 @@ define amdgpu_kernel void @udiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -374,7 +374,7 @@ define amdgpu_kernel void @urem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -406,7 +406,7 @@ define amdgpu_kernel void @sdiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -437,7 +437,7 @@ define amdgpu_kernel void @srem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -1265,7 +1265,7 @@ define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -1285,7 +1285,7 @@ define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP27:%.*]] = fdiv fast float 1.000000e+00, [[TMP26]] ; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]] ; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]]) -; CHECK-NEXT: [[TMP30:%.*]] = fsub fast float -0.000000e+00, [[TMP29]] +; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]]) ; CHECK-NEXT: [[TMP32:%.*]] = fptoui float [[TMP29]] to i32 ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]]) @@ -1305,7 +1305,7 @@ define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]] ; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]]) -; CHECK-NEXT: [[TMP50:%.*]] = fsub fast float -0.000000e+00, [[TMP49]] +; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]] ; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]]) ; CHECK-NEXT: [[TMP52:%.*]] = fptoui float [[TMP49]] to i32 ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]]) @@ -1325,7 +1325,7 @@ define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP67:%.*]] = fdiv fast float 1.000000e+00, [[TMP66]] ; CHECK-NEXT: [[TMP68:%.*]] = fmul fast float [[TMP65]], [[TMP67]] ; CHECK-NEXT: [[TMP69:%.*]] = call fast float @llvm.trunc.f32(float [[TMP68]]) -; CHECK-NEXT: [[TMP70:%.*]] = fsub fast float -0.000000e+00, [[TMP69]] +; CHECK-NEXT: [[TMP70:%.*]] = fneg fast float [[TMP69]] ; CHECK-NEXT: [[TMP71:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP70]], float [[TMP66]], float [[TMP65]]) ; CHECK-NEXT: [[TMP72:%.*]] = fptoui float [[TMP69]] to i32 ; CHECK-NEXT: [[TMP73:%.*]] = call fast float @llvm.fabs.f32(float [[TMP71]]) @@ -1355,7 +1355,7 @@ define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -1377,7 +1377,7 @@ define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP29:%.*]] = fdiv fast float 1.000000e+00, [[TMP28]] ; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]]) -; CHECK-NEXT: [[TMP32:%.*]] = fsub fast float -0.000000e+00, [[TMP31]] +; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]] ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]]) ; CHECK-NEXT: [[TMP34:%.*]] = fptoui float [[TMP31]] to i32 ; CHECK-NEXT: [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]]) @@ -1399,7 +1399,7 @@ define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP51:%.*]] = fdiv fast float 1.000000e+00, [[TMP50]] ; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]] ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]]) -; CHECK-NEXT: [[TMP54:%.*]] = fsub fast float -0.000000e+00, [[TMP53]] +; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]] ; CHECK-NEXT: [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]]) ; CHECK-NEXT: [[TMP56:%.*]] = fptoui float [[TMP53]] to i32 ; CHECK-NEXT: [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]]) @@ -1421,7 +1421,7 @@ define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP73:%.*]] = fdiv fast float 1.000000e+00, [[TMP72]] ; CHECK-NEXT: [[TMP74:%.*]] = fmul fast float [[TMP71]], [[TMP73]] ; CHECK-NEXT: [[TMP75:%.*]] = call fast float @llvm.trunc.f32(float [[TMP74]]) -; CHECK-NEXT: [[TMP76:%.*]] = fsub fast float -0.000000e+00, [[TMP75]] +; CHECK-NEXT: [[TMP76:%.*]] = fneg fast float [[TMP75]] ; CHECK-NEXT: [[TMP77:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP76]], float [[TMP72]], float [[TMP71]]) ; CHECK-NEXT: [[TMP78:%.*]] = fptoui float [[TMP75]] to i32 ; CHECK-NEXT: [[TMP79:%.*]] = call fast float @llvm.fabs.f32(float [[TMP77]]) @@ -1456,7 +1456,7 @@ define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -1480,7 +1480,7 @@ define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]] ; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]] ; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]]) -; CHECK-NEXT: [[TMP37:%.*]] = fsub fast float -0.000000e+00, [[TMP36]] +; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]]) ; CHECK-NEXT: [[TMP39:%.*]] = fptosi float [[TMP36]] to i32 ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]]) @@ -1504,7 +1504,7 @@ define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]] ; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]] ; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]]) -; CHECK-NEXT: [[TMP61:%.*]] = fsub fast float -0.000000e+00, [[TMP60]] +; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]] ; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]]) ; CHECK-NEXT: [[TMP63:%.*]] = fptosi float [[TMP60]] to i32 ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]]) @@ -1528,7 +1528,7 @@ define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP82:%.*]] = fdiv fast float 1.000000e+00, [[TMP81]] ; CHECK-NEXT: [[TMP83:%.*]] = fmul fast float [[TMP80]], [[TMP82]] ; CHECK-NEXT: [[TMP84:%.*]] = call fast float @llvm.trunc.f32(float [[TMP83]]) -; CHECK-NEXT: [[TMP85:%.*]] = fsub fast float -0.000000e+00, [[TMP84]] +; CHECK-NEXT: [[TMP85:%.*]] = fneg fast float [[TMP84]] ; CHECK-NEXT: [[TMP86:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP85]], float [[TMP81]], float [[TMP80]]) ; CHECK-NEXT: [[TMP87:%.*]] = fptosi float [[TMP84]] to i32 ; CHECK-NEXT: [[TMP88:%.*]] = call fast float @llvm.fabs.f32(float [[TMP86]]) @@ -1562,7 +1562,7 @@ define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -1588,7 +1588,7 @@ define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]] ; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]]) -; CHECK-NEXT: [[TMP39:%.*]] = fsub fast float -0.000000e+00, [[TMP38]] +; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]] ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]]) ; CHECK-NEXT: [[TMP41:%.*]] = fptosi float [[TMP38]] to i32 ; CHECK-NEXT: [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]]) @@ -1614,7 +1614,7 @@ define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]] ; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]] ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]]) -; CHECK-NEXT: [[TMP65:%.*]] = fsub fast float -0.000000e+00, [[TMP64]] +; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]] ; CHECK-NEXT: [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]]) ; CHECK-NEXT: [[TMP67:%.*]] = fptosi float [[TMP64]] to i32 ; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]]) @@ -1640,7 +1640,7 @@ define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP88:%.*]] = fdiv fast float 1.000000e+00, [[TMP87]] ; CHECK-NEXT: [[TMP89:%.*]] = fmul fast float [[TMP86]], [[TMP88]] ; CHECK-NEXT: [[TMP90:%.*]] = call fast float @llvm.trunc.f32(float [[TMP89]]) -; CHECK-NEXT: [[TMP91:%.*]] = fsub fast float -0.000000e+00, [[TMP90]] +; CHECK-NEXT: [[TMP91:%.*]] = fneg fast float [[TMP90]] ; CHECK-NEXT: [[TMP92:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP91]], float [[TMP87]], float [[TMP86]]) ; CHECK-NEXT: [[TMP93:%.*]] = fptosi float [[TMP90]] to i32 ; CHECK-NEXT: [[TMP94:%.*]] = call fast float @llvm.fabs.f32(float [[TMP92]]) @@ -1671,7 +1671,7 @@ define amdgpu_kernel void @udiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -1698,7 +1698,7 @@ define amdgpu_kernel void @urem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = fsub fast float -0.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP8]], float [[TMP4]], float [[TMP3]]) ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP7]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]]) @@ -1730,7 +1730,7 @@ define amdgpu_kernel void @sdiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -1761,7 +1761,7 @@ define amdgpu_kernel void @srem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) -; CHECK-NEXT: [[TMP11:%.*]] = fsub fast float -0.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]]) ; CHECK-NEXT: [[TMP13:%.*]] = fptosi float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]]) @@ -1793,7 +1793,7 @@ define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -1813,7 +1813,7 @@ define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP27:%.*]] = fdiv fast float 1.000000e+00, [[TMP26]] ; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]] ; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]]) -; CHECK-NEXT: [[TMP30:%.*]] = fsub fast float -0.000000e+00, [[TMP29]] +; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]]) ; CHECK-NEXT: [[TMP32:%.*]] = fptoui float [[TMP29]] to i32 ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]]) @@ -1833,7 +1833,7 @@ define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]] ; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]]) -; CHECK-NEXT: [[TMP50:%.*]] = fsub fast float -0.000000e+00, [[TMP49]] +; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]] ; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]]) ; CHECK-NEXT: [[TMP52:%.*]] = fptoui float [[TMP49]] to i32 ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]]) @@ -1863,7 +1863,7 @@ define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -1885,7 +1885,7 @@ define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP29:%.*]] = fdiv fast float 1.000000e+00, [[TMP28]] ; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]]) -; CHECK-NEXT: [[TMP32:%.*]] = fsub fast float -0.000000e+00, [[TMP31]] +; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]] ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]]) ; CHECK-NEXT: [[TMP34:%.*]] = fptoui float [[TMP31]] to i32 ; CHECK-NEXT: [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]]) @@ -1907,7 +1907,7 @@ define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP51:%.*]] = fdiv fast float 1.000000e+00, [[TMP50]] ; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]] ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]]) -; CHECK-NEXT: [[TMP54:%.*]] = fsub fast float -0.000000e+00, [[TMP53]] +; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]] ; CHECK-NEXT: [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]]) ; CHECK-NEXT: [[TMP56:%.*]] = fptoui float [[TMP53]] to i32 ; CHECK-NEXT: [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]]) @@ -1942,7 +1942,7 @@ define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -1966,7 +1966,7 @@ define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]] ; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]] ; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]]) -; CHECK-NEXT: [[TMP37:%.*]] = fsub fast float -0.000000e+00, [[TMP36]] +; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]]) ; CHECK-NEXT: [[TMP39:%.*]] = fptosi float [[TMP36]] to i32 ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]]) @@ -1990,7 +1990,7 @@ define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]] ; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]] ; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]]) -; CHECK-NEXT: [[TMP61:%.*]] = fsub fast float -0.000000e+00, [[TMP60]] +; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]] ; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]]) ; CHECK-NEXT: [[TMP63:%.*]] = fptosi float [[TMP60]] to i32 ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]]) @@ -2024,7 +2024,7 @@ define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -2050,7 +2050,7 @@ define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]] ; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]]) -; CHECK-NEXT: [[TMP39:%.*]] = fsub fast float -0.000000e+00, [[TMP38]] +; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]] ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]]) ; CHECK-NEXT: [[TMP41:%.*]] = fptosi float [[TMP38]] to i32 ; CHECK-NEXT: [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]]) @@ -2076,7 +2076,7 @@ define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]] ; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]] ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]]) -; CHECK-NEXT: [[TMP65:%.*]] = fsub fast float -0.000000e+00, [[TMP64]] +; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]] ; CHECK-NEXT: [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]]) ; CHECK-NEXT: [[TMP67:%.*]] = fptosi float [[TMP64]] to i32 ; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]]) @@ -2109,7 +2109,7 @@ define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -2129,7 +2129,7 @@ define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP27:%.*]] = fdiv fast float 1.000000e+00, [[TMP26]] ; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]] ; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]]) -; CHECK-NEXT: [[TMP30:%.*]] = fsub fast float -0.000000e+00, [[TMP29]] +; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP30]], float [[TMP26]], float [[TMP25]]) ; CHECK-NEXT: [[TMP32:%.*]] = fptoui float [[TMP29]] to i32 ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.fabs.f32(float [[TMP31]]) @@ -2149,7 +2149,7 @@ define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]] ; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]]) -; CHECK-NEXT: [[TMP50:%.*]] = fsub fast float -0.000000e+00, [[TMP49]] +; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]] ; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP50]], float [[TMP46]], float [[TMP45]]) ; CHECK-NEXT: [[TMP52:%.*]] = fptoui float [[TMP49]] to i32 ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.fabs.f32(float [[TMP51]]) @@ -2179,7 +2179,7 @@ define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fsub fast float -0.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP10]], float [[TMP6]], float [[TMP5]]) ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = call fast float @llvm.fabs.f32(float [[TMP11]]) @@ -2201,7 +2201,7 @@ define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP29:%.*]] = fdiv fast float 1.000000e+00, [[TMP28]] ; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]]) -; CHECK-NEXT: [[TMP32:%.*]] = fsub fast float -0.000000e+00, [[TMP31]] +; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]] ; CHECK-NEXT: [[TMP33:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP32]], float [[TMP28]], float [[TMP27]]) ; CHECK-NEXT: [[TMP34:%.*]] = fptoui float [[TMP31]] to i32 ; CHECK-NEXT: [[TMP35:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]]) @@ -2223,7 +2223,7 @@ define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP51:%.*]] = fdiv fast float 1.000000e+00, [[TMP50]] ; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]] ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]]) -; CHECK-NEXT: [[TMP54:%.*]] = fsub fast float -0.000000e+00, [[TMP53]] +; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]] ; CHECK-NEXT: [[TMP55:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP54]], float [[TMP50]], float [[TMP49]]) ; CHECK-NEXT: [[TMP56:%.*]] = fptoui float [[TMP53]] to i32 ; CHECK-NEXT: [[TMP57:%.*]] = call fast float @llvm.fabs.f32(float [[TMP55]]) @@ -2258,7 +2258,7 @@ define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -2282,7 +2282,7 @@ define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]] ; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]] ; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]]) -; CHECK-NEXT: [[TMP37:%.*]] = fsub fast float -0.000000e+00, [[TMP36]] +; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]]) ; CHECK-NEXT: [[TMP39:%.*]] = fptosi float [[TMP36]] to i32 ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]]) @@ -2306,7 +2306,7 @@ define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]] ; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]] ; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]]) -; CHECK-NEXT: [[TMP61:%.*]] = fsub fast float -0.000000e+00, [[TMP60]] +; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]] ; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]]) ; CHECK-NEXT: [[TMP63:%.*]] = fptosi float [[TMP60]] to i32 ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]]) @@ -2340,7 +2340,7 @@ define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) -; CHECK-NEXT: [[TMP13:%.*]] = fsub fast float -0.000000e+00, [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]]) ; CHECK-NEXT: [[TMP15:%.*]] = fptosi float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]]) @@ -2366,7 +2366,7 @@ define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]] ; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]]) -; CHECK-NEXT: [[TMP39:%.*]] = fsub fast float -0.000000e+00, [[TMP38]] +; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]] ; CHECK-NEXT: [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]]) ; CHECK-NEXT: [[TMP41:%.*]] = fptosi float [[TMP38]] to i32 ; CHECK-NEXT: [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]]) @@ -2392,7 +2392,7 @@ define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]] ; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]] ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]]) -; CHECK-NEXT: [[TMP65:%.*]] = fsub fast float -0.000000e+00, [[TMP64]] +; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]] ; CHECK-NEXT: [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]]) ; CHECK-NEXT: [[TMP67:%.*]] = fptosi float [[TMP64]] to i32 ; CHECK-NEXT: [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]]) diff --git a/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll b/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll index c46945398822..e32c93bdf407 100644 --- a/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll +++ b/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll @@ -12,7 +12,7 @@ define amdgpu_kernel void @divrem24_assume(i32 addrspace(1)* %arg, i32 %arg1) { ; CHECK-NEXT: [[TMP2:%.*]] = fdiv fast float 1.000000e+00, [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP0]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.trunc.f32(float [[TMP3]]) -; CHECK-NEXT: [[TMP5:%.*]] = fsub fast float -0.000000e+00, [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = fneg fast float [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP5]], float [[TMP1]], float [[TMP0]]) ; CHECK-NEXT: [[TMP7:%.*]] = fptoui float [[TMP4]] to i32 ; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]]) diff --git a/llvm/test/Transforms/InstCombine/cos-1.ll b/llvm/test/Transforms/InstCombine/cos-1.ll index 12a64403e950..cf668f926aa8 100644 --- a/llvm/test/Transforms/InstCombine/cos-1.ll +++ b/llvm/test/Transforms/InstCombine/cos-1.ll @@ -84,7 +84,7 @@ define float @cosf_unary_negated_arg_FMF(float %x) { define double @sin_negated_arg(double %x) { ; ANY-LABEL: @sin_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call double @sin(double [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub double -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]] ; ANY-NEXT: ret double [[TMP2]] ; %neg = fsub double -0.0, %x @@ -95,7 +95,7 @@ define double @sin_negated_arg(double %x) { define double @sin_unary_negated_arg(double %x) { ; ANY-LABEL: @sin_unary_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call double @sin(double [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub double -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]] ; ANY-NEXT: ret double [[TMP2]] ; %neg = fneg double %x @@ -106,7 +106,7 @@ define double @sin_unary_negated_arg(double %x) { define float @sinf_negated_arg(float %x) { ; ANY-LABEL: @sinf_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call float @sinf(float [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub float -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg float [[TMP1]] ; ANY-NEXT: ret float [[TMP2]] ; %neg = fsub float -0.0, %x @@ -117,7 +117,7 @@ define float @sinf_negated_arg(float %x) { define float @sinf_unary_negated_arg(float %x) { ; ANY-LABEL: @sinf_unary_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call float @sinf(float [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub float -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg float [[TMP1]] ; ANY-NEXT: ret float [[TMP2]] ; %neg = fneg float %x @@ -128,7 +128,7 @@ define float @sinf_unary_negated_arg(float %x) { define float @sinf_negated_arg_FMF(float %x) { ; ANY-LABEL: @sinf_negated_arg_FMF( ; ANY-NEXT: [[TMP1:%.*]] = call nnan afn float @sinf(float [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub nnan afn float -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg nnan afn float [[TMP1]] ; ANY-NEXT: ret float [[TMP2]] ; %neg = fsub ninf float -0.0, %x @@ -139,7 +139,7 @@ define float @sinf_negated_arg_FMF(float %x) { define float @sinf_unary_negated_arg_FMF(float %x) { ; ANY-LABEL: @sinf_unary_negated_arg_FMF( ; ANY-NEXT: [[TMP1:%.*]] = call nnan afn float @sinf(float [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub nnan afn float -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg nnan afn float [[TMP1]] ; ANY-NEXT: ret float [[TMP2]] ; %neg = fneg ninf float %x @@ -227,7 +227,7 @@ define double @unary_neg_sin_negated_arg(double %x) { define double @tan_negated_arg(double %x) { ; ANY-LABEL: @tan_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call double @tan(double [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub double -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]] ; ANY-NEXT: ret double [[TMP2]] ; %neg = fsub double -0.0, %x @@ -238,7 +238,7 @@ define double @tan_negated_arg(double %x) { define double @tan_unary_negated_arg(double %x) { ; ANY-LABEL: @tan_unary_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call double @tan(double [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub double -0.000000e+00, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg double [[TMP1]] ; ANY-NEXT: ret double [[TMP2]] ; %neg = fneg double %x @@ -251,7 +251,7 @@ define double @tan_unary_negated_arg(double %x) { define fp128 @tanl_negated_arg(fp128 %x) { ; ANY-LABEL: @tanl_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call fp128 @tanl(fp128 [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub fp128 0xL00000000000000008000000000000000, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg fp128 [[TMP1]] ; ANY-NEXT: ret fp128 [[TMP2]] ; %neg = fsub fp128 0xL00000000000000008000000000000000, %x @@ -262,7 +262,7 @@ define fp128 @tanl_negated_arg(fp128 %x) { define fp128 @tanl_unary_negated_arg(fp128 %x) { ; ANY-LABEL: @tanl_unary_negated_arg( ; ANY-NEXT: [[TMP1:%.*]] = call fp128 @tanl(fp128 [[X:%.*]]) -; ANY-NEXT: [[TMP2:%.*]] = fsub fp128 0xL00000000000000008000000000000000, [[TMP1]] +; ANY-NEXT: [[TMP2:%.*]] = fneg fp128 [[TMP1]] ; ANY-NEXT: ret fp128 [[TMP2]] ; %neg = fneg fp128 %x diff --git a/llvm/test/Transforms/InstCombine/fast-math.ll b/llvm/test/Transforms/InstCombine/fast-math.ll index 9563c377dca5..41c14aad9d86 100644 --- a/llvm/test/Transforms/InstCombine/fast-math.ll +++ b/llvm/test/Transforms/InstCombine/fast-math.ll @@ -504,7 +504,7 @@ define float @fsub_op0_fmul_const_wrong_FMF(float %x) { define float @fold16(float %x, float %y) { ; CHECK-LABEL: @fold16( ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt float [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = fsub float -0.000000e+00, [[Y]] +; CHECK-NEXT: [[TMP1:%.*]] = fneg float [[Y]] ; CHECK-NEXT: [[R_P:%.*]] = select i1 [[CMP]], float [[Y]], float [[TMP1]] ; CHECK-NEXT: [[R:%.*]] = fadd float [[R_P]], [[X]] ; CHECK-NEXT: ret float [[R]] diff --git a/llvm/test/Transforms/InstCombine/fmul.ll b/llvm/test/Transforms/InstCombine/fmul.ll index 89c957b9d083..d53062aa5776 100644 --- a/llvm/test/Transforms/InstCombine/fmul.ll +++ b/llvm/test/Transforms/InstCombine/fmul.ll @@ -994,7 +994,7 @@ define double @fmul_negated_constant_expression(double %x) { define float @negate_if_true(float %x, i1 %cond) { ; CHECK-LABEL: @negate_if_true( -; CHECK-NEXT: [[TMP1:%.*]] = fsub float -0.000000e+00, [[X:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = fneg float [[X:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], float [[TMP1]], float [[X]] ; CHECK-NEXT: ret float [[TMP2]] ; @@ -1005,7 +1005,7 @@ define float @negate_if_true(float %x, i1 %cond) { define float @negate_if_false(float %x, i1 %cond) { ; CHECK-LABEL: @negate_if_false( -; CHECK-NEXT: [[TMP1:%.*]] = fsub arcp float -0.000000e+00, [[X:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = fneg arcp float [[X:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = select arcp i1 [[COND:%.*]], float [[X]], float [[TMP1]] ; CHECK-NEXT: ret float [[TMP2]] ; @@ -1017,7 +1017,7 @@ define float @negate_if_false(float %x, i1 %cond) { define <2 x double> @negate_if_true_commute(<2 x double> %px, i1 %cond) { ; CHECK-LABEL: @negate_if_true_commute( ; CHECK-NEXT: [[X:%.*]] = fdiv <2 x double> , [[PX:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = fsub ninf <2 x double> , [[X]] +; CHECK-NEXT: [[TMP1:%.*]] = fneg ninf <2 x double> [[X]] ; CHECK-NEXT: [[TMP2:%.*]] = select ninf i1 [[COND:%.*]], <2 x double> [[TMP1]], <2 x double> [[X]] ; CHECK-NEXT: ret <2 x double> [[TMP2]] ; @@ -1030,7 +1030,7 @@ define <2 x double> @negate_if_true_commute(<2 x double> %px, i1 %cond) { define <2 x double> @negate_if_false_commute(<2 x double> %px, <2 x i1> %cond) { ; CHECK-LABEL: @negate_if_false_commute( ; CHECK-NEXT: [[X:%.*]] = fdiv <2 x double> , [[PX:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> , [[X]] +; CHECK-NEXT: [[TMP1:%.*]] = fneg <2 x double> [[X]] ; CHECK-NEXT: [[TMP2:%.*]] = select <2 x i1> [[COND:%.*]], <2 x double> [[X]], <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP2]] ; diff --git a/llvm/test/Transforms/InstCombine/select-crash.ll b/llvm/test/Transforms/InstCombine/select-crash.ll index 41b69d25104d..9de338d95208 100644 --- a/llvm/test/Transforms/InstCombine/select-crash.ll +++ b/llvm/test/Transforms/InstCombine/select-crash.ll @@ -4,7 +4,7 @@ define fastcc double @gimp_operation_color_balance_map(float %value, double %highlights) nounwind readnone inlinehint { entry: ; CHECK: gimp_operation_color_balance_map -; CHECK: fsub double -0.000000 +; CHECK: fneg double %conv = fpext float %value to double %div = fdiv double %conv, 1.600000e+01 %add = fadd double %div, 1.000000e+00 @@ -22,7 +22,7 @@ entry: ; PR10180: same crash, but with vectors define <4 x float> @foo(i1 %b, <4 x float> %x, <4 x float> %y, <4 x float> %z) { ; CHECK-LABEL: @foo( -; CHECK: fsub <4 x float> +; CHECK: fneg <4 x float> ; CHECK: select ; CHECK: fadd <4 x float> %a = fadd <4 x float> %x, %y diff --git a/llvm/unittests/IR/InstructionsTest.cpp b/llvm/unittests/IR/InstructionsTest.cpp index afd579400ff3..5595e8ce93cc 100644 --- a/llvm/unittests/IR/InstructionsTest.cpp +++ b/llvm/unittests/IR/InstructionsTest.cpp @@ -1115,5 +1115,20 @@ if.end: EXPECT_EQ(ArgBA->getBasicBlock(), &IfThen); } +TEST(InstructionsTest, UnaryOperator) { + LLVMContext Context; + IRBuilder<> Builder(Context); + Instruction *I = Builder.CreatePHI(Builder.getDoubleTy(), 0); + Value *F = Builder.CreateFNeg(I); + + EXPECT_TRUE(isa(F)); + EXPECT_TRUE(isa(F)); + EXPECT_TRUE(isa(F)); + EXPECT_TRUE(isa(F)); + EXPECT_FALSE(isa(F)); + + F->deleteValue(); +} + } // end anonymous namespace } // end namespace llvm