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SDag: fix how initial loads are formed when splitting vector ops. 

Later code expects the vector loads produced to be directly
concatenable, which means we shouldn't pad anything except the last load
produced with UNDEF.

llvm-svn: 293088
This commit is contained in:
Tim Northover 2017-01-25 20:58:26 +00:00
parent 9e35f1e21c
commit 470f070b7d
2 changed files with 14 additions and 1 deletions
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5
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -3442,7 +3442,10 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
LD->getPointerInfo().getWithOffset(Offset),
MinAlign(Align, Increment), MMOFlags, AAInfo);
LdChain.push_back(L.getValue(1));
if (L->getValueType(0).isVector()) {
if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
// Later code assumes the vector loads produced will be mergeable, so we
// must pad the final entry up to the previous width. Scalars are
// combined separately.
SmallVector<SDValue, 16> Loads;
Loads.push_back(L);
unsigned size = L->getValueSizeInBits(0);

10
llvm/test/CodeGen/ARM/vector-load.ll
View File

@ -251,3 +251,13 @@ define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
%zlA = zext <4 x i8> %lA to <4 x i32>
ret <4 x i32> %zlA
}
; CHECK-LABEL: test_silly_load:
; CHECK: ldr {{r[0-9]+}}, [r0, #24]
; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0:128]!
; CHECK: vldr d{{[0-9]+}}, [r0]
define void @test_silly_load(<28 x i8>* %addr) {
load volatile <28 x i8>, <28 x i8>* %addr
ret void
}