forked from OSchip/llvm-project
[x86] introduce no_callee_saved_registers attribute
This is directly analogous to the existing no_caller_saved_registers, but with the opposite intention. A function or call so marked shifts the responsibility of spilling the usual CSRs to it's caller. An indirect call site and callee which don't agree on the attribute is ill defined. The motivation for this change is that being able to prune callee saves (without modifying other details of the calling convention) is sometimes useful when generating stubs and adapters. There's no intention to expose this as a source language feature; this is expected to be used by frontends to implement adapters where warranted. Some specific examples of use cases: * GC compatible compiled code wants to call an externally defined library function without needing to track pointer values through CSRs. * debug enabled code wants to call precompiled library which doesn't provide enough information to track CSRs while preserving debug quality in caller. * adapter stub entering hand written assembler which doesn't follow normal calling conventions.
This commit is contained in:
Philip Reames
parent
fbd5507178
commit
46e764a628
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@ -3215,6 +3215,10 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
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if ((CB && isa<CallInst>(CB) && CB->hasFnAttr("no_caller_saved_registers")))
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if ((CB && isa<CallInst>(CB) && CB->hasFnAttr("no_caller_saved_registers")))
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return false;
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return false;
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// Functions with no_callee_saved_registers that need special handling.
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if ((CB && CB->hasFnAttr("no_callee_saved_registers")))
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return false;
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// Functions using thunks for indirect calls need to use SDISel.
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// Functions using thunks for indirect calls need to use SDISel.
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if (Subtarget->useIndirectThunkCalls())
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if (Subtarget->useIndirectThunkCalls())
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return false;
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return false;
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@ -4335,11 +4335,19 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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RegsToPass[i].second.getValueType()));
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RegsToPass[i].second.getValueType()));
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// Add a register mask operand representing the call-preserved registers.
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// Add a register mask operand representing the call-preserved registers.
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// If HasNCSR is asserted (attribute NoCallerSavedRegisters exists) then we
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const uint32_t *Mask = [&]() {
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// set X86_INTR calling convention because it has the same CSR mask
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auto AdaptedCC = CallConv;
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// (same preserved registers).
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// If HasNCSR is asserted (attribute NoCallerSavedRegisters exists),
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const uint32_t *Mask = RegInfo->getCallPreservedMask(
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// use X86_INTR calling convention because it has the same CSR mask
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MF, HasNCSR ? (CallingConv::ID)CallingConv::X86_INTR : CallConv);
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// (same preserved registers).
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if (HasNCSR)
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AdaptedCC = (CallingConv::ID)CallingConv::X86_INTR;
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// If NoCalleeSavedRegisters is requested, than use GHC since it happens
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// to use the CSR_NoRegs_RegMask.
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if (CB && CB->hasFnAttr("no_callee_saved_registers"))
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AdaptedCC = (CallingConv::ID)CallingConv::GHC;
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return RegInfo->getCallPreservedMask(MF, AdaptedCC);
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}();
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assert(Mask && "Missing call preserved mask for calling convention");
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assert(Mask && "Missing call preserved mask for calling convention");
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// If this is an invoke in a 32-bit function using a funclet-based
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// If this is an invoke in a 32-bit function using a funclet-based
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@ -290,6 +290,11 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
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if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
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CC = CallingConv::X86_INTR;
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CC = CallingConv::X86_INTR;
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// If atribute specified, override the CSRs normally specified by the
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// calling convention and use the empty set instead.
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if (MF->getFunction().hasFnAttribute("no_callee_saved_registers"))
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return CSR_NoRegs_SaveList;
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switch (CC) {
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switch (CC) {
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case CallingConv::GHC:
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case CallingConv::GHC:
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case CallingConv::HiPE:
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case CallingConv::HiPE:
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@ -0,0 +1,247 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -O0 < %s | FileCheck --check-prefixes=CHECK,CHECK-O0 %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -O3 < %s | FileCheck --check-prefixes=CHECK,CHECK-O3 %s
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declare void @external()
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declare void @no_csr() "no_callee_saved_registers"
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define void @normal() {
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; CHECK-LABEL: normal:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: callq external@PLT
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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call void @external()
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ret void
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}
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; Calling a routine with no CSRs means the caller has to spill a bunch
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define void @test1() {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: callq external@PLT
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; CHECK-NEXT: addq $8, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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call void @external() "no_callee_saved_registers"
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ret void
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}
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; Same as test1, but on callee, not callsite
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define void @test2() {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: pushq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: pushq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset %rbx, -56
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; CHECK-NEXT: .cfi_offset %r12, -48
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; CHECK-NEXT: .cfi_offset %r13, -40
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; CHECK-NEXT: .cfi_offset %r14, -32
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; CHECK-NEXT: .cfi_offset %r15, -24
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; CHECK-NEXT: .cfi_offset %rbp, -16
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; CHECK-NEXT: callq no_csr@PLT
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; CHECK-NEXT: addq $8, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 56
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: popq %r12
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; CHECK-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: popq %r13
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: .cfi_def_cfa_offset 24
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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call void @no_csr()
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ret void
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}
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; on an invoke instead
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define i32 @test3() personality i8* undef {
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; CHECK-O0-LABEL: test3:
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; CHECK-O0: # %bb.0: # %entry
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; CHECK-O0-NEXT: pushq %rbp
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
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; CHECK-O0-NEXT: pushq %r15
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 24
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; CHECK-O0-NEXT: pushq %r14
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 32
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; CHECK-O0-NEXT: pushq %r13
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 40
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; CHECK-O0-NEXT: pushq %r12
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 48
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; CHECK-O0-NEXT: pushq %rbx
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 56
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; CHECK-O0-NEXT: pushq %rax
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 64
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; CHECK-O0-NEXT: .cfi_offset %rbx, -56
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; CHECK-O0-NEXT: .cfi_offset %r12, -48
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; CHECK-O0-NEXT: .cfi_offset %r13, -40
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; CHECK-O0-NEXT: .cfi_offset %r14, -32
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; CHECK-O0-NEXT: .cfi_offset %r15, -24
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; CHECK-O0-NEXT: .cfi_offset %rbp, -16
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; CHECK-O0-NEXT: .Ltmp0:
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; CHECK-O0-NEXT: callq no_csr@PLT
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; CHECK-O0-NEXT: .Ltmp1:
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; CHECK-O0-NEXT: jmp .LBB3_1
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; CHECK-O0-NEXT: .LBB3_1: # %invoke.cont
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; CHECK-O0-NEXT: movl $1, %eax
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; CHECK-O0-NEXT: addq $8, %rsp
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 56
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; CHECK-O0-NEXT: popq %rbx
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 48
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; CHECK-O0-NEXT: popq %r12
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 40
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; CHECK-O0-NEXT: popq %r13
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 32
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; CHECK-O0-NEXT: popq %r14
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 24
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; CHECK-O0-NEXT: popq %r15
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
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; CHECK-O0-NEXT: popq %rbp
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 8
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; CHECK-O0-NEXT: retq
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; CHECK-O0-NEXT: .LBB3_2: # %lpad
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 64
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; CHECK-O0-NEXT: .Ltmp2:
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; CHECK-O0-NEXT: xorl %eax, %eax
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; CHECK-O0-NEXT: addq $8, %rsp
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 56
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; CHECK-O0-NEXT: popq %rbx
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 48
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; CHECK-O0-NEXT: popq %r12
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 40
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; CHECK-O0-NEXT: popq %r13
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 32
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; CHECK-O0-NEXT: popq %r14
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 24
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; CHECK-O0-NEXT: popq %r15
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
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; CHECK-O0-NEXT: popq %rbp
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; CHECK-O0-NEXT: .cfi_def_cfa_offset 8
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; CHECK-O0-NEXT: retq
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;
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; CHECK-O3-LABEL: test3:
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; CHECK-O3: # %bb.0: # %entry
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; CHECK-O3-NEXT: pushq %rbp
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 16
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; CHECK-O3-NEXT: pushq %r15
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 24
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; CHECK-O3-NEXT: pushq %r14
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 32
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; CHECK-O3-NEXT: pushq %r13
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 40
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; CHECK-O3-NEXT: pushq %r12
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 48
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; CHECK-O3-NEXT: pushq %rbx
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 56
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; CHECK-O3-NEXT: pushq %rax
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 64
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; CHECK-O3-NEXT: .cfi_offset %rbx, -56
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; CHECK-O3-NEXT: .cfi_offset %r12, -48
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; CHECK-O3-NEXT: .cfi_offset %r13, -40
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; CHECK-O3-NEXT: .cfi_offset %r14, -32
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; CHECK-O3-NEXT: .cfi_offset %r15, -24
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; CHECK-O3-NEXT: .cfi_offset %rbp, -16
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; CHECK-O3-NEXT: .Ltmp0:
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; CHECK-O3-NEXT: callq no_csr@PLT
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; CHECK-O3-NEXT: .Ltmp1:
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; CHECK-O3-NEXT: # %bb.1: # %invoke.cont
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; CHECK-O3-NEXT: movl $1, %eax
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; CHECK-O3-NEXT: .LBB3_2: # %invoke.cont
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; CHECK-O3-NEXT: addq $8, %rsp
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 56
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; CHECK-O3-NEXT: popq %rbx
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 48
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; CHECK-O3-NEXT: popq %r12
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 40
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; CHECK-O3-NEXT: popq %r13
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 32
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; CHECK-O3-NEXT: popq %r14
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 24
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; CHECK-O3-NEXT: popq %r15
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 16
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; CHECK-O3-NEXT: popq %rbp
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 8
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; CHECK-O3-NEXT: retq
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; CHECK-O3-NEXT: .LBB3_3: # %lpad
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; CHECK-O3-NEXT: .cfi_def_cfa_offset 64
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; CHECK-O3-NEXT: .Ltmp2:
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; CHECK-O3-NEXT: xorl %eax, %eax
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; CHECK-O3-NEXT: jmp .LBB3_2
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entry:
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invoke void @no_csr()
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to label %invoke.cont unwind label %lpad
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invoke.cont:
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ret i32 1
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lpad:
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%0 = landingpad { i8*, i32 }
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cleanup
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ret i32 0
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}
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define void @no_csr_func() "no_callee_saved_registers" {
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; CHECK-LABEL: no_csr_func:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: callq external@PLT
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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call void @external()
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ret void
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}
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||||||
|
|
||||||
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Reference in New Issue