From 46dd413991f6fa74a1da3f139b386e364dfc9f78 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 17 Aug 2011 21:51:27 +0000 Subject: [PATCH] ARM clean up the imm_sr operand class representation. Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. llvm-svn: 137879 --- llvm/lib/Target/ARM/ARMCodeEmitter.cpp | 2 -- llvm/lib/Target/ARM/ARMInstrThumb.td | 14 ++++++++++---- llvm/lib/Target/ARM/ARMInstrThumb2.td | 2 +- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 17 +++++++++++++++++ .../Target/ARM/Disassembler/ARMDisassembler.cpp | 11 ----------- .../Target/ARM/InstPrinter/ARMInstPrinter.cpp | 8 +++++++- .../lib/Target/ARM/InstPrinter/ARMInstPrinter.h | 1 + .../ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 10 ---------- 8 files changed, 36 insertions(+), 29 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp index c30aa3745492..7d4eb6f18f91 100644 --- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp @@ -236,8 +236,6 @@ namespace { const {return 0; } uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) const { return 0; } - unsigned getThumbSRImmOpValue(const MachineInstr &MI, unsigned OpIdx) - const { return 0; } unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) const { diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index f9278773228d..22dfd82564ad 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -19,11 +19,17 @@ def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; -def imm_sr : Operand, ImmLeafgetZExtValue(); + return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32); +}]>; +def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } +def imm_sr : Operand, PatLeaf<(imm), [{ + uint64_t Imm = N->getZExtValue(); return Imm > 0 && Imm <= 32; -}]> { - let EncoderMethod = "getThumbSRImmOpValue"; - let DecoderMethod = "DecodeThumbSRImm"; +}], imm_sr_XFORM> { + let PrintMethod = "printThumbSRImm"; + let ParserMatchClass = ThumbSRImmAsmOperand; } def imm_neg_XFORM : SDNodeXForm opcod, string opc, Operand ty, PatFrag opnode> { def ri : T2sTwoRegShiftImm< (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi, opc, ".w\t$Rd, $Rm, $imm", - [(set rGPR:$Rd, (opnode rGPR:$Rm, ty:$imm))]> { + [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> { let Inst{31-27} = 0b11101; let Inst{26-21} = 0b010010; let Inst{19-16} = 0b1111; // Rn diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 0313ef4b71ed..fcca436ac556 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -482,6 +482,14 @@ public: int64_t Value = CE->getValue(); return Value >= 0 && Value <= 0xffffff; } + bool isImmThumbSR() const { + if (Kind != Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value > 0 && Value < 33; + } bool isPKHLSLImm() const { if (Kind != Immediate) return false; @@ -794,6 +802,15 @@ public: addExpr(Inst, getImm()); } + void addImmThumbSROperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + // The constant encodes as the immediate, except for 32, which encodes as + // zero. + const MCConstantExpr *CE = dyn_cast(getImm()); + unsigned Imm = CE->getValue(); + Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); + } + void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index a585dcbb291d..91b169bd282f 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -210,8 +210,6 @@ static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, @@ -2474,15 +2472,6 @@ static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, return Success; } -static DecodeStatus DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { - if (Val == 0) - Inst.addOperand(MCOperand::CreateImm(32)); - else - Inst.addOperand(MCOperand::CreateImm(Val)); - return Success; -} - static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = Success; diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 67d39a386848..30fa76ad7019 100644 --- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -639,7 +639,13 @@ void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { - O << "#" << MI->getOperand(OpNum).getImm() * 4; + O << "#" << MI->getOperand(OpNum).getImm() * 4; +} + +void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNum).getImm(); + O << "#" << (Imm == 0 ? 32 : Imm); } void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h index 8b94ec5f05d0..e68a6290fe52 100644 --- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h +++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h @@ -74,6 +74,7 @@ public: void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index ee720d7dadad..ecbc6411c884 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -443,16 +443,6 @@ EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, return isAdd; } -uint32_t ARMMCCodeEmitter:: -getThumbSRImmOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { - const MCOperand &MO = MI.getOperand(OpIdx); - assert(MO.isImm() && "Expected constant shift!"); - int val = MO.getImm(); - return (val == 32) ? 0 : val; -} - - /// getBranchTargetOpValue - Helper function to get the branch target operand, /// which is either an immediate or requires a fixup. static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,