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AMDGPU: Avoid folding 2 constant operands into an SALU operation 

Summary:
Catch the (admittedly unusual) case where SIFoldOperands attempts to fold 2
constant operands into the same SALU operation, with neither operand able to be
encoded as an inline constant.

Change-Id: Ibc48d662c9ffd8bbacd154976b0b1c257ace0927

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70896
This commit is contained in:
David Stuttard 2019-12-02 13:01:26 +00:00
parent daff7b8589
commit 46db606834
2 changed files with 94 additions and 0 deletions
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23
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
View File

@ -429,6 +429,29 @@ static bool tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
return true;
}
// Check the case where we might introduce a second constant operand to a
// scalar instruction
if (TII->isSALU(MI->getOpcode())) {
const MCInstrDesc &InstDesc = MI->getDesc();
const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
const SIRegisterInfo &SRI = TII->getRegisterInfo();
// Fine if the operand can be encoded as an inline constant
if (OpToFold->isImm()) {
if (!SRI.opCanUseInlineConstant(OpInfo.OperandType) ||
!TII->isInlineConstant(*OpToFold, OpInfo)) {
// Otherwise check for another constant
for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) {
auto &Op = MI->getOperand(i);
if (OpNo != i &&
TII->isLiteralConstantLike(Op, OpInfo)) {
return false;
}
}
}
}
}
appendFoldCandidate(FoldList, MI, OpNo, OpToFold);
return true;
}

71
llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir Normal file
View File

@ -0,0 +1,71 @@
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: test_part_fold{{$}}
# GCN: %2:sreg_32 = S_ADD_I32 70, %1
---
name: test_part_fold
tracksRegLiveness: true
body: |
bb.0:
%0:sreg_32 = S_MOV_B32 70
%1:sreg_32 = S_MOV_B32 80
%2:sreg_32 = S_ADD_I32 %0, %1, implicit-def $scc
...
# GCN-LABEL: name: test_inline_const{{$}}
# GCN: %2:sreg_32 = S_ADD_I32 70, 63
---
name: test_inline_const
tracksRegLiveness: true
body: |
bb.0:
%0:sreg_32 = S_MOV_B32 70
%1:sreg_32 = S_MOV_B32 63
%2:sreg_32 = S_ADD_I32 %0, %1, implicit-def $scc
...
# GCN-LABEL: name: test_obscure{{$}}
# GCN: %2:sreg_32 = S_LSHL2_ADD_U32 70, %1
---
name: test_obscure
tracksRegLiveness: true
body: |
bb.0:
%0:sreg_32 = S_MOV_B32 70
%1:sreg_32 = S_MOV_B32 80
%2:sreg_32 = S_LSHL2_ADD_U32 %0, %1, implicit-def $scc
...
# GCN-LABEL: name: test_obscure_inline{{$}}
# GCN: %2:sreg_32 = S_LSHL2_ADD_U32 70, 63
---
name: test_obscure_inline
tracksRegLiveness: true
body: |
bb.0:
%0:sreg_32 = S_MOV_B32 70
%1:sreg_32 = S_MOV_B32 63
%2:sreg_32 = S_LSHL2_ADD_U32 %0, %1, implicit-def $scc
...
# GCN-LABEL: name: test_frameindex{{$}}
# GCN: %1:sreg_32 = S_ADD_I32 %stack.0, %0
---
name: test_frameindex
tracksRegLiveness: true
stack:
- { id: 0, type: default, offset: 0, size: 64, alignment: 16}
body: |
bb.0:
%0:sreg_32 = S_MOV_B32 70
%1:sreg_32 = S_ADD_I32 %stack.0, %0, implicit-def $scc
...
# GCN-LABEL: name: test_frameindex_inline{{$}}
# GCN: %1:sreg_32 = S_ADD_I32 %stack.0, 63
---
name: test_frameindex_inline
tracksRegLiveness: true
stack:
- { id: 0, type: default, offset: 0, size: 64, alignment: 16}
body: |
bb.0:
%0:sreg_32 = S_MOV_B32 63
%1:sreg_32 = S_ADD_I32 %stack.0, %0, implicit-def $scc
...