maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF. 

llvm-svn: 129922
This commit is contained in:
Devang Patel 2011-04-21 17:51:06 +00:00
parent 28f2719d83
commit 46bda61a81
1 changed files with 32 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
llvm/lib/Target/ARM/ARMRegisterInfo.td
View File

@ -102,33 +102,41 @@ def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
// Aliases of the F* registers used to hold 64-bit fp values (doubles) // Aliases of the F* registers used to hold 64-bit fp values (doubles)
let SubRegIndices = [ssub_0, ssub_1] in { let SubRegIndices = [ssub_0, ssub_1] in {
def D0 : ARMReg< 0, "d0", [S0, S1]>; def D0 : ARMReg< 0, "d0", [S0, S1]>, DwarfRegNum<[256]>;
def D1 : ARMReg< 1, "d1", [S2, S3]>; def D1 : ARMReg< 1, "d1", [S2, S3]>, DwarfRegNum<[257]>;
def D2 : ARMReg< 2, "d2", [S4, S5]>; def D2 : ARMReg< 2, "d2", [S4, S5]>, DwarfRegNum<[258]>;
def D3 : ARMReg< 3, "d3", [S6, S7]>; def D3 : ARMReg< 3, "d3", [S6, S7]>, DwarfRegNum<[259]>;
def D4 : ARMReg< 4, "d4", [S8, S9]>; def D4 : ARMReg< 4, "d4", [S8, S9]>, DwarfRegNum<[260]>;
def D5 : ARMReg< 5, "d5", [S10, S11]>; def D5 : ARMReg< 5, "d5", [S10, S11]>, DwarfRegNum<[261]>;
def D6 : ARMReg< 6, "d6", [S12, S13]>; def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>;
def D7 : ARMReg< 7, "d7", [S14, S15]>; def D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>;
def D8 : ARMReg< 8, "d8", [S16, S17]>; def D8 : ARMReg< 8, "d8", [S16, S17]>, DwarfRegNum<[264]>;
def D9 : ARMReg< 9, "d9", [S18, S19]>; def D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>;
def D10 : ARMReg<10, "d10", [S20, S21]>; def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
def D11 : ARMReg<11, "d11", [S22, S23]>; def D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>;
def D12 : ARMReg<12, "d12", [S24, S25]>; def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>;
def D13 : ARMReg<13, "d13", [S26, S27]>; def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>;
def D14 : ARMReg<14, "d14", [S28, S29]>; def D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>;
def D15 : ARMReg<15, "d15", [S30, S31]>; def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>;
} }
// VFP3 defines 16 additional double registers // VFP3 defines 16 additional double registers
def D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d17">; def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>;
def D18 : ARMFReg<18, "d18">; def D19 : ARMFReg<19, "d19">; def D17 : ARMFReg<17, "d17">, DwarfRegNum<[273]>;
def D20 : ARMFReg<20, "d20">; def D21 : ARMFReg<21, "d21">; def D18 : ARMFReg<18, "d18">, DwarfRegNum<[274]>;
def D22 : ARMFReg<22, "d22">; def D23 : ARMFReg<23, "d23">; def D19 : ARMFReg<19, "d19">, DwarfRegNum<[275]>;
def D24 : ARMFReg<24, "d24">; def D25 : ARMFReg<25, "d25">; def D20 : ARMFReg<20, "d20">, DwarfRegNum<[276]>;
def D26 : ARMFReg<26, "d26">; def D27 : ARMFReg<27, "d27">; def D21 : ARMFReg<21, "d21">, DwarfRegNum<[277]>;
def D28 : ARMFReg<28, "d28">; def D29 : ARMFReg<29, "d29">; def D22 : ARMFReg<22, "d22">, DwarfRegNum<[278]>;
def D30 : ARMFReg<30, "d30">; def D31 : ARMFReg<31, "d31">; def D23 : ARMFReg<23, "d23">, DwarfRegNum<[279]>;
def D24 : ARMFReg<24, "d24">, DwarfRegNum<[280]>;
def D25 : ARMFReg<25, "d25">, DwarfRegNum<[281]>;
def D26 : ARMFReg<26, "d26">, DwarfRegNum<[282]>;
def D27 : ARMFReg<27, "d27">, DwarfRegNum<[283]>;
def D28 : ARMFReg<28, "d28">, DwarfRegNum<[284]>;
def D29 : ARMFReg<29, "d29">, DwarfRegNum<[285]>;
def D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>;
def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;
// Advanced SIMD (NEON) defines 16 quad-word aliases // Advanced SIMD (NEON) defines 16 quad-word aliases
let SubRegIndices = [dsub_0, dsub_1], let SubRegIndices = [dsub_0, dsub_1],