forked from OSchip/llvm-project
[SystemZ] Enable unaligned accesses
The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. llvm-svn: 182920
This commit is contained in:
Richard Sandiford
parent
2c14269883
commit
46af5a2cdc
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@ -253,6 +253,16 @@ bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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return Imm.isZero() || Imm.isNegZero();
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}
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bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
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bool *Fast) const {
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// Unaligned accesses should never be slower than the expanded version.
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// We check specifically for aligned accesses in the few cases where
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// they are required.
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if (Fast)
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*Fast = true;
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return true;
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}
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//===----------------------------------------------------------------------===//
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// Inline asm support
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//===----------------------------------------------------------------------===//
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@ -125,6 +125,7 @@ public:
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return true;
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}
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
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virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
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virtual std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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@ -34,15 +34,15 @@ define i64 @f1(i64 %length, i64 %index) {
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; CHECK-E: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
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; CHECK-E: mviy 4096([[TMP]]), 4
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%a = alloca i8, i64 %length
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store i8 0, i8 *%a
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store volatile i8 0, i8 *%a
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%b = getelementptr i8 *%a, i64 4095
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store i8 1, i8 *%b
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store volatile i8 1, i8 *%b
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%c = getelementptr i8 *%a, i64 %index
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store i8 2, i8 *%c
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store volatile i8 2, i8 *%c
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%d = getelementptr i8 *%c, i64 4095
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store i8 3, i8 *%d
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store volatile i8 3, i8 *%d
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%e = getelementptr i8 *%d, i64 1
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store i8 4, i8 *%e
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store volatile i8 4, i8 *%e
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%count = call i64 @bar(i8 *%a)
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%res = add i64 %count, 1
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ret i64 %res
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@ -4,6 +4,7 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i16 1
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@h = global i16 1, align 1, section "foo"
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; Check signed comparison.
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define i32 @f1(i32 %src1) {
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@ -79,3 +80,23 @@ exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Repeat f1 with an unaligned address.
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define i32 @f5(i32 %src1) {
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; CHECK: f5:
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; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
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; CHECK: ch %r2, 0([[REG]])
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i16 *@h, align 1
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%src2 = sext i16 %val to i32
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%cond = icmp slt i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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@ -4,6 +4,7 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i16 1
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@h = global i16 1, align 1, section "foo"
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; Check unsigned comparison.
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define i32 @f1(i32 %src1) {
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@ -79,3 +80,24 @@ exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Repeat f1 with an unaligned address.
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define i32 @f5(i32 %src1) {
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; CHECK: f5:
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; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
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; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
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; CHECK: clr %r2, [[VAL]]
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i16 *@h, align 1
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%src2 = zext i16 %val to i32
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%cond = icmp ult i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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@ -4,6 +4,7 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i32 1
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@h = global i32 1, align 2, section "foo"
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; Check signed comparisons.
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define i32 @f1(i32 %src1) {
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@ -76,3 +77,41 @@ exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Repeat f1 with an unaligned address.
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define i32 @f5(i32 %src1) {
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; CHECK: f5:
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; CHECK: larl [[REG:%r[0-5]]], h
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; CHECK: c %r2, 0([[REG]])
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%src2 = load i32 *@h, align 2
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%cond = icmp slt i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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; Repeat f2 with an unaligned address.
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define i32 @f6(i32 %src1) {
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; CHECK: f6:
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; CHECK: larl [[REG:%r[0-5]]], h
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; CHECK: cl %r2, 0([[REG]])
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%src2 = load i32 *@h, align 2
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%cond = icmp ult i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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ret i32 %res
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}
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@ -4,6 +4,7 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i16 1
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@h = global i16 1, align 1, section "foo"
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; Check signed comparison.
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define i64 @f1(i64 %src1) {
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@ -79,3 +80,23 @@ exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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; Repeat f1 with an unaligned address.
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define i64 @f5(i64 %src1) {
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; CHECK: f5:
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; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
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; CHECK: cgh %r2, 0([[REG]])
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i16 *@h, align 1
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%src2 = sext i16 %val to i64
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%cond = icmp slt i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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@ -4,6 +4,7 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i16 1
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@h = global i16 1, align 1, section "foo"
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; Check unsigned comparison.
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define i64 @f1(i64 %src1) {
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@ -79,3 +80,24 @@ exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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; Repeat f1 with an unaligned address.
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define i64 @f5(i64 %src1) {
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; CHECK: f5:
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; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
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; CHECK: llgh [[VAL:%r[0-5]]], 0([[REG]])
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; CHECK: clgr %r2, [[VAL]]
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i16 *@h, align 1
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%src2 = zext i16 %val to i64
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%cond = icmp ult i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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@ -4,6 +4,7 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i32 1
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@h = global i32 1, align 2, section "foo"
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; Check signed comparison.
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define i64 @f1(i64 %src1) {
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@ -79,3 +80,23 @@ exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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; Repeat f1 with an unaligned address.
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define i64 @f5(i64 %src1) {
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; CHECK: f5:
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; CHECK: larl [[REG:%r[0-5]]], h
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; CHECK: cgf %r2, 0([[REG]])
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i32 *@h, align 2
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%src2 = sext i32 %val to i64
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%cond = icmp slt i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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@ -4,6 +4,7 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i32 1
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@h = global i32 1, align 2, section "foo"
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; Check unsigned comparison.
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define i64 @f1(i64 %src1) {
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@ -79,3 +80,23 @@ exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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; Repeat f1 with an unaligned address.
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define i64 @f5(i64 %src1) {
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; CHECK: f5:
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; CHECK: larl [[REG:%r[0-5]]], h
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; CHECK: clgf %r2, 0([[REG]])
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i32 *@h, align 2
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%src2 = zext i32 %val to i64
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%cond = icmp ult i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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@ -4,6 +4,7 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i64 1
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@h = global i64 1, align 4, section "foo"
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; Check signed comparisons.
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define i64 @f1(i64 %src1) {
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@ -76,3 +77,22 @@ exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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; Repeat f1 with an unaligned address.
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define i64 @f5(i64 %src1) {
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; CHECK: f5:
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; CHECK: larl [[REG:%r[0-5]]], h
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; CHECK: cg %r2, 0([[REG]])
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%src2 = load i64 *@h, align 4
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%cond = icmp slt i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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@ -6,6 +6,10 @@
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@gsrc32 = global i32 1
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@gdst16 = global i16 2
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@gdst32 = global i32 2
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@gsrc16u = global i16 1, align 1, section "foo"
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@gsrc32u = global i32 1, align 2, section "foo"
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@gdst16u = global i16 2, align 1, section "foo"
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@gdst32u = global i32 2, align 2, section "foo"
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; Check sign-extending loads from i16.
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define i32 @f1() {
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@ -47,3 +51,49 @@ define void @f4() {
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store i32 %val, i32 *@gdst32
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ret void
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}
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; Repeat f1 with an unaligned variable.
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define i32 @f5() {
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; CHECK: f5:
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; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
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; CHECK: lh %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i16 *@gsrc16u, align 1
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%ext = sext i16 %val to i32
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ret i32 %ext
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}
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; Repeat f2 with an unaligned variable.
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define i32 @f6() {
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; CHECK: f6:
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; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
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; CHECK: llh %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i16 *@gsrc16u, align 1
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%ext = zext i16 %val to i32
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ret i32 %ext
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}
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; Repeat f3 with an unaligned variable.
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define void @f7(i32 %val) {
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; CHECK: f7:
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; CHECK: lgrl [[REG:%r[0-5]]], gdst16u
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; CHECK: sth %r2, 0([[REG]])
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; CHECK: br %r14
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%half = trunc i32 %val to i16
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store i16 %half, i16 *@gdst16u, align 1
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ret void
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}
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; Repeat f4 with unaligned variables.
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define void @f8() {
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; CHECK: f8:
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; CHECK: larl [[REG:%r[0-5]]], gsrc32u
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; CHECK: l [[VAL:%r[0-5]]], 0([[REG]])
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; CHECK: larl [[REG:%r[0-5]]], gdst32u
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; CHECK: st [[VAL]], 0([[REG]])
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; CHECK: br %r14
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%val = load i32 *@gsrc32u, align 2
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store i32 %val, i32 *@gdst32u, align 2
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ret void
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}
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@ -8,6 +8,12 @@
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@gdst16 = global i16 2
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@gdst32 = global i32 2
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@gdst64 = global i64 2
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@gsrc16u = global i16 1, align 1, section "foo"
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@gsrc32u = global i32 1, align 2, section "foo"
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@gsrc64u = global i64 1, align 4, section "foo"
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@gdst16u = global i16 2, align 1, section "foo"
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@gdst32u = global i32 2, align 2, section "foo"
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@gdst64u = global i64 2, align 4, section "foo"
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; Check sign-extending loads from i16.
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define i64 @f1() {
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@ -79,3 +85,82 @@ define void @f7() {
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store i64 %val, i64 *@gdst64
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ret void
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}
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; Repeat f1 with an unaligned variable.
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define i64 @f8() {
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; CHECK: f8:
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; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
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; CHECK: lgh %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i16 *@gsrc16u, align 1
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%ext = sext i16 %val to i64
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ret i64 %ext
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}
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; Repeat f2 with an unaligned variable.
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define i64 @f9() {
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; CHECK: f9:
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; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
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; CHECK: llgh %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i16 *@gsrc16u, align 1
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||||
%ext = zext i16 %val to i64
|
||||
ret i64 %ext
|
||||
}
|
||||
|
||||
; Repeat f3 with an unaligned variable.
|
||||
define i64 @f10() {
|
||||
; CHECK: f10:
|
||||
; CHECK: larl [[REG:%r[0-5]]], gsrc32u
|
||||
; CHECK: lgf %r2, 0([[REG]])
|
||||
; CHECK: br %r14
|
||||
%val = load i32 *@gsrc32u, align 2
|
||||
%ext = sext i32 %val to i64
|
||||
ret i64 %ext
|
||||
}
|
||||
|
||||
; Repeat f4 with an unaligned variable.
|
||||
define i64 @f11() {
|
||||
; CHECK: f11:
|
||||
; CHECK: larl [[REG:%r[0-5]]], gsrc32u
|
||||
; CHECK: llgf %r2, 0([[REG]])
|
||||
; CHECK: br %r14
|
||||
%val = load i32 *@gsrc32u, align 2
|
||||
%ext = zext i32 %val to i64
|
||||
ret i64 %ext
|
||||
}
|
||||
|
||||
; Repeat f5 with an unaligned variable.
|
||||
define void @f12(i64 %val) {
|
||||
; CHECK: f12:
|
||||
; CHECK: lgrl [[REG:%r[0-5]]], gdst16u@GOT
|
||||
; CHECK: sth %r2, 0([[REG]])
|
||||
; CHECK: br %r14
|
||||
%half = trunc i64 %val to i16
|
||||
store i16 %half, i16 *@gdst16u, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
; Repeat f6 with an unaligned variable.
|
||||
define void @f13(i64 %val) {
|
||||
; CHECK: f13:
|
||||
; CHECK: larl [[REG:%r[0-5]]], gdst32u
|
||||
; CHECK: st %r2, 0([[REG]])
|
||||
; CHECK: br %r14
|
||||
%word = trunc i64 %val to i32
|
||||
store i32 %word, i32 *@gdst32u, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Repeat f7 with unaligned variables.
|
||||
define void @f14() {
|
||||
; CHECK: f14:
|
||||
; CHECK: larl [[REG:%r[0-5]]], gsrc64u
|
||||
; CHECK: lg [[VAL:%r[0-5]]], 0([[REG]])
|
||||
; CHECK: larl [[REG:%r[0-5]]], gdst64u
|
||||
; CHECK: stg [[VAL]], 0([[REG]])
|
||||
; CHECK: br %r14
|
||||
%val = load i64 *@gsrc64u, align 4
|
||||
store i64 %val, i64 *@gdst64u, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,59 @@
|
|||
; Check that unaligned accesses are allowed in general. We check the
|
||||
; few exceptions (like CRL) in their respective test files.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
; Check that these four byte stores become a single word store.
|
||||
define void @f1(i8 *%ptr) {
|
||||
; CHECK: f1
|
||||
; CHECK: iilf [[REG:%r[0-5]]], 66051
|
||||
; CHECK: st [[REG]], 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%off1 = getelementptr i8 *%ptr, i64 1
|
||||
%off2 = getelementptr i8 *%ptr, i64 2
|
||||
%off3 = getelementptr i8 *%ptr, i64 3
|
||||
store i8 0, i8 *%ptr
|
||||
store i8 1, i8 *%off1
|
||||
store i8 2, i8 *%off2
|
||||
store i8 3, i8 *%off3
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that unaligned 2-byte accesses are allowed.
|
||||
define i16 @f2(i16 *%src, i16 *%dst) {
|
||||
; CHECK: f2:
|
||||
; CHECK: lh %r2, 0(%r2)
|
||||
; CHECK: sth %r2, 0(%r3)
|
||||
; CHECK: br %r14
|
||||
%val = load i16 *%src, align 1
|
||||
store i16 %val, i16 *%dst, align 1
|
||||
ret i16 %val
|
||||
}
|
||||
|
||||
; Check that unaligned 4-byte accesses are allowed.
|
||||
define i32 @f3(i32 *%src1, i32 *%src2, i32 *%dst) {
|
||||
; CHECK: f3:
|
||||
; CHECK: l %r2, 0(%r2)
|
||||
; CHECK: s %r2, 0(%r3)
|
||||
; CHECK: st %r2, 0(%r4)
|
||||
; CHECK: br %r14
|
||||
%val1 = load i32 *%src1, align 1
|
||||
%val2 = load i32 *%src2, align 2
|
||||
%sub = sub i32 %val1, %val2
|
||||
store i32 %sub, i32 *%dst, align 1
|
||||
ret i32 %sub
|
||||
}
|
||||
|
||||
; Check that unaligned 8-byte accesses are allowed.
|
||||
define i64 @f4(i64 *%src1, i64 *%src2, i64 *%dst) {
|
||||
; CHECK: f4:
|
||||
; CHECK: lg %r2, 0(%r2)
|
||||
; CHECK: sg %r2, 0(%r3)
|
||||
; CHECK: stg %r2, 0(%r4)
|
||||
; CHECK: br %r14
|
||||
%val1 = load i64 *%src1, align 1
|
||||
%val2 = load i64 *%src2, align 2
|
||||
%sub = sub i64 %val1, %val2
|
||||
store i64 %sub, i64 *%dst, align 4
|
||||
ret i64 %sub
|
||||
}
|
||||
Loading…
Reference in New Issue