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More dead code removal (using -Wunreachable-code) 

llvm-svn: 148578
This commit is contained in:
David Blaikie 2012-01-20 21:51:11 +00:00
parent e4d798f078
commit 46a9f016c5
110 changed files with 179 additions and 442 deletions
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1
llvm/include/llvm/CodeGen/ValueTypes.h
View File

@ -446,7 +446,6 @@ namespace llvm {
case 8: return MVT::v8i8;
case 16: return MVT::v16i8;
}
return MVT::INVALID_SIMPLE_VALUE_TYPE;
}
/// changeVectorElementTypeToInteger - Return a vector with the same number

2
llvm/include/llvm/Target/TargetJITInfo.h
View File

@ -58,8 +58,6 @@ namespace llvm {
/// Returns the maximum size and alignment for a call stub on this target.
virtual StubLayout getStubLayout() {
llvm_unreachable("This target doesn't implement getStubLayout!");
StubLayout Result = {0, 0};
return Result;
}
/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a

1
llvm/include/llvm/Target/TargetLowering.h
View File

@ -297,7 +297,6 @@ public:
return VT;
}
}
return VT;
}
/// getVectorTypeBreakdown - Vector types are broken down into some number of

2
llvm/lib/Analysis/ConstantFolding.cpp
View File

@ -1125,7 +1125,6 @@ static Constant *ConstantFoldFP(double (*NativeFP)(double), double V,
if (Ty->isDoubleTy())
return ConstantFP::get(Ty->getContext(), APFloat(V));
llvm_unreachable("Can only constant fold float/double");
return 0; // dummy return to suppress warning
}
static Constant *ConstantFoldBinaryFP(double (*NativeFP)(double, double),
@ -1142,7 +1141,6 @@ static Constant *ConstantFoldBinaryFP(double (*NativeFP)(double, double),
if (Ty->isDoubleTy())
return ConstantFP::get(Ty->getContext(), APFloat(V));
llvm_unreachable("Can only constant fold float/double");
return 0; // dummy return to suppress warning
}
/// ConstantFoldConvertToInt - Attempt to an SSE floating point to integer

2
llvm/lib/Analysis/LoopDependenceAnalysis.cpp
View File

@ -91,8 +91,6 @@ static Value *GetPointerOperand(Value *I) {
if (StoreInst *i = dyn_cast<StoreInst>(I))
return i->getPointerOperand();
llvm_unreachable("Value is no load or store instruction!");
// Never reached.
return 0;
}
static AliasAnalysis::AliasResult UnderlyingObjectsAlias(AliasAnalysis *AA,

2
llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
View File

@ -329,8 +329,6 @@ getLoadLoadClobberFullWidthSize(const Value *MemLocBase, int64_t MemLocOffs,
NewLoadByteSize <<= 1;
}
return 0;
}
namespace {

2
llvm/lib/Analysis/PHITransAddr.cpp
View File

@ -74,7 +74,6 @@ static bool VerifySubExpr(Value *Expr,
errs() << *I << '\n';
llvm_unreachable("Either something is missing from InstInputs or "
"CanPHITrans is wrong.");
return false;
}
// Validate the operands of the instruction.
@ -101,7 +100,6 @@ bool PHITransAddr::Verify() const {
for (unsigned i = 0, e = InstInputs.size(); i != e; ++i)
errs() << " InstInput #" << i << " is " << *InstInputs[i] << "\n";
llvm_unreachable("This is unexpected.");
return false;
}
// a-ok.

30
llvm/lib/Analysis/ScalarEvolution.cpp
View File

@ -259,11 +259,9 @@ Type *SCEV::getType() const {
return cast<SCEVUnknown>(this)->getType();
case scCouldNotCompute:
llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
return 0;
default: break;
default:
llvm_unreachable("Unknown SCEV kind!");
}
llvm_unreachable("Unknown SCEV kind!");
return 0;
}
bool SCEV::isZero() const {
@ -611,11 +609,8 @@ namespace {
}
default:
break;
llvm_unreachable("Unknown SCEV kind!");
}
llvm_unreachable("Unknown SCEV kind!");
return 0;
}
};
}
@ -5319,7 +5314,6 @@ const SCEV *ScalarEvolution::computeSCEVAtScope(const SCEV *V, const Loop *L) {
}
llvm_unreachable("Unknown SCEV type!");
return 0;
}
/// getSCEVAtScope - This is a convenience function which does
@ -5950,7 +5944,6 @@ ScalarEvolution::isKnownPredicateWithRanges(ICmpInst::Predicate Pred,
switch (Pred) {
default:
llvm_unreachable("Unexpected ICmpInst::Predicate value!");
break;
case ICmpInst::ICMP_SGT:
Pred = ICmpInst::ICMP_SLT;
std::swap(LHS, RHS);
@ -6801,11 +6794,8 @@ ScalarEvolution::computeLoopDisposition(const SCEV *S, const Loop *L) {
return LoopInvariant;
case scCouldNotCompute:
llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
return LoopVariant;
default: break;
default: llvm_unreachable("Unknown SCEV kind!");
}
llvm_unreachable("Unknown SCEV kind!");
return LoopVariant;
}
bool ScalarEvolution::isLoopInvariant(const SCEV *S, const Loop *L) {
@ -6887,11 +6877,9 @@ ScalarEvolution::computeBlockDisposition(const SCEV *S, const BasicBlock *BB) {
return ProperlyDominatesBlock;
case scCouldNotCompute:
llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
return DoesNotDominateBlock;
default: break;
default:
llvm_unreachable("Unknown SCEV kind!");
}
llvm_unreachable("Unknown SCEV kind!");
return DoesNotDominateBlock;
}
bool ScalarEvolution::dominates(const SCEV *S, const BasicBlock *BB) {
@ -6937,11 +6925,9 @@ bool ScalarEvolution::hasOperand(const SCEV *S, const SCEV *Op) const {
return false;
case scCouldNotCompute:
llvm_unreachable("Attempt to use a SCEVCouldNotCompute object!");
return false;
default: break;
default:
llvm_unreachable("Unknown SCEV kind!");
}
llvm_unreachable("Unknown SCEV kind!");
return false;
}
void ScalarEvolution::forgetMemoizedResults(const SCEV *S) {

1
llvm/lib/Analysis/ScalarEvolutionExpander.cpp
View File

@ -650,7 +650,6 @@ const Loop *SCEVExpander::getRelevantLoop(const SCEV *S) {
return RelevantLoops[D] = Result;
}
llvm_unreachable("Unexpected SCEV type!");
return 0;
}
namespace {

1
llvm/lib/Analysis/ScalarEvolutionNormalization.cpp
View File

@ -190,7 +190,6 @@ TransformImpl(const SCEV *S, Instruction *User, Value *OperandValToReplace) {
}
llvm_unreachable("Unexpected SCEV kind!");
return 0;
}
/// Manage recursive transformation across an expression DAG. Revisiting

8
llvm/lib/AsmParser/LLParser.cpp
View File

@ -1043,13 +1043,11 @@ bool LLParser::ParseOptionalCallingConv(CallingConv::ID &CC) {
case lltok::kw_cc: {
unsigned ArbitraryCC;
Lex.Lex();
if (ParseUInt32(ArbitraryCC)) {
if (ParseUInt32(ArbitraryCC))
return true;
} else
CC = static_cast<CallingConv::ID>(ArbitraryCC);
return false;
CC = static_cast<CallingConv::ID>(ArbitraryCC);
return false;
}
break;
}
Lex.Lex();

8
llvm/lib/CodeGen/Analysis.cpp
View File

@ -167,10 +167,8 @@ ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) {
case FCmpInst::FCMP_ULE: return ISD::SETULE;
case FCmpInst::FCMP_UNE: return ISD::SETUNE;
case FCmpInst::FCMP_TRUE: return ISD::SETTRUE;
default: break;
default: llvm_unreachable("Invalid FCmp predicate opcode!");
}
llvm_unreachable("Invalid FCmp predicate opcode!");
return ISD::SETFALSE;
}
ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) {
@ -181,9 +179,8 @@ ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) {
case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE;
case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT;
case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE;
default: break;
default: return CC;
}
return CC;
}
/// getICmpCondCode - Return the ISD condition code corresponding to
@ -203,7 +200,6 @@ ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) {
case ICmpInst::ICMP_UGT: return ISD::SETUGT;
default:
llvm_unreachable("Invalid ICmp predicate opcode!");
return ISD::SETNE;
}
}

5
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -1136,7 +1136,7 @@ void AsmPrinter::EmitJumpTableEntry(const MachineJumpTableInfo *MJTI,
const MCExpr *Value = 0;
switch (MJTI->getEntryKind()) {
case MachineJumpTableInfo::EK_Inline:
llvm_unreachable("Cannot emit EK_Inline jump table entry"); break;
llvm_unreachable("Cannot emit EK_Inline jump table entry");
case MachineJumpTableInfo::EK_Custom32:
Value = TM.getTargetLowering()->LowerCustomJumpTableEntry(MJTI, MBB, UID,
OutContext);
@ -1439,7 +1439,6 @@ static const MCExpr *LowerConstant(const Constant *CV, AsmPrinter &AP) {
const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV);
if (CE == 0) {
llvm_unreachable("Unknown constant value to lower!");
return MCConstantExpr::Create(0, Ctx);
}
switch (CE->getOpcode()) {
@ -1461,7 +1460,6 @@ static const MCExpr *LowerConstant(const Constant *CV, AsmPrinter &AP) {
!AP.MF ? 0 : AP.MF->getFunction()->getParent());
report_fatal_error(OS.str());
}
return MCConstantExpr::Create(0, Ctx);
case Instruction::GetElementPtr: {
const TargetData &TD = *AP.TM.getTargetData();
// Generate a symbolic expression for the byte address
@ -2140,5 +2138,4 @@ GCMetadataPrinter *AsmPrinter::GetOrCreateGCPrinter(GCStrategy *S) {
}
report_fatal_error("no GCMetadataPrinter registered for GC: " + Twine(Name));
return 0;
}

6
llvm/lib/CodeGen/AsmPrinter/DIE.cpp
View File

@ -224,9 +224,8 @@ unsigned DIEInteger::SizeOf(AsmPrinter *AP, unsigned Form) const {
case dwarf::DW_FORM_udata: return MCAsmInfo::getULEB128Size(Integer);
case dwarf::DW_FORM_sdata: return MCAsmInfo::getSLEB128Size(Integer);
case dwarf::DW_FORM_addr: return AP->getTargetData().getPointerSize();
default: llvm_unreachable("DIE Value form not supported yet"); break;
default: llvm_unreachable("DIE Value form not supported yet");
}
return 0;
}
#ifndef NDEBUG
@ -340,9 +339,8 @@ unsigned DIEBlock::SizeOf(AsmPrinter *AP, unsigned Form) const {
case dwarf::DW_FORM_block2: return Size + sizeof(int16_t);
case dwarf::DW_FORM_block4: return Size + sizeof(int32_t);
case dwarf::DW_FORM_block: return Size + MCAsmInfo::getULEB128Size(Size);
default: llvm_unreachable("Improper form for block"); break;
default: llvm_unreachable("Improper form for block");
}
return 0;
}
#ifndef NDEBUG

3
llvm/lib/CodeGen/BranchFolding.cpp
View File

@ -483,8 +483,9 @@ BranchFolder::MergePotentialsElt::operator<(const MergePotentialsElt &o) const {
// an object with itself.
#ifndef _GLIBCXX_DEBUG
llvm_unreachable("Predecessor appears twice");
#endif
#else
return false;
#endif
}
}

2
llvm/lib/CodeGen/GCStrategy.cpp
View File

@ -114,14 +114,12 @@ bool GCStrategy::initializeCustomLowering(Module &M) { return false; }
bool GCStrategy::performCustomLowering(Function &F) {
dbgs() << "gc " << getName() << " must override performCustomLowering.\n";
llvm_unreachable(0);
return 0;
}
bool GCStrategy::findCustomSafePoints(GCFunctionInfo& FI, MachineFunction &F) {
dbgs() << "gc " << getName() << " must override findCustomSafePoints.\n";
llvm_unreachable(0);
return 0;
}

1
llvm/lib/CodeGen/MachineSSAUpdater.cpp
View File

@ -214,7 +214,6 @@ MachineBasicBlock *findCorrespondingPred(const MachineInstr *MI,
}
llvm_unreachable("MachineOperand::getParent() failure?");
return 0;
}
/// RewriteUse - Rewrite a use of the symbolic value. This handles PHI nodes,

2
llvm/lib/CodeGen/PseudoSourceValue.cpp
View File

@ -87,7 +87,6 @@ bool PseudoSourceValue::isConstant(const MachineFrameInfo *) const {
this == getJumpTable())
return true;
llvm_unreachable("Unknown PseudoSourceValue!");
return false;
}
bool PseudoSourceValue::isAliased(const MachineFrameInfo *MFI) const {
@ -97,7 +96,6 @@ bool PseudoSourceValue::isAliased(const MachineFrameInfo *MFI) const {
this == getJumpTable())
return false;
llvm_unreachable("Unknown PseudoSourceValue!");
return true;
}
bool PseudoSourceValue::mayAlias(const MachineFrameInfo *MFI) const {

2
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -801,10 +801,8 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
Node->dump();
#endif
llvm_unreachable("This target-independent node should have been selected!");
break;
case ISD::EntryToken:
llvm_unreachable("EntryToken should have been excluded from the schedule!");
break;
case ISD::MERGE_VALUES:
case ISD::TokenFactor: // fall thru
break;

1
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -2438,7 +2438,6 @@ std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
switch (Opc) {
default:
llvm_unreachable("Unhandled atomic intrinsic Expand!");
break;
case ISD::ATOMIC_SWAP:
switch (VT.SimpleTy) {
default: llvm_unreachable("Unexpected value type for atomic!");

3
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1179,7 +1179,6 @@ std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
switch (Opc) {
default:
llvm_unreachable("Unhandled atomic intrinsic Expand!");
break;
case ISD::ATOMIC_SWAP:
switch (VT.SimpleTy) {
default: llvm_unreachable("Unexpected value type for atomic!");
@ -1501,8 +1500,6 @@ ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
return true;
}
return false;
}
void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,

12
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2245,8 +2245,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
if (Tmp2 == 1) return 1;
return std::min(Tmp, Tmp2)-1;
break;
return std::min(Tmp, Tmp2)-1;
case ISD::SUB:
Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
@ -2275,8 +2274,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
// is, at worst, one more bit than the inputs.
Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
if (Tmp == 1) return 1; // Early out.
return std::min(Tmp, Tmp2)-1;
break;
return std::min(Tmp, Tmp2)-1;
case ISD::TRUNCATE:
// FIXME: it's tricky to do anything useful for this, but it is an important
// case for targets like X86.
@ -3160,16 +3158,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
case ISD::SELECT:
if (N1C) {
if (N1C->getZExtValue())
return N2; // select true, X, Y -> X
else
return N3; // select false, X, Y -> Y
return N2; // select true, X, Y -> X
return N3; // select false, X, Y -> Y
}
if (N2 == N3) return N2; // select C, X, X -> X
break;
case ISD::VECTOR_SHUFFLE:
llvm_unreachable("should use getVectorShuffle constructor!");
break;
case ISD::INSERT_SUBVECTOR: {
SDValue Index = N3;
if (VT.isSimple() && N1.getValueType().isSimple()

6
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -206,7 +206,6 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
llvm_unreachable("Unknown mismatch!");
return SDValue();
}
/// getCopyFromParts - Create a value that contains the specified legal parts
@ -1128,7 +1127,6 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
}
llvm_unreachable("Can't get register for value!");
return SDValue();
}
void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
@ -3379,7 +3377,7 @@ void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
DebugLoc dl = getCurDebugLoc();
ISD::NodeType NT;
switch (I.getOperation()) {
default: llvm_unreachable("Unknown atomicrmw operation"); return;
default: llvm_unreachable("Unknown atomicrmw operation");
case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
@ -5064,7 +5062,6 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
case Intrinsic::gcread:
case Intrinsic::gcwrite:
llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
return 0;
case Intrinsic::flt_rounds:
setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
return 0;
@ -6605,7 +6602,6 @@ void TargetLowering::LowerOperationWrapper(SDNode *N,
SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
llvm_unreachable("LowerOperation not implemented for this target!");
return SDValue();
}
void

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -249,7 +249,6 @@ TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
"TargetLowering::EmitInstrWithCustomInserter!";
#endif
llvm_unreachable(0);
return 0;
}
void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
@ -981,7 +980,6 @@ static void collectFailStats(const Instruction *I) {
case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
}
return;
}
#endif

1
llvm/lib/CodeGen/SplitKit.cpp
View File

@ -1072,7 +1072,6 @@ void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
break;
case SM_Speed:
llvm_unreachable("Spill mode 'speed' not implemented yet");
break;
}
// Transfer the simply mapped values, check if any are skipped.

4
llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
View File

@ -53,11 +53,9 @@ TargetLoweringObjectFileELF::getCFIPersonalitySymbol(const GlobalValue *GV,
report_fatal_error("We do not support this DWARF encoding yet!");
case dwarf::DW_EH_PE_absptr:
return Mang->getSymbol(GV);
break;
case dwarf::DW_EH_PE_pcrel: {
return getContext().GetOrCreateSymbol(StringRef("DW.ref.") +
Mang->getSymbol(GV)->getName());
break;
}
}
}
@ -361,8 +359,6 @@ getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,
report_fatal_error("Global variable '" + GV->getName() +
"' has an invalid section specifier '" +
GV->getSection() + "': " + ErrorCode + ".");
// Fall back to dropping it into the data section.
return DataSection;
}
// Get the section.

2
llvm/lib/DebugInfo/DWARFDebugInfoEntry.cpp
View File

@ -203,8 +203,6 @@ bool DWARFDebugInfoEntryMinimal::extractFast(const DWARFCompileUnit *cu,
AbbrevDecl = NULL;
return true; // NULL debug tag entry
}
return false;
}
bool

2
llvm/lib/ExecutionEngine/ExecutionEngineBindings.cpp
View File

@ -76,9 +76,7 @@ double LLVMGenericValueToFloat(LLVMTypeRef TyRef, LLVMGenericValueRef GenVal) {
return unwrap(GenVal)->DoubleVal;
default:
llvm_unreachable("LLVMGenericValueToFloat supports only float and double.");
break;
}
return 0; // Not reached
}
void LLVMDisposeGenericValue(LLVMGenericValueRef GenVal) {

1
llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
View File

@ -1254,7 +1254,6 @@ GenericValue Interpreter::getConstantExprValue (ConstantExpr *CE,
default:
dbgs() << "Unhandled ConstantExpr: " << *CE << "\n";
llvm_unreachable(0);
return GenericValue();
}
return Dest;
}

1
llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp
View File

@ -409,7 +409,6 @@ GenericValue lle_X_sprintf(FunctionType *FT,
break;
}
}
return GV;
}
// int printf(const char *, ...) - a very rough implementation to make output

1
llvm/lib/ExecutionEngine/JIT/JIT.cpp
View File

@ -475,7 +475,6 @@ GenericValue JIT::runFunction(Function *F,
case Type::FP128TyID:
case Type::PPC_FP128TyID:
llvm_unreachable("long double not supported yet");
return rv;
case Type::PointerTyID:
return PTOGV(((void*(*)())(intptr_t)FPtr)());
}

2
llvm/lib/ExecutionEngine/MCJIT/MCJIT.cpp
View File

@ -90,7 +90,6 @@ MCJIT::~MCJIT() {
void *MCJIT::getPointerToBasicBlock(BasicBlock *BB) {
report_fatal_error("not yet implemented");
return 0;
}
void *MCJIT::getPointerToFunction(Function *F) {
@ -209,7 +208,6 @@ GenericValue MCJIT::runFunction(Function *F,
case Type::FP128TyID:
case Type::PPC_FP128TyID:
llvm_unreachable("long double not supported yet");
return rv;
case Type::PointerTyID:
return PTOGV(((void*(*)())(intptr_t)FPtr)());
}

1
llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp
View File

@ -72,7 +72,6 @@ resolveX86_64Relocation(uintptr_t Address, uintptr_t Value, bool isPCRel,
case macho::RIT_X86_64_TLV:
return Error("Relocation type not implemented yet!");
}
return false;
}
bool RuntimeDyldMachO::

3
llvm/lib/MC/MCDisassembler/Disassembler.cpp
View File

@ -18,6 +18,7 @@
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/MemoryObject.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
namespace llvm {
class Target;
@ -163,5 +164,5 @@ size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
return Size;
}
}
return 0;
llvm_unreachable("Invalid DecodeStatus!");
}

4
llvm/lib/MC/MCDisassembler/EDOperand.cpp
View File

@ -200,7 +200,6 @@ int EDOperand::evaluate(uint64_t &result,
return 0;
}
} // switch (operandType)
break;
case Triple::arm:
case Triple::thumb:
switch (operandType) {
@ -236,10 +235,7 @@ int EDOperand::evaluate(uint64_t &result,
return 0;
}
}
break;
}
return -1;
}
int EDOperand::isRegister() {

1
llvm/lib/MC/MCParser/AsmParser.cpp
View File

@ -827,7 +827,6 @@ bool AsmParser::ParseExpression(const MCExpr *&Res, SMLoc &EndLoc) {
if (!ModifiedRes) {
return TokError("invalid modifier '" + getTok().getIdentifier() +
"' (no symbols present)");
return true;
}
Res = ModifiedRes;

1
llvm/lib/MC/MCPureStreamer.cpp
View File

@ -96,7 +96,6 @@ public:
virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Directory,
StringRef Filename) {
report_fatal_error("unsupported directive in pure streamer");
return false;
}
/// @}

1
llvm/lib/MC/WinCOFFStreamer.cpp
View File

@ -253,7 +253,6 @@ void WinCOFFStreamer::EmitSymbolAttribute(MCSymbol *Symbol,
default:
llvm_unreachable("unsupported attribute");
break;
}
}

9
llvm/lib/Support/Triple.cpp
View File

@ -10,6 +10,7 @@
#include "llvm/ADT/Triple.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/ErrorHandling.h"
#include <cstring>
using namespace llvm;
@ -42,7 +43,7 @@ const char *Triple::getArchTypeName(ArchType Kind) {
case amdil: return "amdil";
}
return "<invalid>";
llvm_unreachable("Invalid ArchType!");
}
const char *Triple::getArchTypePrefix(ArchType Kind) {
@ -86,7 +87,7 @@ const char *Triple::getVendorTypeName(VendorType Kind) {
case SCEI: return "scei";
}
return "<invalid>";
llvm_unreachable("Invalid VendorType!");
}
const char *Triple::getOSTypeName(OSType Kind) {
@ -115,7 +116,7 @@ const char *Triple::getOSTypeName(OSType Kind) {
case NativeClient: return "nacl";
}
return "<invalid>";
llvm_unreachable("Invalid OSType");
}
const char *Triple::getEnvironmentTypeName(EnvironmentType Kind) {
@ -129,7 +130,7 @@ const char *Triple::getEnvironmentTypeName(EnvironmentType Kind) {
case ANDROIDEABI: return "androideabi";
}
return "<invalid>";
llvm_unreachable("Invalid EnvironmentType!");
}
Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {

5
llvm/lib/TableGen/TGParser.cpp
View File

@ -318,7 +318,6 @@ Init *TGParser::ParseObjectName(MultiClass *CurMultiClass) {
// Some of these can also begin values but we disallow those cases
// because they are unlikely to be useful.
return StringInit::get(GetNewAnonymousName());
break;
default:
break;
}
@ -722,7 +721,6 @@ Init *TGParser::ParseOperation(Record *CurRec) {
default:
TokError("unknown operation");
return 0;
break;
case tgtok::XHead:
case tgtok::XTail:
case tgtok::XEmpty:
@ -1026,8 +1024,6 @@ Init *TGParser::ParseOperation(Record *CurRec) {
CurMultiClass);
}
}
TokError("could not parse operation");
return 0;
}
/// ParseOperatorType - Parse a type for an operator. This returns
@ -1088,7 +1084,6 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType,
// still exists in some .td files. Ignore it.
Lex.Lex(); // Skip '#'.
return ParseSimpleValue(CurRec, ItemType, Mode);
break;
case tgtok::IntVal: R = IntInit::get(Lex.getCurIntVal()); Lex.Lex(); break;
case tgtok::StrVal: {
std::string Val = Lex.getCurStrVal();

2
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -824,7 +824,7 @@ getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
}
return MCSymbolRefExpr::VK_None;
llvm_unreachable("Invalid ARMCPModifier!");
}
MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {

166
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -558,85 +558,84 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
if (MCID.getSize())
return MCID.getSize();
// If this machine instr is an inline asm, measure it.
if (MI->getOpcode() == ARM::INLINEASM)
return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
if (MI->isLabel())
return 0;
unsigned Opc = MI->getOpcode();
switch (Opc) {
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::EH_LABEL:
case TargetOpcode::DBG_VALUE:
return 0;
case TargetOpcode::BUNDLE:
return getInstBundleLength(MI);
case ARM::MOVi16_ga_pcrel:
case ARM::MOVTi16_ga_pcrel:
case ARM::t2MOVi16_ga_pcrel:
case ARM::t2MOVTi16_ga_pcrel:
return 4;
case ARM::MOVi32imm:
case ARM::t2MOVi32imm:
return 8;
case ARM::CONSTPOOL_ENTRY:
// If this machine instr is a constant pool entry, its size is recorded as
// operand #2.
return MI->getOperand(2).getImm();
case ARM::Int_eh_sjlj_longjmp:
return 16;
case ARM::tInt_eh_sjlj_longjmp:
return 10;
case ARM::Int_eh_sjlj_setjmp:
case ARM::Int_eh_sjlj_setjmp_nofp:
return 20;
case ARM::tInt_eh_sjlj_setjmp:
case ARM::t2Int_eh_sjlj_setjmp:
case ARM::t2Int_eh_sjlj_setjmp_nofp:
return 12;
case ARM::BR_JTr:
case ARM::BR_JTm:
case ARM::BR_JTadd:
case ARM::tBR_JTr:
case ARM::t2BR_JT:
case ARM::t2TBB_JT:
case ARM::t2TBH_JT: {
// These are jumptable branches, i.e. a branch followed by an inlined
// jumptable. The size is 4 + 4 * number of entries. For TBB, each
// entry is one byte; TBH two byte each.
unsigned EntrySize = (Opc == ARM::t2TBB_JT)
? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
unsigned NumOps = MCID.getNumOperands();
MachineOperand JTOP =
MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
unsigned JTI = JTOP.getIndex();
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
assert(MJTI != 0);
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
assert(JTI < JT.size());
// Thumb instructions are 2 byte aligned, but JT entries are 4 byte
// 4 aligned. The assembler / linker may add 2 byte padding just before
// the JT entries. The size does not include this padding; the
// constant islands pass does separate bookkeeping for it.
// FIXME: If we know the size of the function is less than (1 << 16) *2
// bytes, we can use 16-bit entries instead. Then there won't be an
// alignment issue.
unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
unsigned NumEntries = getNumJTEntries(JT, JTI);
if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
// Make sure the instruction that follows TBB is 2-byte aligned.
// FIXME: Constant island pass should insert an "ALIGN" instruction
// instead.
++NumEntries;
return NumEntries * EntrySize + InstSize;
}
default:
// Otherwise, pseudo-instruction sizes are zero.
return 0;
}
return 0; // Not reached
// If this machine instr is an inline asm, measure it.
if (MI->getOpcode() == ARM::INLINEASM)
return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
if (MI->isLabel())
return 0;
unsigned Opc = MI->getOpcode();
switch (Opc) {
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::EH_LABEL:
case TargetOpcode::DBG_VALUE:
return 0;
case TargetOpcode::BUNDLE:
return getInstBundleLength(MI);
case ARM::MOVi16_ga_pcrel:
case ARM::MOVTi16_ga_pcrel:
case ARM::t2MOVi16_ga_pcrel:
case ARM::t2MOVTi16_ga_pcrel:
return 4;
case ARM::MOVi32imm:
case ARM::t2MOVi32imm:
return 8;
case ARM::CONSTPOOL_ENTRY:
// If this machine instr is a constant pool entry, its size is recorded as
// operand #2.
return MI->getOperand(2).getImm();
case ARM::Int_eh_sjlj_longjmp:
return 16;
case ARM::tInt_eh_sjlj_longjmp:
return 10;
case ARM::Int_eh_sjlj_setjmp:
case ARM::Int_eh_sjlj_setjmp_nofp:
return 20;
case ARM::tInt_eh_sjlj_setjmp:
case ARM::t2Int_eh_sjlj_setjmp:
case ARM::t2Int_eh_sjlj_setjmp_nofp:
return 12;
case ARM::BR_JTr:
case ARM::BR_JTm:
case ARM::BR_JTadd:
case ARM::tBR_JTr:
case ARM::t2BR_JT:
case ARM::t2TBB_JT:
case ARM::t2TBH_JT: {
// These are jumptable branches, i.e. a branch followed by an inlined
// jumptable. The size is 4 + 4 * number of entries. For TBB, each
// entry is one byte; TBH two byte each.
unsigned EntrySize = (Opc == ARM::t2TBB_JT)
? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
unsigned NumOps = MCID.getNumOperands();
MachineOperand JTOP =
MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
unsigned JTI = JTOP.getIndex();
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
assert(MJTI != 0);
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
assert(JTI < JT.size());
// Thumb instructions are 2 byte aligned, but JT entries are 4 byte
// 4 aligned. The assembler / linker may add 2 byte padding just before
// the JT entries. The size does not include this padding; the
// constant islands pass does separate bookkeeping for it.
// FIXME: If we know the size of the function is less than (1 << 16) *2
// bytes, we can use 16-bit entries instead. Then there won't be an
// alignment issue.
unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
unsigned NumEntries = getNumJTEntries(JT, JTI);
if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
// Make sure the instruction that follows TBB is 2-byte aligned.
// FIXME: Constant island pass should insert an "ALIGN" instruction
// instead.
++NumEntries;
return NumEntries * EntrySize + InstSize;
}
default:
// Otherwise, pseudo-instruction sizes are zero.
return 0;
}
}
unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
@ -1472,13 +1471,12 @@ llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
int llvm::getMatchingCondBranchOpcode(int Opc) {
if (Opc == ARM::B)
return ARM::Bcc;
else if (Opc == ARM::tB)
if (Opc == ARM::tB)
return ARM::tBcc;
else if (Opc == ARM::t2B)
return ARM::t2Bcc;
if (Opc == ARM::t2B)
return ARM::t2Bcc;
llvm_unreachable("Unknown unconditional branch opcode!");
return 0;
}
@ -1651,7 +1649,6 @@ bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
}
default:
llvm_unreachable("Unsupported addressing mode!");
break;
}
Offset += InstrOffs * Scale;
@ -2013,7 +2010,6 @@ ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
switch (Opc) {
default:
llvm_unreachable("Unexpected multi-uops instruction!");
break;
case ARM::VLDMQIA:
case ARM::VSTMQIA:
return 2;

4
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -569,12 +569,10 @@ ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
llvm_unreachable("What is the exception register");
return 0;
}
unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
llvm_unreachable("What is the exception handler register");
return 0;
}
unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
@ -823,7 +821,6 @@ getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
}
default:
llvm_unreachable("Unsupported addressing mode!");
break;
}
return InstrOffs * Scale;
@ -1019,7 +1016,6 @@ bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
break;
default:
llvm_unreachable("Unsupported addressing mode!");
break;
}
Offset += getFrameIndexInstrOffset(MI, i);

3
llvm/lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -406,7 +406,6 @@ unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
case ARM_AM::ror:
case ARM_AM::rrx: return 3;
}
return 0;
}
/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
@ -532,7 +531,6 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
switch (MI.getDesc().TSFlags & ARMII::FormMask) {
default: {
llvm_unreachable("Unhandled instruction encoding format!");
break;
}
case ARMII::MiscFrm:
if (MI.getOpcode() == ARM::LEApcrelJT) {
@ -541,7 +539,6 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
break;
}
llvm_unreachable("Unhandled instruction encoding!");
break;
case ARMII::Pseudo:
emitPseudoInstruction(MI);
break;

1
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -730,7 +730,6 @@ InitialFunctionScan(const std::vector<MachineInstr*> &CPEMIs) {
switch (Opc) {
default:
llvm_unreachable("Unknown addressing mode for CP reference!");
break;
// Taking the address of a CP entry.
case ARM::LEApcrel:

11
llvm/lib/Target/ARM/ARMELFWriterInfo.cpp
View File

@ -41,15 +41,14 @@ unsigned ARMELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
case ARM::reloc_arm_machine_cp_entry:
case ARM::reloc_arm_jt_base:
case ARM::reloc_arm_pic_jt:
assert(0 && "unsupported ARM relocation type"); break;
assert(0 && "unsupported ARM relocation type"); return 0;
case ARM::reloc_arm_branch: return ELF::R_ARM_CALL; break;
case ARM::reloc_arm_movt: return ELF::R_ARM_MOVT_ABS; break;
case ARM::reloc_arm_movw: return ELF::R_ARM_MOVW_ABS_NC; break;
case ARM::reloc_arm_branch: return ELF::R_ARM_CALL;
case ARM::reloc_arm_movt: return ELF::R_ARM_MOVT_ABS;
case ARM::reloc_arm_movw: return ELF::R_ARM_MOVW_ABS_NC;
default:
llvm_unreachable("unknown ARM relocation type"); break;
llvm_unreachable("unknown ARM relocation type");
}
return 0;
}
long int ARMELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,

2
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -1340,8 +1340,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
}
return false;
}
bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {

1
llvm/lib/Target/ARM/ARMFastISel.cpp
View File

@ -2340,7 +2340,6 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
return SelectCall(&I, "memset");
}
}
return false;
}
bool ARMFastISel::SelectTrunc(const Instruction *I) {

1
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -2192,7 +2192,6 @@ SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
default:
llvm_unreachable("Unknown so_reg opcode!");
break;
}
SDValue SOShImm =
CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);

8
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -3494,7 +3494,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
if (Op.getOperand(1).getValueType().isFloatingPoint()) {
switch (SetCCOpcode) {
default: llvm_unreachable("Illegal FP comparison"); break;
default: llvm_unreachable("Illegal FP comparison");
case ISD::SETUNE:
case ISD::SETNE: Invert = true; // Fallthrough
case ISD::SETOEQ:
@ -3533,7 +3533,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
} else {
// Integer comparisons.
switch (SetCCOpcode) {
default: llvm_unreachable("Illegal integer comparison"); break;
default: llvm_unreachable("Illegal integer comparison");
case ISD::SETNE: Invert = true;
case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
case ISD::SETLT: Swap = true;
@ -3740,7 +3740,6 @@ static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
default:
llvm_unreachable("unexpected size for isNEONModifiedImm");
return SDValue();
}
unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
@ -5063,7 +5062,6 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ATOMIC_LOAD:
case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
}
return SDValue();
}
/// ReplaceNodeResults - Replace the results of node with an illegal result
@ -5075,7 +5073,6 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
switch (N->getOpcode()) {
default:
llvm_unreachable("Don't know how to custom expand this!");
break;
case ISD::BITCAST:
Res = ExpandBITCAST(N, DAG);
break;
@ -8374,7 +8371,6 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
if (Scale & 1) return false;
return isPowerOf2_32(Scale);
}
break;
}
return true;
}

24
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -144,7 +144,6 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
case ARM_AM::db: return ARM::LDMDB;
case ARM_AM::ib: return ARM::LDMIB;
}
break;
case ARM::STRi12:
++NumSTMGened;
switch (Mode) {
@ -154,7 +153,6 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
case ARM_AM::db: return ARM::STMDB;
case ARM_AM::ib: return ARM::STMIB;
}
break;
case ARM::t2LDRi8:
case ARM::t2LDRi12:
++NumLDMGened;
@ -163,7 +161,6 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
case ARM_AM::ia: return ARM::t2LDMIA;
case ARM_AM::db: return ARM::t2LDMDB;
}
break;
case ARM::t2STRi8:
case ARM::t2STRi12:
++NumSTMGened;
@ -172,7 +169,6 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
case ARM_AM::ia: return ARM::t2STMIA;
case ARM_AM::db: return ARM::t2STMDB;
}
break;
case ARM::VLDRS:
++NumVLDMGened;
switch (Mode) {
@ -180,7 +176,6 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
case ARM_AM::ia: return ARM::VLDMSIA;
case ARM_AM::db: return 0; // Only VLDMSDB_UPD exists.
}
break;
case ARM::VSTRS:
++NumVSTMGened;
switch (Mode) {
@ -188,7 +183,6 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
case ARM_AM::ia: return ARM::VSTMSIA;
case ARM_AM::db: return 0; // Only VSTMSDB_UPD exists.
}
break;
case ARM::VLDRD:
++NumVLDMGened;
switch (Mode) {
@ -196,7 +190,6 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
case ARM_AM::ia: return ARM::VLDMDIA;
case ARM_AM::db: return 0; // Only VLDMDDB_UPD exists.
}
break;
case ARM::VSTRD:
++NumVSTMGened;
switch (Mode) {
@ -204,10 +197,7 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
case ARM_AM::ia: return ARM::VSTMDIA;
case ARM_AM::db: return 0; // Only VSTMDDB_UPD exists.
}
break;
}
return 0;
}
namespace llvm {
@ -262,8 +252,6 @@ AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
case ARM::STMIB_UPD:
return ARM_AM::ib;
}
return ARM_AM::bad_am_submode;
}
} // end namespace ARM_AM
@ -606,7 +594,6 @@ static unsigned getUpdatingLSMultipleOpcode(unsigned Opc,
case ARM_AM::da: return ARM::LDMDA_UPD;
case ARM_AM::db: return ARM::LDMDB_UPD;
}
break;
case ARM::STMIA:
case ARM::STMDA:
case ARM::STMDB:
@ -618,7 +605,6 @@ static unsigned getUpdatingLSMultipleOpcode(unsigned Opc,
case ARM_AM::da: return ARM::STMDA_UPD;
case ARM_AM::db: return ARM::STMDB_UPD;
}
break;
case ARM::t2LDMIA:
case ARM::t2LDMDB:
switch (Mode) {
@ -626,7 +612,6 @@ static unsigned getUpdatingLSMultipleOpcode(unsigned Opc,
case ARM_AM::ia: return ARM::t2LDMIA_UPD;
case ARM_AM::db: return ARM::t2LDMDB_UPD;
}
break;
case ARM::t2STMIA:
case ARM::t2STMDB:
switch (Mode) {
@ -634,38 +619,31 @@ static unsigned getUpdatingLSMultipleOpcode(unsigned Opc,
case ARM_AM::ia: return ARM::t2STMIA_UPD;
case ARM_AM::db: return ARM::t2STMDB_UPD;
}
break;
case ARM::VLDMSIA:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VLDMSIA_UPD;
case ARM_AM::db: return ARM::VLDMSDB_UPD;
}
break;
case ARM::VLDMDIA:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VLDMDIA_UPD;
case ARM_AM::db: return ARM::VLDMDDB_UPD;
}
break;
case ARM::VSTMSIA:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VSTMSIA_UPD;
case ARM_AM::db: return ARM::VSTMSDB_UPD;
}
break;
case ARM::VSTMDIA:
switch (Mode) {
default: llvm_unreachable("Unhandled submode!");
case ARM_AM::ia: return ARM::VSTMDIA_UPD;
case ARM_AM::db: return ARM::VSTMDDB_UPD;
}
break;
}
return 0;
}
/// MergeBaseUpdateLSMultiple - Fold proceeding/trailing inc/dec of base
@ -786,7 +764,6 @@ static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc,
return ARM::t2STR_PRE;
default: llvm_unreachable("Unhandled opcode!");
}
return 0;
}
static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc,
@ -812,7 +789,6 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc,
return ARM::t2STR_POST;
default: llvm_unreachable("Unhandled opcode!");
}
return 0;
}
/// MergeBaseUpdateLoadStore - Fold proceeding/trailing inc/dec of base

7
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -2500,7 +2500,7 @@ static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
// Use the same layout as the tablegen'erated register name matcher. Ugly,
// but efficient.
switch (Name.size()) {
default: break;
default: return -1;
case 2:
if (Name[0] != CoprocOp)
return -1;
@ -2517,7 +2517,6 @@ static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
case '8': return 8;
case '9': return 9;
}
break;
case 3:
if (Name[0] != CoprocOp || Name[1] != '1')
return -1;
@ -2530,10 +2529,7 @@ static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
case '4': return 14;
case '5': return 15;
}
break;
}
return -1;
}
/// parseITCondCode - Try to parse a condition code for an IT instruction.
@ -6384,7 +6380,6 @@ MatchAndEmitInstruction(SMLoc IDLoc,
}
llvm_unreachable("Implement any new match types added!");
return true;
}
/// parseDirective parses the arm specific directives

2
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -97,7 +97,7 @@ static bool Check(DecodeStatus &Out, DecodeStatus In) {
Out = In;
return false;
}
return false;
llvm_unreachable("Invalid DecodeStatus!");
}

2
llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
View File

@ -217,7 +217,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
default: llvm_unreachable("invalid fixup kind!");
case FK_Data_4:
switch (Modifier) {
default: llvm_unreachable("Unsupported Modifier"); break;
default: llvm_unreachable("Unsupported Modifier");
case MCSymbolRefExpr::VK_ARM_GOT:
Type = ELF::R_ARM_GOT_BREL;
break;

4
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -184,7 +184,7 @@ public:
case ARM_AM::ror:
case ARM_AM::rrx: return 3;
}
return 0;
llvm_unreachable("Invalid ShiftOpc!");
}
/// getAddrMode2OpValue - Return encoding for addrmode2 operands.
@ -422,7 +422,6 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
}
llvm_unreachable("Unable to encode MCOperand!");
return 0;
}
/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
@ -884,7 +883,6 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
};
llvm_unreachable("Unsupported MCExpr type in MCOperand!");
return 0;
}
uint32_t ARMMCCodeEmitter::

1
llvm/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
View File

@ -296,7 +296,6 @@ void ARMMachObjectWriter::RecordRelocation(MachObjectWriter *Writer,
unsigned RelocType = macho::RIT_Vanilla;
if (!getARMFixupKindMachOInfo(Fixup.getKind(), RelocType, Log2Size)) {
report_fatal_error("unknown ARM fixup kind!");
return;
}
// If this is a difference or a defined symbol plus an offset, then we need a

3
llvm/lib/Target/CBackend/CBackend.cpp
View File

@ -553,8 +553,6 @@ raw_ostream &CWriter::printType(raw_ostream &Out, Type *Ty,
default:
llvm_unreachable("Unhandled case in getTypeProps!");
}
return Out;
}
void CWriter::printConstantArray(ConstantArray *CPA, bool Static) {
@ -743,7 +741,6 @@ void CWriter::printCast(unsigned opc, Type *SrcTy, Type *DstTy) {
break; // These don't need a source cast.
default:
llvm_unreachable("Invalid cast opcode");
break;
}
}

1
llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp
View File

@ -248,7 +248,6 @@ void SPUAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) {
switch (MO.getType()) {
case MachineOperand::MO_Immediate:
report_fatal_error("printOp() does not handle immediate values");
return;
case MachineOperand::MO_MachineBasicBlock:
O << *MO.getMBB()->getSymbol();

15
llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -90,8 +90,6 @@ namespace {
short s_val = (short) i_val;
return i_val == s_val;
}
return false;
}
//! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
@ -286,8 +284,8 @@ namespace {
llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
#else
SelectAddrIdxOnly(Op, Op, Op0, Op1);
#endif
break;
#endif
}
OutOps.push_back(Op0);
@ -326,7 +324,7 @@ SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
val = dyn_cast<ConstantSDNode>(N.getNode())->getSExtValue();
Base = CurDAG->getTargetConstant( val , MVT::i32);
Index = Zero;
return true; break;
return true;
case ISD::ConstantPool:
case ISD::GlobalAddress:
report_fatal_error("SPU SelectAFormAddr: Pool/Global not lowered.");
@ -578,22 +576,16 @@ SDValue SPUDAGToDAGISel::getRC( MVT VT ) {
switch( VT.SimpleTy ) {
case MVT::i8:
return CurDAG->getTargetConstant(SPU::R8CRegClass.getID(), MVT::i32);
break;
case MVT::i16:
return CurDAG->getTargetConstant(SPU::R16CRegClass.getID(), MVT::i32);
break;
case MVT::i32:
return CurDAG->getTargetConstant(SPU::R32CRegClass.getID(), MVT::i32);
break;
case MVT::f32:
return CurDAG->getTargetConstant(SPU::R32FPRegClass.getID(), MVT::i32);
break;
case MVT::i64:
return CurDAG->getTargetConstant(SPU::R64CRegClass.getID(), MVT::i32);
break;
case MVT::i128:
return CurDAG->getTargetConstant(SPU::GPRCRegClass.getID(), MVT::i32);
break;
case MVT::v16i8:
case MVT::v8i16:
case MVT::v4i32:
@ -601,11 +593,10 @@ SDValue SPUDAGToDAGISel::getRC( MVT VT ) {
case MVT::v2i64:
case MVT::v2f64:
return CurDAG->getTargetConstant(SPU::VECREGRegClass.getID(), MVT::i32);
break;
default:
assert( false && "add a new case here" );
return SDValue();
}
return SDValue();
}
//! Convert the operand from a target-independent to a target-specific node

15
llvm/lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -1038,7 +1038,6 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
llvm_unreachable("LowerConstantPool: Relocation model other than static"
" not supported.");
return SDValue();
}
//! Alternate entry point for generating the address of a constant pool entry
@ -1069,7 +1068,6 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
llvm_unreachable("LowerJumpTable: Relocation model other than static"
" not supported.");
return SDValue();
}
static SDValue
@ -1097,8 +1095,6 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
"not supported.");
/*NOTREACHED*/
}
return SDValue();
}
//! Custom lower double precision floating point constants
@ -1696,7 +1692,6 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
SDValue T = DAG.getConstant(Value32, MVT::i32);
return DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T));
break;
}
case MVT::v2f64: {
uint64_t f64val = uint64_t(SplatBits);
@ -1706,7 +1701,6 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
SDValue T = DAG.getConstant(f64val, MVT::i64);
return DAG.getNode(ISD::BITCAST, dl, MVT::v2f64,
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
break;
}
case MVT::v16i8: {
// 8-bit constants have to be expanded to 16-bits
@ -1733,8 +1727,6 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl);
}
}
return SDValue();
}
/*!
@ -2008,8 +2000,6 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0);
}
}
return SDValue();
}
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
@ -2222,8 +2212,6 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc,
switch (Opc) {
default:
llvm_unreachable("Unhandled i8 math operator");
/*NOTREACHED*/
break;
case ISD::ADD: {
// 8-bit addition: Promote the arguments up to 16-bits and truncate
// the result:
@ -2308,11 +2296,8 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc,
N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
DAG.getNode(Opc, dl, MVT::i16, N0, N1));
break;
}
}
return SDValue();
}
//! Lower byte immediate operations for v16i8 vectors:

1
llvm/lib/Target/CppBackend/CPPBackend.cpp
View File

@ -189,7 +189,6 @@ static std::string getTypePrefix(Type *Ty) {
case Type::VectorTyID: return "packed_";
default: return "other_";
}
return "unknown_";
}
void CppWriter::error(const std::string& msg) {

1
llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
View File

@ -223,7 +223,6 @@ void HexagonAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) {
case MachineOperand::MO_Immediate:
dbgs() << "printOp() does not handle immediate values\n";
abort();
return;
case MachineOperand::MO_MachineBasicBlock:
O << *MO.getMBB()->getSymbol();

2
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -571,8 +571,6 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl) {
ReplaceUses(Froms, Tos, 3);
return Result_1;
}
return SelectCode(LD);
}

2
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -113,8 +113,6 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
return false;
}
llvm_unreachable(0);
return true;
}

2
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1375,7 +1375,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
default:
return false;
}
return false;
}
@ -1450,5 +1449,4 @@ isConditionalLoad (const MachineInstr* MI) const {
default:
return false;
}
return false;
}

1
llvm/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
View File

@ -347,7 +347,6 @@ MatchAndEmitInstruction(SMLoc IDLoc,
}
llvm_unreachable("Implement any new match types added!");
return true;
}
MBlazeOperand *MBlazeAsmParser::

2
llvm/lib/Target/MBlaze/MBlazeELFWriterInfo.cpp
View File

@ -41,7 +41,6 @@ unsigned MBlazeELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
default:
llvm_unreachable("unknown mblaze machine relocation type");
}
return 0;
}
long int MBlazeELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
@ -54,7 +53,6 @@ long int MBlazeELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
default:
llvm_unreachable("unknown mblaze relocation type");
}
return 0;
}
unsigned MBlazeELFWriterInfo::getRelocationTySize(unsigned RelTy) const {

2
llvm/lib/Target/MBlaze/MBlazeISelLowering.cpp
View File

@ -602,7 +602,6 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
SDValue MBlazeTargetLowering::
LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
llvm_unreachable("TLS not implemented for MicroBlaze.");
return SDValue(); // Not reached
}
SDValue MBlazeTargetLowering::
@ -1081,7 +1080,6 @@ getConstraintType(const std::string &Constraint) const
case 'y':
case 'f':
return C_RegisterClass;
break;
}
}
return TargetLowering::getConstraintType(Constraint);

2
llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
View File

@ -184,10 +184,8 @@ unsigned MBlazeRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
unsigned MBlazeRegisterInfo::getEHExceptionRegister() const {
llvm_unreachable("What is the exception register");
return 0;
}
unsigned MBlazeRegisterInfo::getEHHandlerRegister() const {
llvm_unreachable("What is the exception handler register");
return 0;
}

4
llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h
View File

@ -96,7 +96,6 @@ static inline bool isSpecialMBlazeRegister(unsigned Reg) {
default:
return false;
}
return false; // Not reached
}
/// getMBlazeRegisterNumbering - Given the enum value for some register, e.g.
@ -161,7 +160,6 @@ static inline unsigned getMBlazeRegisterNumbering(unsigned RegEnum) {
case MBlaze::RPVR11 : return 0x200B;
default: llvm_unreachable("Unknown register number!");
}
return 0; // Not reached
}
/// getRegisterFromNumbering - Given the enum value for some register, e.g.
@ -202,7 +200,6 @@ static inline unsigned getMBlazeRegisterFromNumbering(unsigned Reg) {
case 31 : return MBlaze::R31;
default: llvm_unreachable("Unknown register number!");
}
return 0; // Not reached
}
static inline unsigned getSpecialMBlazeRegisterFromNumbering(unsigned Reg) {
@ -233,7 +230,6 @@ static inline unsigned getSpecialMBlazeRegisterFromNumbering(unsigned Reg) {
case 0x200B : return MBlaze::RPVR11;
default: llvm_unreachable("Unknown register number!");
}
return 0; // Not reached
}
} // end namespace llvm;

13
llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCCodeEmitter.cpp
View File

@ -109,17 +109,14 @@ unsigned MBlazeMCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO) const {
if (MO.isReg())
return getMBlazeRegisterNumbering(MO.getReg());
else if (MO.isImm())
if (MO.isImm())
return static_cast<unsigned>(MO.getImm());
else if (MO.isExpr())
return 0; // The relocation has already been recorded at this point.
else {
if (MO.isExpr())
return 0; // The relocation has already been recorded at this point.
#ifndef NDEBUG
errs() << MO;
errs() << MO;
#endif
llvm_unreachable(0);
}
return 0;
llvm_unreachable(0);
}
void MBlazeMCCodeEmitter::

1
llvm/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.cpp
View File

@ -92,7 +92,6 @@ void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo,
switch (CC) {
default:
llvm_unreachable("Unsupported CC code");
break;
case MSP430CC::COND_E:
O << "eq";
break;

13
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -194,7 +194,6 @@ SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
default:
llvm_unreachable("unimplemented operand");
return SDValue();
}
}
@ -260,12 +259,9 @@ MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
case CallingConv::Fast:
return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
case CallingConv::MSP430_INTR:
if (Ins.empty())
return Chain;
else {
if (Ins.empty())
return Chain;
report_fatal_error("ISRs cannot have arguments");
return SDValue();
}
}
}
@ -290,7 +286,6 @@ MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
Outs, OutVals, Ins, dl, DAG, InVals);
case CallingConv::MSP430_INTR:
report_fatal_error("ISRs cannot be called directly");
return SDValue();
}
}
@ -391,10 +386,8 @@ MSP430TargetLowering::LowerReturn(SDValue Chain,
SmallVector<CCValAssign, 16> RVLocs;
// ISRs cannot return any value.
if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
report_fatal_error("ISRs cannot return any value");
return SDValue();
}
// CCState - Info about the registers and stack slot.
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),

2
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -327,6 +327,4 @@ unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
case MSP430II::Size6Bytes:
return 6;
}
return 6;
}

1
llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
View File

@ -197,7 +197,6 @@ inline static unsigned getMipsRegisterNumbering(unsigned RegEnum)
return 31;
default: llvm_unreachable("Unknown register number!");
}
return 0; // Not reached
}
}

2
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -237,8 +237,6 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
return Ret;
}
llvm_unreachable("Unable to encode MCOperand!");
// Not reached
return 0;
}
/// getMemEncoding - Return binary encoding of memory related operand.

1
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -2826,7 +2826,6 @@ getConstraintType(const std::string &Constraint) const
case 'y':
case 'f':
return C_RegisterClass;
break;
}
}
return TargetLowering::getConstraintType(Constraint);

2
llvm/lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -252,11 +252,9 @@ getFrameRegister(const MachineFunction &MF) const {
unsigned MipsRegisterInfo::
getEHExceptionRegister() const {
llvm_unreachable("What is the exception register");
return 0;
}
unsigned MipsRegisterInfo::
getEHHandlerRegister() const {
llvm_unreachable("What is the exception handler register");
return 0;
}

1
llvm/lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp
View File

@ -215,7 +215,6 @@ void PTXInstPrinter::printRoundingMode(const MCInst *MI, unsigned OpNo,
llvm_unreachable("Unknown rounding mode!");
case PTXRoundingMode::RndDefault:
llvm_unreachable("FP rounding-mode pass did not handle instruction!");
break;
case PTXRoundingMode::RndNone:
// Do not print anything.
break;

4
llvm/lib/Target/PTX/PTXAsmPrinter.cpp
View File

@ -358,11 +358,9 @@ void PTXAsmPrinter::EmitVariableDeclaration(const GlobalVariable *gv) {
void PTXAsmPrinter::EmitFunctionEntryLabel() {
// The function label could have already been emitted if two symbols end up
// conflicting due to asm renaming. Detect this and emit an error.
if (!CurrentFnSym->isUndefined()) {
if (!CurrentFnSym->isUndefined())
report_fatal_error("'" + Twine(CurrentFnSym->getName()) +
"' label emitted multiple times to assembly file");
return;
}
const PTXMachineFunctionInfo *MFI = MF->getInfo<PTXMachineFunctionInfo>();
const PTXParamManager &PM = MFI->getParamManager();

1
llvm/lib/Target/PTX/PTXISelLowering.cpp
View File

@ -211,7 +211,6 @@ SDValue PTXTargetLowering::
switch (CallConv) {
default:
llvm_unreachable("Unsupported calling convention");
break;
case CallingConv::PTX_Kernel:
MFI->setKernel(true);
break;

1
llvm/lib/Target/PTX/PTXRegisterInfo.h
View File

@ -49,7 +49,6 @@ public:
virtual unsigned getFrameRegister(const MachineFunction &MF) const {
llvm_unreachable("PTX does not have a frame register");
return 0;
}
}; // struct PTXRegisterInfo
} // namespace llvm

1
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -602,7 +602,6 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
case ISD::SETULT: return 0;
case ISD::SETUGT: return 1;
}
return 0;
}
SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {

1
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -4569,7 +4569,6 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
}
return SDValue();
}
void PPCTargetLowering::ReplaceNodeResults(SDNode *N,

2
llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -118,10 +118,8 @@ unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
unsigned SparcRegisterInfo::getEHExceptionRegister() const {
llvm_unreachable("What is the exception register");
return 0;
}
unsigned SparcRegisterInfo::getEHHandlerRegister() const {
llvm_unreachable("What is the exception handler register");
return 0;
}

3
llvm/lib/Target/TargetData.cpp
View File

@ -496,9 +496,7 @@ uint64_t TargetData::getTypeSizeInBits(Type *Ty) const {
return cast<VectorType>(Ty)->getBitWidth();
default:
llvm_unreachable("TargetData::getTypeSizeInBits(): Unsupported type");
break;
}
return 0;
}
/*!
@ -553,7 +551,6 @@ unsigned TargetData::getAlignment(Type *Ty, bool abi_or_pref) const {
break;
default:
llvm_unreachable("Bad type for getAlignment!!!");
break;
}
return getAlignmentInfo((AlignTypeEnum)AlignType, getTypeSizeInBits(Ty),

16
llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -72,6 +72,8 @@ bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
*rECX = registers[2];
*rEDX = registers[3];
return false;
#else
return true;
#endif
#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
#if defined(__GNUC__)
@ -98,9 +100,12 @@ bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
mov dword ptr [esi],edx
}
return false;
#else
return true;
#endif
#endif
#else
return true;
#endif
}
/// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
@ -131,7 +136,11 @@ bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
*rECX = registers[2];
*rEDX = registers[3];
return false;
#else
return true;
#endif
#else
return true;
#endif
#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
#if defined(__GNUC__)
@ -160,9 +169,12 @@ bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
mov dword ptr [esi],edx
}
return false;
#else
return true;
#endif
#endif
#else
return true;
#endif
}
void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,

7
llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
View File

@ -44,20 +44,15 @@ unsigned X86WinCOFFObjectWriter::getRelocType(unsigned FixupKind) const {
case X86::reloc_riprel_4byte:
case X86::reloc_riprel_4byte_movq_load:
return Is64Bit ? COFF::IMAGE_REL_AMD64_REL32 : COFF::IMAGE_REL_I386_REL32;
break;
case FK_Data_4:
case X86::reloc_signed_4byte:
return Is64Bit ? COFF::IMAGE_REL_AMD64_ADDR32 : COFF::IMAGE_REL_I386_DIR32;
break;
case FK_Data_8:
if (Is64Bit)
return COFF::IMAGE_REL_AMD64_ADDR64;
else
llvm_unreachable("unsupported relocation type");
break;
llvm_unreachable("unsupported relocation type");
case FK_SecRel_4:
return Is64Bit ? COFF::IMAGE_REL_AMD64_SREL32 : COFF::IMAGE_REL_I386_SECREL;
break;
default:
llvm_unreachable("unsupported relocation type");
}

4
llvm/lib/Target/X86/X86ELFWriterInfo.cpp
View File

@ -60,7 +60,6 @@ unsigned X86ELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
llvm_unreachable("unknown x86 machine relocation type");
}
}
return 0;
}
long int X86ELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
@ -83,7 +82,6 @@ long int X86ELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
llvm_unreachable("unknown x86 relocation type");
}
}
return 0;
}
unsigned X86ELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
@ -107,7 +105,6 @@ unsigned X86ELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
llvm_unreachable("unknown x86 relocation type");
}
}
return 0;
}
bool X86ELFWriterInfo::isPCRelativeRel(unsigned RelTy) const {
@ -132,7 +129,6 @@ bool X86ELFWriterInfo::isPCRelativeRel(unsigned RelTy) const {
llvm_unreachable("unknown x86 relocation type");
}
}
return 0;
}
unsigned X86ELFWriterInfo::getAbsoluteLabelMachineRelTy() const {

32
llvm/lib/Target/X86/X86FrameLowering.cpp
View File

@ -1305,28 +1305,22 @@ HasNestArgument(const MachineFunction *MF) {
/// the first register, false for the second.
static unsigned
GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
if (Is64Bit) {
if (Is64Bit)
return Primary ? X86::R11 : X86::R12;
} else {
CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
bool IsNested = HasNestArgument(&MF);
if (CallingConvention == CallingConv::X86_FastCall ||
CallingConvention == CallingConv::Fast) {
if (IsNested) {
report_fatal_error("Segmented stacks does not support fastcall with "
"nested function.");
return -1;
} else {
return Primary ? X86::EAX : X86::ECX;
}
} else {
if (IsNested)
return Primary ? X86::EDX : X86::EAX;
else
return Primary ? X86::ECX : X86::EAX;
}
CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
bool IsNested = HasNestArgument(&MF);
if (CallingConvention == CallingConv::X86_FastCall ||
CallingConvention == CallingConv::Fast) {
if (IsNested)
report_fatal_error("Segmented stacks does not support fastcall with "
"nested function.");
return Primary ? X86::EAX : X86::ECX;
}
if (IsNested)
return Primary ? X86::EDX : X86::EAX;
return Primary ? X86::ECX : X86::EAX;
}
// The stack limit in the TCB is set to this many bytes above the actual stack

1
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -1968,7 +1968,6 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
getI8Imm(ShlVal));
break;
}
case X86ISD::UMUL: {
SDValue N0 = Node->getOperand(0);

14
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -2909,7 +2909,6 @@ static bool isTargetShuffle(unsigned Opcode) {
case X86ISD::VPERM2X128:
return true;
}
return false;
}
static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
@ -2921,8 +2920,6 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
case X86ISD::MOVDDUP:
return DAG.getNode(Opc, dl, VT, V1);
}
return SDValue();
}
static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
@ -2935,8 +2932,6 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
case X86ISD::VPERMILP:
return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
}
return SDValue();
}
static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
@ -2949,7 +2944,6 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
return DAG.getNode(Opc, dl, VT, V1, V2,
DAG.getConstant(TargetMask, MVT::i8));
}
return SDValue();
}
static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
@ -2967,7 +2961,6 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
case X86ISD::UNPCKH:
return DAG.getNode(Opc, dl, VT, V1, V2);
}
return SDValue();
}
SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
@ -7439,11 +7432,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
Chain.getValue(1));
}
assert(false &&
"TLS not implemented for this target.");
llvm_unreachable("Unreachable");
return SDValue();
llvm_unreachable("TLS not implemented for this target.");
}
@ -13501,7 +13490,6 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
switch (N->getOpcode()) {
default:
llvm_unreachable("Unknown shift opcode!");
break;
case ISD::SHL:
if (VT == MVT::v2i64)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,

7
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -1164,7 +1164,6 @@ X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
switch (MI.getOpcode()) {
default:
llvm_unreachable(0);
break;
case X86::MOVSX16rr8:
case X86::MOVZX16rr8:
case X86::MOVSX32rr8:
@ -1207,7 +1206,8 @@ bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
static bool isFrameLoadOpcode(int Opcode) {
switch (Opcode) {
default: break;
default:
return false;
case X86::MOV8rm:
case X86::MOV16rm:
case X86::MOV32rm:
@ -1229,9 +1229,7 @@ static bool isFrameLoadOpcode(int Opcode) {
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
return true;
break;
}
return false;
}
static bool isFrameStoreOpcode(int Opcode) {
@ -1575,7 +1573,6 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
switch (MIOpc) {
default:
llvm_unreachable(0);
break;
case X86::SHL16ri: {
unsigned ShAmt = MI->getOperand(2).getImm();
MIB.addReg(0).addImm(1 << ShAmt)

1
llvm/lib/Target/X86/X86JITInfo.cpp
View File

@ -571,6 +571,5 @@ char* X86JITInfo::allocateThreadLocalMemory(size_t size) {
return TLSOffset;
#else
llvm_unreachable("Cannot allocate thread local storage on this arch!");
return 0;
#endif
}

4
llvm/lib/Target/X86/X86RegisterInfo.cpp
View File

@ -526,12 +526,10 @@ unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
unsigned X86RegisterInfo::getEHExceptionRegister() const {
llvm_unreachable("What is the exception register");
return 0;
}
unsigned X86RegisterInfo::getEHHandlerRegister() const {
llvm_unreachable("What is the exception handler register");
return 0;
}
namespace llvm {
@ -713,8 +711,6 @@ unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
return X86::R15;
}
}
return Reg;
}
}

9
llvm/lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -187,7 +187,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
default:
llvm_unreachable("unimplemented operand");
return SDValue();
}
}
@ -199,7 +198,6 @@ void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
switch (N->getOpcode()) {
default:
llvm_unreachable("Don't know how to custom expand this!");
return;
case ISD::ADD:
case ISD::SUB:
Results.push_back(ExpandADDSUB(N, DAG));
@ -275,9 +273,8 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
}
if (! GVar) {
if (!GVar) {
llvm_unreachable("Thread local object not a GlobalVariable?");
return SDValue();
}
Type *Ty = cast<PointerType>(GV->getType())->getElementType();
if (!Ty->isSized() || isZeroLengthArray(Ty)) {
@ -757,7 +754,7 @@ SDValue XCoreTargetLowering::
LowerVAARG(SDValue Op, SelectionDAG &DAG) const
{
llvm_unreachable("unimplemented");
// FIX Arguments passed by reference need a extra dereference.
// FIXME Arguments passed by reference need a extra dereference.
SDNode *Node = Op.getNode();
DebugLoc dl = Node->getDebugLoc();
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
@ -1602,8 +1599,6 @@ XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
// reg + reg<<2
return AM.Scale == 4 && AM.BaseOffs == 0;
}
return false;
}
//===----------------------------------------------------------------------===//

1
llvm/lib/Transforms/IPO/GlobalOpt.cpp
View File

@ -1210,7 +1210,6 @@ static Value *GetHeapSROAValue(Value *V, unsigned FieldNo,
PHIsToRewrite.push_back(std::make_pair(PN, FieldNo));
} else {
llvm_unreachable("Unknown usable value");
Result = 0;
}
return FieldVals[FieldNo] = Result;

2
llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
View File

@ -87,7 +87,6 @@ static unsigned getFCmpCode(FCmpInst::Predicate CC, bool &isOrdered) {
default:
// Not expecting FCMP_FALSE and FCMP_TRUE;
llvm_unreachable("Unexpected FCmp predicate!");
return 0;
}
}
@ -1555,7 +1554,6 @@ Value *InstCombiner::FoldOrOfICmps(ICmpInst *LHS, ICmpInst *RHS) {
case ICmpInst::ICMP_SLT: // (X != 13 | X s< 15) -> true
return ConstantInt::getTrue(LHS->getContext());
}
break;
case ICmpInst::ICMP_ULT:
switch (RHSCC) {
default: llvm_unreachable("Unknown integer condition code!");

1
llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
View File

@ -215,7 +215,6 @@ Value *InstCombiner::EvaluateInDifferentType(Value *V, Type *Ty,
default:
// TODO: Can handle more cases here.
llvm_unreachable("Unreachable!");
break;
}
Res->takeName(I);

1
llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
View File

@ -184,7 +184,6 @@ Instruction *InstCombiner::FoldSelectOpOp(SelectInst &SI, Instruction *TI,
return BinaryOperator::Create(BO->getOpcode(), NewSI, MatchOp);
}
llvm_unreachable("Shouldn't get here");
return 0;
}
static bool isSelect01(Constant *C1, Constant *C2) {

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