forked from OSchip/llvm-project
[X86][SSE] Add bool vector extraction test cases from PR15215
llvm-svn: 314813
This commit is contained in:
Simon Pilgrim
parent
491b6b5490
commit
46a804cfd9
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32 --check-prefix=X32-SSE2
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX2
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define i32 @PR15215_bad(<4 x i32> %input) {
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; X32-SSE2-LABEL: PR15215_bad:
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; X32-SSE2: # BB#0: # %entry
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; X32-SSE2-NEXT: pslld $31, %xmm0
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; X32-SSE2-NEXT: psrad $31, %xmm0
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; X32-SSE2-NEXT: movmskps %xmm0, %eax
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; X32-SSE2-NEXT: retl
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;
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; X32-AVX2-LABEL: PR15215_bad:
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; X32-AVX2: # BB#0: # %entry
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; X32-AVX2-NEXT: vpslld $31, %xmm0, %xmm0
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; X32-AVX2-NEXT: vpsrad $31, %xmm0, %xmm0
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; X32-AVX2-NEXT: vmovmskps %xmm0, %eax
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; X32-AVX2-NEXT: retl
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;
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; X64-SSE2-LABEL: PR15215_bad:
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; X64-SSE2: # BB#0: # %entry
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; X64-SSE2-NEXT: pslld $31, %xmm0
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; X64-SSE2-NEXT: psrad $31, %xmm0
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; X64-SSE2-NEXT: movmskps %xmm0, %eax
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; X64-SSE2-NEXT: retq
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;
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; X64-AVX2-LABEL: PR15215_bad:
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; X64-AVX2: # BB#0: # %entry
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; X64-AVX2-NEXT: vpslld $31, %xmm0, %xmm0
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; X64-AVX2-NEXT: vpsrad $31, %xmm0, %xmm0
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; X64-AVX2-NEXT: vmovmskps %xmm0, %eax
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; X64-AVX2-NEXT: retq
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entry:
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%0 = trunc <4 x i32> %input to <4 x i1>
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%1 = bitcast <4 x i1> %0 to i4
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%2 = zext i4 %1 to i32
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ret i32 %2
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}
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define i32 @PR15215_good(<4 x i32> %input) {
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; X32-SSE2-LABEL: PR15215_good:
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; X32-SSE2: # BB#0: # %entry
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; X32-SSE2-NEXT: pushl %esi
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; X32-SSE2-NEXT: .Lcfi0:
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; X32-SSE2-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE2-NEXT: .Lcfi1:
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; X32-SSE2-NEXT: .cfi_offset %esi, -8
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; X32-SSE2-NEXT: movd %xmm0, %eax
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; X32-SSE2-NEXT: andl $1, %eax
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
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; X32-SSE2-NEXT: movd %xmm1, %ecx
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; X32-SSE2-NEXT: andl $1, %ecx
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
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; X32-SSE2-NEXT: movd %xmm1, %edx
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; X32-SSE2-NEXT: andl $1, %edx
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; X32-SSE2-NEXT: movd %xmm0, %esi
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; X32-SSE2-NEXT: andl $1, %esi
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; X32-SSE2-NEXT: leal (%eax,%ecx,2), %eax
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; X32-SSE2-NEXT: leal (%eax,%edx,4), %eax
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; X32-SSE2-NEXT: leal (%eax,%esi,8), %eax
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; X32-SSE2-NEXT: popl %esi
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; X32-SSE2-NEXT: retl
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;
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; X32-AVX2-LABEL: PR15215_good:
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; X32-AVX2: # BB#0: # %entry
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; X32-AVX2-NEXT: pushl %esi
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; X32-AVX2-NEXT: .Lcfi0:
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; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
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; X32-AVX2-NEXT: .Lcfi1:
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; X32-AVX2-NEXT: .cfi_offset %esi, -8
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; X32-AVX2-NEXT: vmovd %xmm0, %eax
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; X32-AVX2-NEXT: andl $1, %eax
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; X32-AVX2-NEXT: vpextrd $1, %xmm0, %ecx
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; X32-AVX2-NEXT: andl $1, %ecx
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; X32-AVX2-NEXT: vpextrd $2, %xmm0, %edx
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; X32-AVX2-NEXT: andl $1, %edx
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; X32-AVX2-NEXT: vpextrd $3, %xmm0, %esi
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; X32-AVX2-NEXT: andl $1, %esi
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; X32-AVX2-NEXT: leal (%eax,%ecx,2), %eax
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; X32-AVX2-NEXT: leal (%eax,%edx,4), %eax
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; X32-AVX2-NEXT: leal (%eax,%esi,8), %eax
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; X32-AVX2-NEXT: popl %esi
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; X32-AVX2-NEXT: retl
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;
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; X64-SSE2-LABEL: PR15215_good:
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; X64-SSE2: # BB#0: # %entry
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; X64-SSE2-NEXT: movd %xmm0, %eax
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; X64-SSE2-NEXT: andl $1, %eax
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; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
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; X64-SSE2-NEXT: movd %xmm1, %ecx
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; X64-SSE2-NEXT: andl $1, %ecx
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; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
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; X64-SSE2-NEXT: movd %xmm1, %edx
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; X64-SSE2-NEXT: andl $1, %edx
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; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; X64-SSE2-NEXT: movd %xmm0, %esi
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; X64-SSE2-NEXT: andl $1, %esi
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; X64-SSE2-NEXT: leal (%rax,%rcx,2), %eax
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; X64-SSE2-NEXT: leal (%rax,%rdx,4), %eax
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; X64-SSE2-NEXT: leal (%rax,%rsi,8), %eax
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; X64-SSE2-NEXT: retq
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;
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; X64-AVX2-LABEL: PR15215_good:
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; X64-AVX2: # BB#0: # %entry
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; X64-AVX2-NEXT: vmovd %xmm0, %eax
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; X64-AVX2-NEXT: andl $1, %eax
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; X64-AVX2-NEXT: vpextrd $1, %xmm0, %ecx
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; X64-AVX2-NEXT: andl $1, %ecx
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; X64-AVX2-NEXT: vpextrd $2, %xmm0, %edx
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; X64-AVX2-NEXT: andl $1, %edx
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; X64-AVX2-NEXT: vpextrd $3, %xmm0, %esi
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; X64-AVX2-NEXT: andl $1, %esi
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; X64-AVX2-NEXT: leal (%rax,%rcx,2), %eax
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; X64-AVX2-NEXT: leal (%rax,%rdx,4), %eax
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; X64-AVX2-NEXT: leal (%rax,%rsi,8), %eax
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; X64-AVX2-NEXT: retq
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entry:
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%0 = trunc <4 x i32> %input to <4 x i1>
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%1 = extractelement <4 x i1> %0, i32 0
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%e1 = select i1 %1, i32 1, i32 0
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%2 = extractelement <4 x i1> %0, i32 1
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%e2 = select i1 %2, i32 2, i32 0
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%3 = extractelement <4 x i1> %0, i32 2
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%e3 = select i1 %3, i32 4, i32 0
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%4 = extractelement <4 x i1> %0, i32 3
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%e4 = select i1 %4, i32 8, i32 0
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%5 = or i32 %e1, %e2
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%6 = or i32 %5, %e3
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%7 = or i32 %6, %e4
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ret i32 %7
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}
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