maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[AArch64]Fix the problem that AArch64 backend fails to select scalar_to_vector of vector types having more than one element. 

llvm-svn: 197135
This commit is contained in:
Hao Liu 2013-12-12 07:36:26 +00:00
parent 5a10da129f
commit 46a10eec28
2 changed files with 87 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
llvm/lib/Target/AArch64/AArch64InstrNEON.td
View File

@ -6707,14 +6707,48 @@ def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
(FMOVdx $src)>;
def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
(v8i8 (EXTRACT_SUBREG (v16i8
(INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
sub_64))>;
def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
(v4i16 (EXTRACT_SUBREG (v8i16
(INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
sub_64))>;
def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
(v2i32 (EXTRACT_SUBREG (v16i8
(INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
sub_64))>;
def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
(INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))>;
def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
(INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))>;
def : Pat<(v4i32 (scalar_to_vector GPR32:$Rn)),
(INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))>;
def : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)),
(INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>;
def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
(v2i32 (EXTRACT_SUBREG (v16i8
(INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
sub_64))>;
def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
(v2i32 (EXTRACT_SUBREG (v16i8
(INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
sub_64))>;
def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
(v1f32 FPR32:$Rn)>;
def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
(v1f64 FPR64:$Rn)>;
def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
(FMOVdd $src)>;
def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
(f64 FPR64:$src), sub_64)>;

50
llvm/test/CodeGen/AArch64/neon-copy.ll
View File

@ -612,4 +612,54 @@ define <1 x double> @test_bitcasti64tov1f64(i64 %in) {
%res = bitcast i64 %in to <1 x double>
; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
ret <1 x double> %res
}
; Test insert element into an undef vector
define <8 x i8> @scalar_to_vector.v8i8(i8 %a) {
; CHECK-LABEL: scalar_to_vector.v8i8:
; CHECK: ins {{v[0-9]+}}.b[0], {{w[0-9]+}}
%b = insertelement <8 x i8> undef, i8 %a, i32 0
ret <8 x i8> %b
}
define <16 x i8> @scalar_to_vector.v16i8(i8 %a) {
; CHECK-LABEL: scalar_to_vector.v16i8:
; CHECK: ins {{v[0-9]+}}.b[0], {{w[0-9]+}}
%b = insertelement <16 x i8> undef, i8 %a, i32 0
ret <16 x i8> %b
}
define <4 x i16> @scalar_to_vector.v4i16(i16 %a) {
; CHECK-LABEL: scalar_to_vector.v4i16:
; CHECK: ins {{v[0-9]+}}.h[0], {{w[0-9]+}}
%b = insertelement <4 x i16> undef, i16 %a, i32 0
ret <4 x i16> %b
}
define <8 x i16> @scalar_to_vector.v8i16(i16 %a) {
; CHECK-LABEL: scalar_to_vector.v8i16:
; CHECK: ins {{v[0-9]+}}.h[0], {{w[0-9]+}}
%b = insertelement <8 x i16> undef, i16 %a, i32 0
ret <8 x i16> %b
}
define <2 x i32> @scalar_to_vector.v2i32(i32 %a) {
; CHECK-LABEL: scalar_to_vector.v2i32:
; CHECK: ins {{v[0-9]+}}.s[0], {{w[0-9]+}}
%b = insertelement <2 x i32> undef, i32 %a, i32 0
ret <2 x i32> %b
}
define <4 x i32> @scalar_to_vector.v4i32(i32 %a) {
; CHECK-LABEL: scalar_to_vector.v4i32:
; CHECK: ins {{v[0-9]+}}.s[0], {{w[0-9]+}}
%b = insertelement <4 x i32> undef, i32 %a, i32 0
ret <4 x i32> %b
}
define <2 x i64> @scalar_to_vector.v2i64(i64 %a) {
; CHECK-LABEL: scalar_to_vector.v2i64:
; CHECK: ins {{v[0-9]+}}.d[0], {{x[0-9]+}}
%b = insertelement <2 x i64> undef, i64 %a, i32 0
ret <2 x i64> %b
}