forked from OSchip/llvm-project
[Hexagon] Add a member Subtarget to HexagonInstrInfo, NFC
llvm-svn: 314920
This commit is contained in:
Krzysztof Parzyszek
parent
2a6c9adb2f
commit
4697ddeea4
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@ -116,7 +116,8 @@ const int Hexagon_ADDI_OFFSET_MIN = -32768;
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void HexagonInstrInfo::anchor() {}
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HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
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: HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP) {}
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: HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
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Subtarget(ST) {}
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static bool isIntRegForSubInst(unsigned Reg) {
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return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
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@ -698,7 +699,7 @@ unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB,
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unsigned NewLoopCount = createVR(MF, MVT::i32);
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MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
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addReg(LoopCount).addImm(-1);
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const auto &HRI = *MF->getSubtarget<HexagonSubtarget>().getRegisterInfo();
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const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
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// Update the previously generated instructions with the new loop counter.
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for (SmallVectorImpl<MachineInstr *>::iterator I = PrevInsts.begin(),
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E = PrevInsts.end(); I != E; ++I)
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@ -741,8 +742,7 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DestReg,
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unsigned SrcReg, bool KillSrc) const {
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MachineFunction &MF = *MBB.getParent();
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auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
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unsigned KillFlag = getKillRegState(KillSrc);
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if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
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@ -846,8 +846,7 @@ void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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unsigned RegAlign = TRI->getSpillAlignment(*RC);
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unsigned KillFlag = getKillRegState(isKill);
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bool HasAlloca = MFI.hasVarSizedObjects();
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const auto &HST = MF.getSubtarget<HexagonSubtarget>();
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const HexagonFrameLowering &HFI = *HST.getFrameLowering();
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const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
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@ -912,8 +911,7 @@ void HexagonInstrInfo::loadRegFromStackSlot(
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unsigned SlotAlign = MFI.getObjectAlignment(FI);
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unsigned RegAlign = TRI->getSpillAlignment(*RC);
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bool HasAlloca = MFI.hasVarSizedObjects();
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const auto &HST = MF.getSubtarget<HexagonSubtarget>();
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const HexagonFrameLowering &HFI = *HST.getFrameLowering();
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const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
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@ -979,7 +977,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Opc = MI.getOpcode();
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@ -1374,8 +1372,7 @@ bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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bool HexagonInstrInfo::DefinesPredicate(MachineInstr &MI,
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std::vector<MachineOperand> &Pred) const {
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MachineFunction &MF = *MI.getParent()->getParent();
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const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
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for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
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MachineOperand MO = MI.getOperand(oper);
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@ -1405,8 +1402,7 @@ bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
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return false;
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if (MI.isCall() || isTailCall(MI)) {
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const MachineFunction &MF = *MI.getParent()->getParent();
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if (!MF.getSubtarget<HexagonSubtarget>().usePredicatedCalls())
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if (!Subtarget.usePredicatedCalls())
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return false;
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}
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return true;
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@ -1484,10 +1480,8 @@ unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
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ScheduleHazardRecognizer*
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HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
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const InstrItineraryData *II, const ScheduleDAG *DAG) const {
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if (UseDFAHazardRec) {
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auto &HST = DAG->MF.getSubtarget<HexagonSubtarget>();
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return new HexagonHazardRecognizer(II, this, HST);
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}
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if (UseDFAHazardRec)
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return new HexagonHazardRecognizer(II, this, Subtarget);
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return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
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}
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@ -1730,23 +1724,11 @@ bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
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}
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bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
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const MachineFunction *MF = MI.getParent()->getParent();
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const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
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const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
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if (!(isTC1(MI))
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&& !(QII->isTC2Early(MI))
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&& !(MI.getDesc().mayLoad())
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&& !(MI.getDesc().mayStore())
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&& (MI.getDesc().getOpcode() != Hexagon::S2_allocframe)
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&& (MI.getDesc().getOpcode() != Hexagon::L2_deallocframe)
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&& !(QII->isMemOp(MI))
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&& !(MI.isBranch())
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&& !(MI.isReturn())
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&& !MI.isCall())
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return true;
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return false;
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return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
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!MI.getDesc().mayStore() &&
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MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
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MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
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!isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
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}
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// Return true if the instruction is a compund branch instruction.
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@ -1818,8 +1800,7 @@ bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
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const MachineInstr &ConsMI) const {
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if (!ProdMI.getDesc().getNumDefs())
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return false;
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const MachineFunction &MF = *ProdMI.getParent()->getParent();
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const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
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SmallVector<unsigned, 4> DefsA;
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SmallVector<unsigned, 4> DefsB;
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@ -2762,10 +2743,9 @@ bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
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// Returns true, if a LD insn can be promoted to a cur load.
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bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
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auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>();
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const uint64_t F = MI.getDesc().TSFlags;
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return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
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HST.hasV60TOps();
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Subtarget.hasV60TOps();
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}
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// Returns true, if a ST insn can be promoted to a new-value store.
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@ -3378,15 +3358,13 @@ int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
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}
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int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
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const MachineFunction &MF = *MI.getParent()->getParent();
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const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
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int NewOp = MI.getOpcode();
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if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
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NewOp = Hexagon::getPredOldOpcode(NewOp);
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// All Hexagon architectures have prediction bits on dot-new branches,
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// but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
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// to pick the right opcode when converting back to dot-old.
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if (!HST.getFeatureBits()[Hexagon::ArchV60]) {
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if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
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switch (NewOp) {
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case Hexagon::J2_jumptpt:
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NewOp = Hexagon::J2_jumpt;
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@ -3411,7 +3389,7 @@ int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
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assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
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}
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if (HST.hasV60TOps())
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if (Subtarget.hasV60TOps())
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return NewOp;
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// Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
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@ -3433,8 +3411,7 @@ int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
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HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
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const MachineInstr &MI) const {
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unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
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const MachineFunction &MF = *MI.getParent()->getParent();
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const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
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switch (MI.getOpcode()) {
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default:
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@ -3802,8 +3779,7 @@ int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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unsigned DefIdx,
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const MachineInstr &UseMI,
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unsigned UseIdx) const {
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const MachineFunction &MF = *DefMI.getParent()->getParent();
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const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
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// Get DefIdx and UseIdx for super registers.
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MachineOperand DefMO = DefMI.getOperand(DefIdx);
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@ -3880,10 +3856,8 @@ unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
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if (Size != 0)
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return Size;
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const MachineFunction &MF = *MI.getParent()->getParent();
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const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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// Handle vector access sizes.
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const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
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switch (S) {
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case HexagonII::HVXVectorAccess:
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return HRI.getSpillSize(Hexagon::HvxVRRegClass);
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@ -4003,8 +3977,7 @@ uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
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}
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unsigned HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
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const TargetSubtargetInfo &ST = MI.getParent()->getParent()->getSubtarget();
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const InstrItineraryData &II = *ST.getInstrItineraryData();
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const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
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const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
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return IS.getUnits();
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@ -37,6 +37,7 @@ class MachineOperand;
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class TargetRegisterInfo;
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class HexagonInstrInfo : public HexagonGenInstrInfo {
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const HexagonSubtarget &Subtarget;
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virtual void anchor();
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public:
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