[globalisel][regbank] Warn about MIR ambiguities when register bank/class names clash.

llvm-svn: 317132

llvm/include/llvm/TableGen/Error.h

@@ -19,6 +19,8 @@
 
 namespace llvm {
 
+void PrintNote(ArrayRef<SMLoc> NoteLoc, const Twine &Msg);
+
 void PrintWarning(ArrayRef<SMLoc> WarningLoc, const Twine &Msg);
 void PrintWarning(const char *Loc, const Twine &Msg);
 void PrintWarning(const Twine &Msg);

llvm/lib/TableGen/Error.cpp

@@ -39,6 +39,10 @@ static void PrintMessage(ArrayRef<SMLoc> Loc, SourceMgr::DiagKind Kind,
                         "instantiated from multiclass");
 }
 
+void PrintNote(ArrayRef<SMLoc> NoteLoc, const Twine &Msg) {
+  PrintMessage(NoteLoc, SourceMgr::DK_Note, Msg);
+}
+
 void PrintWarning(ArrayRef<SMLoc> WarningLoc, const Twine &Msg) {
   PrintMessage(WarningLoc, SourceMgr::DK_Warning, Msg);
 }

llvm/utils/TableGen/RegisterBankEmitter.cpp

@@ -299,6 +299,19 @@ void RegisterBankEmitter::run(raw_ostream &OS) {
     Banks.push_back(Bank);
   }
 
+  // Warn about ambiguous MIR caused by register bank/class name clashes.
+  for (const auto &Class : Records.getAllDerivedDefinitions("RegisterClass")) {
+    for (const auto &Bank : Banks) {
+      if (Bank.getName().lower() == Class->getName().lower()) {
+        PrintWarning(Bank.getDef().getLoc(), "Register bank names should be "
+                                             "distinct from register classes "
+                                             "to avoid ambiguous MIR");
+        PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here");
+        PrintNote(Class->getLoc(), "RegisterClass was declared here");
+      }
+    }
+  }
+
   emitSourceFileHeader("Register Bank Source Fragments", OS);
   OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
      << "#undef GET_REGBANK_DECLARATIONS\n";