From 46632d89bb8e15aa97ef6d1b769e0dc265fbbd53 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Tue, 12 May 2009 22:30:18 +0000 Subject: [PATCH] correct register class for tADDspi to GPR since the register will always be SP llvm-svn: 71602 --- llvm/lib/Target/ARM/ARMInstrThumb.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 914be0390b4b..ffb83a8b4d36 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -307,7 +307,7 @@ def tADDrPCi : TI<(outs tGPR:$dst), (ins i32imm:$rhs), def tADDrSPi : TI<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), "add $dst, $sp, $rhs * 4 @ addrspi", []>; -def tADDspi : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), +def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), "add $dst, $rhs * 4", []>; def tAND : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),