forked from OSchip/llvm-project
AMDGPU: Convert AMDGPUResourceUsageAnalysis to a Module pass
This is more precise in the face of indirect calls and aliases, still assuming the call target is defined somewhere in the current module. This sometimes changes the order the functions are printed, and also changes the point where context errors are printed relative to stdout. This also likely has negative consequences for compile time and memory usage.
This commit is contained in:
Matt Arsenault
parent
935abab65c
commit
4622afa94c
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@ -25,7 +25,6 @@
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#include "AMDGPUResourceUsageAnalysis.h"
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#include "AMDGPU.h"
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#include "AMDGPUTargetMachine.h"
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#include "GCNSubtarget.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/Analysis/CallGraph.h"
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@ -98,34 +97,39 @@ int32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs(
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return getTotalNumVGPRs(ST, NumAGPR, NumVGPR);
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}
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bool AMDGPUResourceUsageAnalysis::runOnSCC(CallGraphSCC &SCC) {
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bool AMDGPUResourceUsageAnalysis::runOnModule(Module &M) {
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auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
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if (!TPC)
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return false;
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TM = static_cast<const GCNTargetMachine *>(&TPC->getTM<TargetMachine>());
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MachineModuleInfo &MMI = getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
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const TargetMachine &TM = TPC->getTM<TargetMachine>();
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bool HasIndirectCall = false;
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for (CallGraphNode *I : SCC) {
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Function *F = I->getFunction();
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if (!F || F->isDeclaration())
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for (Function &F : M) {
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if (F.isDeclaration())
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continue;
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MachineModuleInfo &MMI =
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getAnalysis<MachineModuleInfoWrapperPass>().getMMI();
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MachineFunction &MF = MMI.getOrCreateMachineFunction(*F);
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MachineFunction *MF = MMI.getMachineFunction(F);
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assert(MF && "function must have been generated already");
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auto CI = CallGraphResourceInfo.insert(
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std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
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std::make_pair(&F, SIFunctionResourceInfo()));
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SIFunctionResourceInfo &Info = CI.first->second;
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assert(CI.second && "should only be called once per function");
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Info = analyzeResourceUsage(MF);
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Info = analyzeResourceUsage(*MF, TM);
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HasIndirectCall |= Info.HasIndirectCall;
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}
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if (HasIndirectCall)
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propagateIndirectCallRegisterUsage();
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return false;
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}
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AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo
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AMDGPUResourceUsageAnalysis::analyzeResourceUsage(const MachineFunction &MF) {
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AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
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const MachineFunction &MF, const TargetMachine &TM) const {
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SIFunctionResourceInfo Info;
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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@ -471,16 +475,9 @@ AMDGPUResourceUsageAnalysis::analyzeResourceUsage(const MachineFunction &MF) {
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std::max(CalleeFrameSize,
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static_cast<uint64_t>(AssumedStackSizeForExternalCall));
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const SIFunctionResourceInfo &WorstCase =
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getWorstCaseResourceInfo(*MF.getFunction().getParent());
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MaxSGPR = std::max(WorstCase.NumExplicitSGPR - 1, MaxSGPR);
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MaxVGPR = std::max(WorstCase.NumVGPR - 1, MaxVGPR);
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MaxAGPR = std::max(WorstCase.NumAGPR - 1, MaxAGPR);
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// Register usage of indirect calls gets handled later
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Info.UsesVCC = true;
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Info.UsesFlatScratch |=
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WorstCase.UsesFlatScratch && ST.hasFlatAddressSpace();
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Info.UsesFlatScratch = ST.hasFlatAddressSpace();
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Info.HasDynamicallySizedStack = true;
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Info.HasIndirectCall = true;
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} else {
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@ -509,49 +506,31 @@ AMDGPUResourceUsageAnalysis::analyzeResourceUsage(const MachineFunction &MF) {
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return Info;
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}
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const AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo &
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AMDGPUResourceUsageAnalysis::getWorstCaseResourceInfo(const Module &M) {
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if (ModuleWorstCaseInfo)
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return *ModuleWorstCaseInfo;
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void AMDGPUResourceUsageAnalysis::propagateIndirectCallRegisterUsage() {
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// Collect the maximum number of registers from non-hardware-entrypoints.
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// All these functions are potential targets for indirect calls.
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int32_t NonKernelMaxSGPRs = 0;
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int32_t NonKernelMaxVGPRs = 0;
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int32_t NonKernelMaxAGPRs = 0;
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computeWorstCaseModuleRegisterUsage(M);
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return *ModuleWorstCaseInfo;
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}
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/// Find the worst case register usage for all callable functions in the module,
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/// assuming all reachable functions are defined in the current module.
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void AMDGPUResourceUsageAnalysis::computeWorstCaseModuleRegisterUsage(
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const Module &M) {
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assert(!ModuleWorstCaseInfo);
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ModuleWorstCaseInfo = SIFunctionResourceInfo();
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ModuleWorstCaseInfo->UsesVCC = true;
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ModuleWorstCaseInfo->HasDynamicallySizedStack = true;
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ModuleWorstCaseInfo->HasRecursion = true;
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ModuleWorstCaseInfo->HasIndirectCall = true;
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for (const Function &F : M) {
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if (F.isIntrinsic())
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continue;
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if (AMDGPU::isEntryFunctionCC(F.getCallingConv()))
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continue;
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const GCNSubtarget &ST = TM->getSubtarget<GCNSubtarget>(F);
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const int32_t MaxVGPR = ST.getMaxNumVGPRs(F);
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const int32_t MaxSGPR = ST.getMaxNumSGPRs(F);
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ModuleWorstCaseInfo->NumVGPR =
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std::max(ModuleWorstCaseInfo->NumVGPR, MaxVGPR);
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if (ST.hasMAIInsts()) {
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const int32_t MaxAGPR = ST.getMaxNumAGPRs(F);
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ModuleWorstCaseInfo->NumAGPR =
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std::max(ModuleWorstCaseInfo->NumAGPR, MaxAGPR);
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for (const auto &I : CallGraphResourceInfo) {
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if (!AMDGPU::isEntryFunctionCC(I.getFirst()->getCallingConv())) {
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auto &Info = I.getSecond();
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NonKernelMaxSGPRs = std::max(NonKernelMaxSGPRs, Info.NumExplicitSGPR);
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NonKernelMaxVGPRs = std::max(NonKernelMaxVGPRs, Info.NumVGPR);
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NonKernelMaxAGPRs = std::max(NonKernelMaxAGPRs, Info.NumAGPR);
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}
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}
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ModuleWorstCaseInfo->NumExplicitSGPR =
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std::max(ModuleWorstCaseInfo->NumExplicitSGPR, MaxSGPR);
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ModuleWorstCaseInfo->UsesFlatScratch |= ST.hasFlatAddressSpace();
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// Add register usage for functions with indirect calls.
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// For calls to unknown functions, we assume the maximum register usage of
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// all non-hardware-entrypoints in the current module.
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for (auto &I : CallGraphResourceInfo) {
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auto &Info = I.getSecond();
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if (Info.HasIndirectCall) {
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Info.NumExplicitSGPR = std::max(Info.NumExplicitSGPR, NonKernelMaxSGPRs);
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Info.NumVGPR = std::max(Info.NumVGPR, NonKernelMaxVGPRs);
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Info.NumAGPR = std::max(Info.NumAGPR, NonKernelMaxAGPRs);
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}
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}
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}
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@ -20,12 +20,11 @@
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namespace llvm {
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class GCNTargetMachine;
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class GCNSubtarget;
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class MachineFunction;
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class TargetMachine;
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struct AMDGPUResourceUsageAnalysis : public CallGraphSCCPass {
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struct AMDGPUResourceUsageAnalysis : public ModulePass {
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static char ID;
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public:
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@ -51,15 +50,15 @@ public:
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int32_t getTotalNumVGPRs(const GCNSubtarget &ST) const;
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};
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AMDGPUResourceUsageAnalysis() : CallGraphSCCPass(ID) {}
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AMDGPUResourceUsageAnalysis() : ModulePass(ID) {}
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bool runOnSCC(CallGraphSCC &SCC) override;
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bool doInitialization(CallGraph &CG) override {
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bool doInitialization(Module &M) override {
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CallGraphResourceInfo.clear();
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return CallGraphSCCPass::doInitialization(CG);
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return ModulePass::doInitialization(M);
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}
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bool runOnModule(Module &M) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineModuleInfoWrapperPass>();
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AU.setPreservesAll();
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@ -72,16 +71,12 @@ public:
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return Info->getSecond();
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}
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const SIFunctionResourceInfo &getWorstCaseResourceInfo(const Module &M);
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private:
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void computeWorstCaseModuleRegisterUsage(const Module &M);
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SIFunctionResourceInfo analyzeResourceUsage(const MachineFunction &MF,
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const TargetMachine &TM) const;
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void propagateIndirectCallRegisterUsage();
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SIFunctionResourceInfo analyzeResourceUsage(const MachineFunction &MF);
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const GCNTargetMachine *TM = nullptr;
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DenseMap<const Function *, SIFunctionResourceInfo> CallGraphResourceInfo;
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Optional<SIFunctionResourceInfo> ModuleWorstCaseInfo;
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPURESOURCEUSAGEANALYSIS_H
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@ -154,23 +154,23 @@ bb:
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declare void @undef_func()
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; GCN-LABEL: {{^}}kernel_call_undef_func:
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; GFX908: .amdhsa_next_free_vgpr 128
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; GFX90A: .amdhsa_next_free_vgpr 512
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; GFX90A: .amdhsa_accum_offset 256
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; GFX908: .amdhsa_next_free_vgpr 32
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; GFX90A: .amdhsa_next_free_vgpr 64
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; GFX90A: .amdhsa_accum_offset 32
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; GCN908: NumVgprs: 128
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; GCN908: NumAgprs: 128
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; GCN90A: NumVgprs: 256
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; GCN90A: NumAgprs: 256
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; GFX908: TotalNumVgprs: 128
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; GFX90A: TotalNumVgprs: 512
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; GFX908: VGPRBlocks: 31
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; GFX90A: VGPRBlocks: 63
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; GFX908: NumVGPRsForWavesPerEU: 128
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; GFX90A: NumVGPRsForWavesPerEU: 512
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; GFX90A: AccumOffset: 256
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; GFX908: Occupancy: 2
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; GFX90A: Occupancy: 1
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; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63
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; GFX908: TotalNumVgprs: 32
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; GFX90A: TotalNumVgprs: 64
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; GFX908: VGPRBlocks: 7
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; GFX90A: VGPRBlocks: 7
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; GFX908: NumVGPRsForWavesPerEU: 32
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; GFX90A: NumVGPRsForWavesPerEU: 64
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; GFX90A: AccumOffset: 32
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; GFX908: Occupancy: 8
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; GFX90A: Occupancy: 8
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; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 7
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define amdgpu_kernel void @kernel_call_undef_func() #0 {
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bb:
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call void @undef_func()
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@ -144,8 +144,8 @@ attributes #0 = { nounwind }
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; GCN: amdpal.pipelines:
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; GCN-NEXT: - .registers:
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; SDAG-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf03cf{{$}}
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; GISEL-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf03cf{{$}}
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; SDAG-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf01ca{{$}}
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; GISEL-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf01ce{{$}}
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; GCN-NEXT: 0x2e13 (COMPUTE_PGM_RSRC2): 0x8001{{$}}
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; GCN-NEXT: .shader_functions:
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; GCN-NEXT: dynamic_stack:
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@ -178,24 +178,25 @@ attributes #0 = { nounwind }
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; GCN-NEXT: .vgpr_count: 0x2{{$}}
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; GCN-NEXT: no_stack_extern_call:
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; GCN-NEXT: .lds_size: 0{{$}}
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; GFX8-NEXT: .sgpr_count: 0x68{{$}}
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; GFX9-NEXT: .sgpr_count: 0x6c{{$}}
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; GFX8-NEXT: .sgpr_count: 0x28{{$}}
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; GFX9-NEXT: .sgpr_count: 0x2c{{$}}
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; GCN-NEXT: .stack_frame_size_in_bytes: 0x10{{$}}
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; GCN-NEXT: .vgpr_count: 0x40{{$}}
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; SDAG-NEXT: .vgpr_count: 0x2b{{$}}
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; GISEL-NEXT: .vgpr_count: 0x34{{$}}
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; GCN-NEXT: no_stack_extern_call_many_args:
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; GCN-NEXT: .lds_size: 0{{$}}
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; GFX8-NEXT: .sgpr_count: 0x68{{$}}
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; GFX9-NEXT: .sgpr_count: 0x6c{{$}}
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; GFX8-NEXT: .sgpr_count: 0x28{{$}}
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; GFX9-NEXT: .sgpr_count: 0x2c{{$}}
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; GCN-NEXT: .stack_frame_size_in_bytes: 0x90{{$}}
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; SDAG-NEXT: .vgpr_count: 0x40{{$}}
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; GISEL-NEXT: .vgpr_count: 0x40{{$}}
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; SDAG-NEXT: .vgpr_count: 0x2b{{$}}
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; GISEL-NEXT: .vgpr_count: 0x34{{$}}
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; GCN-NEXT: no_stack_indirect_call:
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; GCN-NEXT: .lds_size: 0{{$}}
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; GFX8-NEXT: .sgpr_count: 0x68{{$}}
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; GFX9-NEXT: .sgpr_count: 0x6c{{$}}
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; GFX8-NEXT: .sgpr_count: 0x28{{$}}
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; GFX9-NEXT: .sgpr_count: 0x2c{{$}}
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; GCN-NEXT: .stack_frame_size_in_bytes: 0x10{{$}}
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; SDAG-NEXT: .vgpr_count: 0x40{{$}}
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; GISEL-NEXT: .vgpr_count: 0x40{{$}}
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; SDAG-NEXT: .vgpr_count: 0x2b{{$}}
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; GISEL-NEXT: .vgpr_count: 0x34{{$}}
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; GCN-NEXT: simple_lds:
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; GCN-NEXT: .lds_size: 0x100{{$}}
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; GCN-NEXT: .sgpr_count: 0x20{{$}}
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@ -218,17 +219,18 @@ attributes #0 = { nounwind }
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; GCN-NEXT: .vgpr_count: 0x3{{$}}
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; GCN-NEXT: simple_stack_extern_call:
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; GCN-NEXT: .lds_size: 0{{$}}
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; GFX8-NEXT: .sgpr_count: 0x68{{$}}
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; GFX9-NEXT: .sgpr_count: 0x6c{{$}}
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; GFX8-NEXT: .sgpr_count: 0x28{{$}}
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; GFX9-NEXT: .sgpr_count: 0x2c{{$}}
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; GCN-NEXT: .stack_frame_size_in_bytes: 0x20{{$}}
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; GCN-NEXT: .vgpr_count: 0x40{{$}}
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; SDAG-NEXT: .vgpr_count: 0x2b{{$}}
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; GISEL-NEXT: .vgpr_count: 0x34{{$}}
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; GCN-NEXT: simple_stack_indirect_call:
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; GCN-NEXT: .lds_size: 0{{$}}
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; GFX8-NEXT: .sgpr_count: 0x68{{$}}
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; GFX9-NEXT: .sgpr_count: 0x6c{{$}}
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; GFX8-NEXT: .sgpr_count: 0x28{{$}}
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; GFX9-NEXT: .sgpr_count: 0x2c{{$}}
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; GCN-NEXT: .stack_frame_size_in_bytes: 0x20{{$}}
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; SDAG-NEXT: .vgpr_count: 0x40{{$}}
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; GISEL-NEXT: .vgpr_count: 0x40{{$}}
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; SDAG-NEXT: .vgpr_count: 0x2b{{$}}
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; GISEL-NEXT: .vgpr_count: 0x34{{$}}
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; GCN-NEXT: simple_stack_recurse:
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; GCN-NEXT: .lds_size: 0{{$}}
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; GCN-NEXT: .sgpr_count: 0x26{{$}}
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@ -556,9 +556,8 @@ attributes #512 = { nounwind "amdgpu-flat-work-group-size"="512,512" }
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; GCN-LABEL: {{^}}f1024:
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; GFX9: NumVgprs: 64
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; GFX90A: NumVgprs: 128
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; GFX90A: NumAgprs: 128
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; GFX90A: TotalNumVgprs: 256
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; GFX90A: NumAgprs: 64
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; GFX90A: TotalNumVgprs: 128
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; GFX10WGP-WAVE32: NumVgprs: 128
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; GFX10WGP-WAVE64: NumVgprs: 128
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; GFX10CU-WAVE32: NumVgprs: 64
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@ -8,12 +8,12 @@
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@alias = hidden alias void (), void ()* @aliasee_default
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; ALL-LABEL: {{^}}kernel:
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; GFX908: .amdhsa_next_free_vgpr 64
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; GFX908-NEXT: .amdhsa_next_free_sgpr 102
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; GFX908: .amdhsa_next_free_vgpr 41
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; GFX908-NEXT: .amdhsa_next_free_sgpr 33
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; GFX90A: .amdhsa_next_free_vgpr 256
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; GFX90A-NEXT: .amdhsa_next_free_sgpr 102
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; GFX90A-NEXT: .amdhsa_accum_offset 128
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; GFX90A: .amdhsa_next_free_vgpr 71
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; GFX90A-NEXT: .amdhsa_next_free_sgpr 33
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; GFX90A-NEXT: .amdhsa_accum_offset 44
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define amdgpu_kernel void @kernel() #0 {
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bb:
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call void @alias() #2
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@ -7,8 +7,8 @@
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@alias0 = hidden alias void (), void ()* @aliasee_default_vgpr64_sgpr102
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; CHECK-LABEL: {{^}}kernel0:
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; CHECK: .amdhsa_next_free_vgpr 64
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; CHECK-NEXT: .amdhsa_next_free_sgpr 102
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; CHECK: .amdhsa_next_free_vgpr 53
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; CHECK-NEXT: .amdhsa_next_free_sgpr 33
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define amdgpu_kernel void @kernel0() #0 {
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bb:
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call void @alias0() #2
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@ -10,7 +10,7 @@
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; CHECK-LABEL: {{^}}kernel1:
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; CHECK: .amdhsa_next_free_vgpr 42
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; CHECK-NEXT: .amdhsa_next_free_sgpr 74
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; CHECK-NEXT: .amdhsa_next_free_sgpr 33
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define amdgpu_kernel void @kernel1() #0 {
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bb:
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call void asm sideeffect "; clobber v40 ", "~{v40}"()
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@ -7,8 +7,8 @@
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@alias2 = hidden alias void (), void()* @aliasee_vgpr64_sgpr102
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; CHECK-LABEL: {{^}}kernel2:
|
||||
; CHECK: .amdhsa_next_free_vgpr 64
|
||||
; CHECK-NEXT: .amdhsa_next_free_sgpr 102
|
||||
; CHECK: .amdhsa_next_free_vgpr 53
|
||||
; CHECK-NEXT: .amdhsa_next_free_sgpr 33
|
||||
define amdgpu_kernel void @kernel2() #0 {
|
||||
bb:
|
||||
call void @alias2() #2
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@
|
|||
@alias3 = hidden alias void (), void ()* @aliasee_vgpr256_sgpr102
|
||||
|
||||
; CHECK-LABEL: {{^}}kernel3:
|
||||
; CHECK: .amdhsa_next_free_vgpr 256
|
||||
; CHECK-NEXT: .amdhsa_next_free_sgpr 102
|
||||
; CHECK: .amdhsa_next_free_vgpr 253
|
||||
; CHECK-NEXT: .amdhsa_next_free_sgpr 33
|
||||
define amdgpu_kernel void @kernel3() #0 {
|
||||
bb:
|
||||
call void @alias3() #2
|
||||
|
|
|
|||
|
|
@ -227,10 +227,10 @@ define amdgpu_kernel void @usage_direct_recursion(i32 %n) #0 {
|
|||
; Make sure there's no assert when a sgpr96 is used.
|
||||
; GCN-LABEL: {{^}}count_use_sgpr96_external_call
|
||||
; GCN: ; sgpr96 s[{{[0-9]+}}:{{[0-9]+}}]
|
||||
; CI: NumSgprs: 104
|
||||
; VI-NOBUG: NumSgprs: 108
|
||||
; CI: NumSgprs: 84
|
||||
; VI-NOBUG: NumSgprs: 86
|
||||
; VI-BUG: NumSgprs: 96
|
||||
; GCN: NumVgprs: 64
|
||||
; GCN: NumVgprs: 50
|
||||
define amdgpu_kernel void @count_use_sgpr96_external_call() {
|
||||
entry:
|
||||
tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1
|
||||
|
|
@ -241,10 +241,10 @@ entry:
|
|||
; Make sure there's no assert when a sgpr160 is used.
|
||||
; GCN-LABEL: {{^}}count_use_sgpr160_external_call
|
||||
; GCN: ; sgpr160 s[{{[0-9]+}}:{{[0-9]+}}]
|
||||
; CI: NumSgprs: 104
|
||||
; VI-NOBUG: NumSgprs: 108
|
||||
; CI: NumSgprs: 84
|
||||
; VI-NOBUG: NumSgprs: 86
|
||||
; VI-BUG: NumSgprs: 96
|
||||
; GCN: NumVgprs: 64
|
||||
; GCN: NumVgprs: 50
|
||||
define amdgpu_kernel void @count_use_sgpr160_external_call() {
|
||||
entry:
|
||||
tail call void asm sideeffect "; sgpr160 $0", "s"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
|
||||
|
|
@ -255,10 +255,10 @@ entry:
|
|||
; Make sure there's no assert when a vgpr160 is used.
|
||||
; GCN-LABEL: {{^}}count_use_vgpr160_external_call
|
||||
; GCN: ; vgpr160 v[{{[0-9]+}}:{{[0-9]+}}]
|
||||
; CI: NumSgprs: 104
|
||||
; VI-NOBUG: NumSgprs: 108
|
||||
; CI: NumSgprs: 84
|
||||
; VI-NOBUG: NumSgprs: 86
|
||||
; VI-BUG: NumSgprs: 96
|
||||
; GCN: NumVgprs: 64
|
||||
; GCN: NumVgprs: 50
|
||||
define amdgpu_kernel void @count_use_vgpr160_external_call() {
|
||||
entry:
|
||||
tail call void asm sideeffect "; vgpr160 $0", "v"(<5 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14>) #1
|
||||
|
|
|
|||
|
|
@ -16,8 +16,8 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr(i8) {
|
|||
; GCN-NEXT: amd_machine_version_stepping = 0
|
||||
; GCN-NEXT: kernel_code_entry_byte_offset = 256
|
||||
; GCN-NEXT: kernel_code_prefetch_byte_size = 0
|
||||
; GCN-NEXT: granulated_workitem_vgpr_count = 15
|
||||
; GCN-NEXT: granulated_wavefront_sgpr_count = 12
|
||||
; GCN-NEXT: granulated_workitem_vgpr_count = 10
|
||||
; GCN-NEXT: granulated_wavefront_sgpr_count = 8
|
||||
; GCN-NEXT: priority = 0
|
||||
; GCN-NEXT: float_mode = 240
|
||||
; GCN-NEXT: priv = 0
|
||||
|
|
@ -60,8 +60,8 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr(i8) {
|
|||
; GCN-NEXT: gds_segment_byte_size = 0
|
||||
; GCN-NEXT: kernarg_segment_byte_size = 64
|
||||
; GCN-NEXT: workgroup_fbarrier_count = 0
|
||||
; GCN-NEXT: wavefront_sgpr_count = 104
|
||||
; GCN-NEXT: workitem_vgpr_count = 64
|
||||
; GCN-NEXT: wavefront_sgpr_count = 68
|
||||
; GCN-NEXT: workitem_vgpr_count = 42
|
||||
; GCN-NEXT: reserved_vgpr_first = 0
|
||||
; GCN-NEXT: reserved_vgpr_count = 0
|
||||
; GCN-NEXT: reserved_sgpr_first = 0
|
||||
|
|
@ -109,8 +109,8 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr(i8) {
|
|||
; GISEL-NEXT: amd_machine_version_stepping = 0
|
||||
; GISEL-NEXT: kernel_code_entry_byte_offset = 256
|
||||
; GISEL-NEXT: kernel_code_prefetch_byte_size = 0
|
||||
; GISEL-NEXT: granulated_workitem_vgpr_count = 15
|
||||
; GISEL-NEXT: granulated_wavefront_sgpr_count = 12
|
||||
; GISEL-NEXT: granulated_workitem_vgpr_count = 10
|
||||
; GISEL-NEXT: granulated_wavefront_sgpr_count = 8
|
||||
; GISEL-NEXT: priority = 0
|
||||
; GISEL-NEXT: float_mode = 240
|
||||
; GISEL-NEXT: priv = 0
|
||||
|
|
@ -153,8 +153,8 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr(i8) {
|
|||
; GISEL-NEXT: gds_segment_byte_size = 0
|
||||
; GISEL-NEXT: kernarg_segment_byte_size = 64
|
||||
; GISEL-NEXT: workgroup_fbarrier_count = 0
|
||||
; GISEL-NEXT: wavefront_sgpr_count = 104
|
||||
; GISEL-NEXT: workitem_vgpr_count = 64
|
||||
; GISEL-NEXT: wavefront_sgpr_count = 68
|
||||
; GISEL-NEXT: workitem_vgpr_count = 42
|
||||
; GISEL-NEXT: reserved_vgpr_first = 0
|
||||
; GISEL-NEXT: reserved_vgpr_count = 0
|
||||
; GISEL-NEXT: reserved_sgpr_first = 0
|
||||
|
|
@ -207,8 +207,8 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr_arg(i8) {
|
|||
; GCN-NEXT: amd_machine_version_stepping = 0
|
||||
; GCN-NEXT: kernel_code_entry_byte_offset = 256
|
||||
; GCN-NEXT: kernel_code_prefetch_byte_size = 0
|
||||
; GCN-NEXT: granulated_workitem_vgpr_count = 15
|
||||
; GCN-NEXT: granulated_wavefront_sgpr_count = 12
|
||||
; GCN-NEXT: granulated_workitem_vgpr_count = 10
|
||||
; GCN-NEXT: granulated_wavefront_sgpr_count = 8
|
||||
; GCN-NEXT: priority = 0
|
||||
; GCN-NEXT: float_mode = 240
|
||||
; GCN-NEXT: priv = 0
|
||||
|
|
@ -251,8 +251,8 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr_arg(i8) {
|
|||
; GCN-NEXT: gds_segment_byte_size = 0
|
||||
; GCN-NEXT: kernarg_segment_byte_size = 64
|
||||
; GCN-NEXT: workgroup_fbarrier_count = 0
|
||||
; GCN-NEXT: wavefront_sgpr_count = 104
|
||||
; GCN-NEXT: workitem_vgpr_count = 64
|
||||
; GCN-NEXT: wavefront_sgpr_count = 68
|
||||
; GCN-NEXT: workitem_vgpr_count = 42
|
||||
; GCN-NEXT: reserved_vgpr_first = 0
|
||||
; GCN-NEXT: reserved_vgpr_count = 0
|
||||
; GCN-NEXT: reserved_sgpr_first = 0
|
||||
|
|
@ -301,8 +301,8 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr_arg(i8) {
|
|||
; GISEL-NEXT: amd_machine_version_stepping = 0
|
||||
; GISEL-NEXT: kernel_code_entry_byte_offset = 256
|
||||
; GISEL-NEXT: kernel_code_prefetch_byte_size = 0
|
||||
; GISEL-NEXT: granulated_workitem_vgpr_count = 15
|
||||
; GISEL-NEXT: granulated_wavefront_sgpr_count = 12
|
||||
; GISEL-NEXT: granulated_workitem_vgpr_count = 10
|
||||
; GISEL-NEXT: granulated_wavefront_sgpr_count = 8
|
||||
; GISEL-NEXT: priority = 0
|
||||
; GISEL-NEXT: float_mode = 240
|
||||
; GISEL-NEXT: priv = 0
|
||||
|
|
@ -345,8 +345,8 @@ define amdgpu_kernel void @test_indirect_call_sgpr_ptr_arg(i8) {
|
|||
; GISEL-NEXT: gds_segment_byte_size = 0
|
||||
; GISEL-NEXT: kernarg_segment_byte_size = 64
|
||||
; GISEL-NEXT: workgroup_fbarrier_count = 0
|
||||
; GISEL-NEXT: wavefront_sgpr_count = 104
|
||||
; GISEL-NEXT: workitem_vgpr_count = 64
|
||||
; GISEL-NEXT: wavefront_sgpr_count = 68
|
||||
; GISEL-NEXT: workitem_vgpr_count = 42
|
||||
; GISEL-NEXT: reserved_vgpr_first = 0
|
||||
; GISEL-NEXT: reserved_vgpr_count = 0
|
||||
; GISEL-NEXT: reserved_sgpr_first = 0
|
||||
|
|
|
|||
|
|
@ -91,6 +91,7 @@ define void @func_call_tail_call() #1 {
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}void_func_void:
|
||||
define void @void_func_void() noinline {
|
||||
ret void
|
||||
}
|
||||
|
|
@ -105,6 +106,7 @@ define void @test_funcx2() #0 {
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}wombat:
|
||||
define weak amdgpu_kernel void @wombat(i32* %arg, i32* %arg2) {
|
||||
bb:
|
||||
call void @hoge() #0
|
||||
|
|
|
|||
|
|
@ -136,12 +136,12 @@
|
|||
; GCN-O0-NEXT: Branch relaxation pass
|
||||
; GCN-O0-NEXT: Register Usage Information Collector Pass
|
||||
; GCN-O0-NEXT: Live DEBUG_VALUE analysis
|
||||
; GCN-O0-NEXT: Function register usage analysis
|
||||
; GCN-O0-NEXT: FunctionPass Manager
|
||||
; GCN-O0-NEXT: Lazy Machine Block Frequency Analysis
|
||||
; GCN-O0-NEXT: Machine Optimization Remark Emitter
|
||||
; GCN-O0-NEXT: AMDGPU Assembly Printer
|
||||
; GCN-O0-NEXT: Free MachineFunction
|
||||
; GCN-O0-NEXT: Function register usage analysis
|
||||
; GCN-O0-NEXT: FunctionPass Manager
|
||||
; GCN-O0-NEXT: Lazy Machine Block Frequency Analysis
|
||||
; GCN-O0-NEXT: Machine Optimization Remark Emitter
|
||||
; GCN-O0-NEXT: AMDGPU Assembly Printer
|
||||
; GCN-O0-NEXT: Free MachineFunction
|
||||
; GCN-O0-NEXT:Pass Arguments: -domtree
|
||||
; GCN-O0-NEXT: FunctionPass Manager
|
||||
; GCN-O0-NEXT: Dominator Tree Construction
|
||||
|
|
@ -388,12 +388,12 @@
|
|||
; GCN-O1-NEXT: Branch relaxation pass
|
||||
; GCN-O1-NEXT: Register Usage Information Collector Pass
|
||||
; GCN-O1-NEXT: Live DEBUG_VALUE analysis
|
||||
; GCN-O1-NEXT: Function register usage analysis
|
||||
; GCN-O1-NEXT: FunctionPass Manager
|
||||
; GCN-O1-NEXT: Lazy Machine Block Frequency Analysis
|
||||
; GCN-O1-NEXT: Machine Optimization Remark Emitter
|
||||
; GCN-O1-NEXT: AMDGPU Assembly Printer
|
||||
; GCN-O1-NEXT: Free MachineFunction
|
||||
; GCN-O1-NEXT: Function register usage analysis
|
||||
; GCN-O1-NEXT: FunctionPass Manager
|
||||
; GCN-O1-NEXT: Lazy Machine Block Frequency Analysis
|
||||
; GCN-O1-NEXT: Machine Optimization Remark Emitter
|
||||
; GCN-O1-NEXT: AMDGPU Assembly Printer
|
||||
; GCN-O1-NEXT: Free MachineFunction
|
||||
; GCN-O1-NEXT:Pass Arguments: -domtree
|
||||
; GCN-O1-NEXT: FunctionPass Manager
|
||||
; GCN-O1-NEXT: Dominator Tree Construction
|
||||
|
|
@ -673,12 +673,12 @@
|
|||
; GCN-O1-OPTS-NEXT: Branch relaxation pass
|
||||
; GCN-O1-OPTS-NEXT: Register Usage Information Collector Pass
|
||||
; GCN-O1-OPTS-NEXT: Live DEBUG_VALUE analysis
|
||||
; GCN-O1-OPTS-NEXT: Function register usage analysis
|
||||
; GCN-O1-OPTS-NEXT: FunctionPass Manager
|
||||
; GCN-O1-OPTS-NEXT: Lazy Machine Block Frequency Analysis
|
||||
; GCN-O1-OPTS-NEXT: Machine Optimization Remark Emitter
|
||||
; GCN-O1-OPTS-NEXT: AMDGPU Assembly Printer
|
||||
; GCN-O1-OPTS-NEXT: Free MachineFunction
|
||||
; GCN-O1-OPTS-NEXT: Function register usage analysis
|
||||
; GCN-O1-OPTS-NEXT: FunctionPass Manager
|
||||
; GCN-O1-OPTS-NEXT: Lazy Machine Block Frequency Analysis
|
||||
; GCN-O1-OPTS-NEXT: Machine Optimization Remark Emitter
|
||||
; GCN-O1-OPTS-NEXT: AMDGPU Assembly Printer
|
||||
; GCN-O1-OPTS-NEXT: Free MachineFunction
|
||||
; GCN-O1-OPTS-NEXT:Pass Arguments: -domtree
|
||||
; GCN-O1-OPTS-NEXT: FunctionPass Manager
|
||||
; GCN-O1-OPTS-NEXT: Dominator Tree Construction
|
||||
|
|
@ -960,12 +960,12 @@
|
|||
; GCN-O2-NEXT: Branch relaxation pass
|
||||
; GCN-O2-NEXT: Register Usage Information Collector Pass
|
||||
; GCN-O2-NEXT: Live DEBUG_VALUE analysis
|
||||
; GCN-O2-NEXT: Function register usage analysis
|
||||
; GCN-O2-NEXT: FunctionPass Manager
|
||||
; GCN-O2-NEXT: Lazy Machine Block Frequency Analysis
|
||||
; GCN-O2-NEXT: Machine Optimization Remark Emitter
|
||||
; GCN-O2-NEXT: AMDGPU Assembly Printer
|
||||
; GCN-O2-NEXT: Free MachineFunction
|
||||
; GCN-O2-NEXT: Function register usage analysis
|
||||
; GCN-O2-NEXT: FunctionPass Manager
|
||||
; GCN-O2-NEXT: Lazy Machine Block Frequency Analysis
|
||||
; GCN-O2-NEXT: Machine Optimization Remark Emitter
|
||||
; GCN-O2-NEXT: AMDGPU Assembly Printer
|
||||
; GCN-O2-NEXT: Free MachineFunction
|
||||
; GCN-O2-NEXT:Pass Arguments: -domtree
|
||||
; GCN-O2-NEXT: FunctionPass Manager
|
||||
; GCN-O2-NEXT: Dominator Tree Construction
|
||||
|
|
@ -1260,12 +1260,12 @@
|
|||
; GCN-O3-NEXT: Branch relaxation pass
|
||||
; GCN-O3-NEXT: Register Usage Information Collector Pass
|
||||
; GCN-O3-NEXT: Live DEBUG_VALUE analysis
|
||||
; GCN-O3-NEXT: Function register usage analysis
|
||||
; GCN-O3-NEXT: FunctionPass Manager
|
||||
; GCN-O3-NEXT: Lazy Machine Block Frequency Analysis
|
||||
; GCN-O3-NEXT: Machine Optimization Remark Emitter
|
||||
; GCN-O3-NEXT: AMDGPU Assembly Printer
|
||||
; GCN-O3-NEXT: Free MachineFunction
|
||||
; GCN-O3-NEXT: Function register usage analysis
|
||||
; GCN-O3-NEXT: FunctionPass Manager
|
||||
; GCN-O3-NEXT: Lazy Machine Block Frequency Analysis
|
||||
; GCN-O3-NEXT: Machine Optimization Remark Emitter
|
||||
; GCN-O3-NEXT: AMDGPU Assembly Printer
|
||||
; GCN-O3-NEXT: Free MachineFunction
|
||||
; GCN-O3-NEXT:Pass Arguments: -domtree
|
||||
; GCN-O3-NEXT: FunctionPass Manager
|
||||
; GCN-O3-NEXT: Dominator Tree Construction
|
||||
|
|
|
|||
|
|
@ -1,6 +1,9 @@
|
|||
; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX908 %s
|
||||
; RUN: not llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefixes=GCN,GFX900 %s
|
||||
|
||||
; GFX900: couldn't allocate input reg for constraint 'a'
|
||||
|
||||
|
||||
; GCN-LABEL: {{^}}max_10_vgprs:
|
||||
; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
|
||||
; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
|
||||
|
|
@ -65,8 +68,6 @@ define amdgpu_kernel void @max_10_vgprs(i32 addrspace(1)* %p) #0 {
|
|||
; GFX908: v_accvgpr_read_b32 [[V_REG]], [[A_REG]]
|
||||
; GFX908-NOT: buffer_
|
||||
|
||||
; GFX900: couldn't allocate input reg for constraint 'a'
|
||||
|
||||
; GFX908: NumVgprs: 10
|
||||
; GFX908: ScratchSize: 0
|
||||
; GFX908: VGPRBlocks: 2
|
||||
|
|
|
|||
|
|
@ -14,6 +14,9 @@
|
|||
|
||||
; RUN: llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
|
||||
|
||||
; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (i32 addrspace(1)*): debugtrap handler not supported
|
||||
|
||||
|
||||
declare void @llvm.trap() #0
|
||||
declare void @llvm.debugtrap() #1
|
||||
|
||||
|
|
@ -54,7 +57,6 @@ define amdgpu_kernel void @hsa_trap(i32 addrspace(1)* nocapture readonly %arg0)
|
|||
; NOMESA-TRAP: .long 47180
|
||||
; NOMESA-TRAP-NEXT: .long 144
|
||||
|
||||
; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (i32 addrspace(1)*): debugtrap handler not supported
|
||||
; GCN-LABEL: {{^}}hsa_debugtrap:
|
||||
; HSA-TRAP: enable_trap_handler = 0
|
||||
; HSA-TRAP: s_trap 3
|
||||
|
|
|
|||
Loading…
Reference in New Issue