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Remove refs to non-DebugLoc version of BuildMI from XCore, PIC16. 

llvm-svn: 64432
This commit is contained in:
Dale Johannesen 2009-02-13 02:29:03 +00:00
parent e9f623e27c
commit 460bfeba8c
4 changed files with 45 additions and 39 deletions
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5
llvm/lib/Target/PIC16/PIC16ISelLowering.cpp
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@ -1362,6 +1362,7 @@ PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const { MachineBasicBlock *BB) const {
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm(); unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
DebugLoc dl = MI->getDebugLoc();
// To "insert" a SELECT_CC instruction, we actually have to insert the diamond // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
// control-flow pattern. The incoming instruction knows the destination vreg // control-flow pattern. The incoming instruction knows the destination vreg
@ -1380,7 +1381,7 @@ PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineFunction *F = BB->getParent(); MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
BuildMI(BB, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC); BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
F->insert(It, copy0MBB); F->insert(It, copy0MBB);
F->insert(It, sinkMBB); F->insert(It, sinkMBB);
@ -1403,7 +1404,7 @@ PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ... // ...
BB = sinkMBB; BB = sinkMBB;
BuildMI(BB, TII.get(PIC16::PHI), MI->getOperand(0).getReg()) BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);

10
llvm/lib/Target/XCore/XCoreInstrInfo.cpp
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@ -302,6 +302,8 @@ unsigned
XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond)const{ const SmallVectorImpl<MachineOperand> &Cond)const{
// FIXME there should probably be a DebugLoc argument here
DebugLoc dl = DebugLoc::getUnknownLoc();
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) && assert((Cond.size() == 2 || Cond.size() == 0) &&
@ -310,11 +312,11 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
if (FBB == 0) { // One way branch. if (FBB == 0) { // One way branch.
if (Cond.empty()) { if (Cond.empty()) {
// Unconditional branch // Unconditional branch
BuildMI(&MBB, get(XCore::BRFU_lu6)).addMBB(TBB); BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(TBB);
} else { } else {
// Conditional branch. // Conditional branch.
unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
BuildMI(&MBB, get(Opc)).addReg(Cond[1].getReg()) BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg())
.addMBB(TBB); .addMBB(TBB);
} }
return 1; return 1;
@ -323,9 +325,9 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
// Two-way Conditional branch. // Two-way Conditional branch.
assert(Cond.size() == 2 && "Unexpected number of components!"); assert(Cond.size() == 2 && "Unexpected number of components!");
unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
BuildMI(&MBB, get(Opc)).addReg(Cond[1].getReg()) BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg())
.addMBB(TBB); .addMBB(TBB);
BuildMI(&MBB, get(XCore::BRFU_lu6)).addMBB(FBB); BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(FBB);
return 2; return 2;
} }

63
llvm/lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@ -171,6 +171,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, RegScavenger *RS) const { int SPAdj, RegScavenger *RS) const {
assert(SPAdj == 0 && "Unexpected"); assert(SPAdj == 0 && "Unexpected");
MachineInstr &MI = *II; MachineInstr &MI = *II;
DebugLoc dl = MI.getDebugLoc();
unsigned i = 0; unsigned i = 0;
while (!MI.getOperand(i).isFI()) { while (!MI.getOperand(i).isFI()) {
@ -231,21 +232,21 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
} }
unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II, unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
SPAdj); SPAdj);
loadConstant(MBB, II, ScratchReg, Offset); loadConstant(MBB, II, ScratchReg, Offset, dl);
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case XCore::LDWFI: case XCore::LDWFI:
New = BuildMI(MBB, II, TII.get(XCore::LDW_3r), Reg) New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
.addReg(FramePtr) .addReg(FramePtr)
.addReg(ScratchReg, false, false, true); .addReg(ScratchReg, false, false, true);
break; break;
case XCore::STWFI: case XCore::STWFI:
New = BuildMI(MBB, II, TII.get(XCore::STW_3r)) New = BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
.addReg(Reg, false, false, isKill) .addReg(Reg, false, false, isKill)
.addReg(FramePtr) .addReg(FramePtr)
.addReg(ScratchReg, false, false, true); .addReg(ScratchReg, false, false, true);
break; break;
case XCore::LDAWFI: case XCore::LDAWFI:
New = BuildMI(MBB, II, TII.get(XCore::LDAWF_l3r), Reg) New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
.addReg(FramePtr) .addReg(FramePtr)
.addReg(ScratchReg, false, false, true); .addReg(ScratchReg, false, false, true);
break; break;
@ -255,18 +256,18 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
} else { } else {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case XCore::LDWFI: case XCore::LDWFI:
New = BuildMI(MBB, II, TII.get(XCore::LDW_2rus), Reg) New = BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
.addReg(FramePtr) .addReg(FramePtr)
.addImm(Offset); .addImm(Offset);
break; break;
case XCore::STWFI: case XCore::STWFI:
New = BuildMI(MBB, II, TII.get(XCore::STW_2rus)) New = BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
.addReg(Reg, false, false, isKill) .addReg(Reg, false, false, isKill)
.addReg(FramePtr) .addReg(FramePtr)
.addImm(Offset); .addImm(Offset);
break; break;
case XCore::LDAWFI: case XCore::LDAWFI:
New = BuildMI(MBB, II, TII.get(XCore::LDAWF_l2rus), Reg) New = BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
.addReg(FramePtr) .addReg(FramePtr)
.addImm(Offset); .addImm(Offset);
break; break;
@ -286,18 +287,18 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int NewOpcode; int NewOpcode;
case XCore::LDWFI: case XCore::LDWFI:
NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
BuildMI(MBB, II, TII.get(NewOpcode), Reg) BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
.addImm(Offset); .addImm(Offset);
break; break;
case XCore::STWFI: case XCore::STWFI:
NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
BuildMI(MBB, II, TII.get(NewOpcode)) BuildMI(MBB, II, dl, TII.get(NewOpcode))
.addReg(Reg, false, false, isKill) .addReg(Reg, false, false, isKill)
.addImm(Offset); .addImm(Offset);
break; break;
case XCore::LDAWFI: case XCore::LDAWFI:
NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
BuildMI(MBB, II, TII.get(NewOpcode), Reg) BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
.addImm(Offset); .addImm(Offset);
break; break;
default: default:
@ -349,7 +350,7 @@ processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
void XCoreRegisterInfo:: void XCoreRegisterInfo::
loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DstReg, int64_t Value) const { unsigned DstReg, int64_t Value, DebugLoc dl) const {
// TODO use mkmsk if possible. // TODO use mkmsk if possible.
if (!isImmU16(Value)) { if (!isImmU16(Value)) {
// TODO use constant pool. // TODO use constant pool.
@ -357,12 +358,12 @@ loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
abort(); abort();
} }
int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6; int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
BuildMI(MBB, I, TII.get(Opcode), DstReg).addImm(Value); BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
} }
void XCoreRegisterInfo:: void XCoreRegisterInfo::
storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int Offset) const { unsigned SrcReg, int Offset, DebugLoc dl) const {
assert(Offset%4 == 0 && "Misaligned stack offset"); assert(Offset%4 == 0 && "Misaligned stack offset");
Offset/=4; Offset/=4;
bool isU6 = isImmU6(Offset); bool isU6 = isImmU6(Offset);
@ -371,23 +372,23 @@ storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
abort(); abort();
} }
int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6; int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
BuildMI(MBB, I, TII.get(Opcode)) BuildMI(MBB, I, dl, TII.get(Opcode))
.addReg(SrcReg) .addReg(SrcReg)
.addImm(Offset); .addImm(Offset);
} }
void XCoreRegisterInfo:: void XCoreRegisterInfo::
loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DstReg, int Offset) const { unsigned DstReg, int Offset, DebugLoc dl) const {
assert(Offset%4 == 0 && "Misaligned stack offset"); assert(Offset%4 == 0 && "Misaligned stack offset");
Offset/=4; Offset/=4;
bool isU6 = isImmU6(Offset); bool isU6 = isImmU6(Offset);
if (!isU6 && !isImmU16(Offset)) { if (!isU6 && !isImmU16(Offset)) {
cerr << "storeToStack offset too big " << Offset << "\n"; cerr << "loadFromStack offset too big " << Offset << "\n";
abort(); abort();
} }
int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
BuildMI(MBB, I, TII.get(Opcode), DstReg) BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
.addImm(Offset); .addImm(Offset);
} }
@ -397,6 +398,7 @@ void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
DebugLoc dl = DebugLoc::getUnknownLoc();
bool FP = hasFP(MF); bool FP = hasFP(MF);
@ -429,14 +431,14 @@ void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
} else { } else {
Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
} }
BuildMI(MBB, MBBI, TII.get(Opcode)).addImm(FrameSize); BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
if (emitFrameMoves) { if (emitFrameMoves) {
std::vector<MachineMove> &Moves = MMI->getFrameMoves(); std::vector<MachineMove> &Moves = MMI->getFrameMoves();
// Show update of SP. // Show update of SP.
unsigned FrameLabelId = MMI->NextLabelID(); unsigned FrameLabelId = MMI->NextLabelID();
BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId); BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
MachineLocation SPDst(MachineLocation::VirtualFP); MachineLocation SPDst(MachineLocation::VirtualFP);
MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4); MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4);
@ -450,12 +452,12 @@ void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
} }
if (saveLR) { if (saveLR) {
int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot()); int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4); storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl);
MBB.addLiveIn(XCore::LR); MBB.addLiveIn(XCore::LR);
if (emitFrameMoves) { if (emitFrameMoves) {
unsigned SaveLRLabelId = MMI->NextLabelID(); unsigned SaveLRLabelId = MMI->NextLabelID();
BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(SaveLRLabelId); BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveLRLabelId);
MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset); MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset);
MachineLocation CSSrc(XCore::LR); MachineLocation CSSrc(XCore::LR);
MMI->getFrameMoves().push_back(MachineMove(SaveLRLabelId, MMI->getFrameMoves().push_back(MachineMove(SaveLRLabelId,
@ -467,12 +469,12 @@ void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
if (FP) { if (FP) {
// Save R10 to the stack. // Save R10 to the stack.
int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot()); int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4); storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl);
// R10 is live-in. It is killed at the spill. // R10 is live-in. It is killed at the spill.
MBB.addLiveIn(XCore::R10); MBB.addLiveIn(XCore::R10);
if (emitFrameMoves) { if (emitFrameMoves) {
unsigned SaveR10LabelId = MMI->NextLabelID(); unsigned SaveR10LabelId = MMI->NextLabelID();
BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(SaveR10LabelId); BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveR10LabelId);
MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset); MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset);
MachineLocation CSSrc(XCore::R10); MachineLocation CSSrc(XCore::R10);
MMI->getFrameMoves().push_back(MachineMove(SaveR10LabelId, MMI->getFrameMoves().push_back(MachineMove(SaveR10LabelId,
@ -480,12 +482,12 @@ void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
} }
// Set the FP from the SP. // Set the FP from the SP.
unsigned FramePtr = XCore::R10; unsigned FramePtr = XCore::R10;
BuildMI(MBB, MBBI, TII.get(XCore::LDAWSP_ru6), FramePtr) BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
.addImm(0); .addImm(0);
if (emitFrameMoves) { if (emitFrameMoves) {
// Show FP is now valid. // Show FP is now valid.
unsigned FrameLabelId = MMI->NextLabelID(); unsigned FrameLabelId = MMI->NextLabelID();
BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId); BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
MachineLocation SPDst(FramePtr); MachineLocation SPDst(FramePtr);
MachineLocation SPSrc(MachineLocation::VirtualFP); MachineLocation SPSrc(MachineLocation::VirtualFP);
MMI->getFrameMoves().push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); MMI->getFrameMoves().push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
@ -513,13 +515,14 @@ void XCoreRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end()); MachineBasicBlock::iterator MBBI = prior(MBB.end());
DebugLoc dl = DebugLoc::getUnknownLoc();
bool FP = hasFP(MF); bool FP = hasFP(MF);
if (FP) { if (FP) {
// Restore the stack pointer. // Restore the stack pointer.
unsigned FramePtr = XCore::R10; unsigned FramePtr = XCore::R10;
BuildMI(MBB, MBBI, TII.get(XCore::SETSP_1r)) BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
.addReg(FramePtr); .addReg(FramePtr);
} }
@ -545,13 +548,13 @@ void XCoreRegisterInfo::emitEpilogue(MachineFunction &MF,
// Restore R10 // Restore R10
int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot()); int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
FPSpillOffset += FrameSize*4; FPSpillOffset += FrameSize*4;
loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset); loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl);
} }
bool restoreLR = XFI->getUsesLR(); bool restoreLR = XFI->getUsesLR();
if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) { if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) {
int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot()); int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
LRSpillOffset += FrameSize*4; LRSpillOffset += FrameSize*4;
loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset); loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl);
restoreLR = false; restoreLR = false;
} }
if (restoreLR) { if (restoreLR) {
@ -559,11 +562,11 @@ void XCoreRegisterInfo::emitEpilogue(MachineFunction &MF,
assert(MBBI->getOpcode() == XCore::RETSP_u6 assert(MBBI->getOpcode() == XCore::RETSP_u6
|| MBBI->getOpcode() == XCore::RETSP_lu6); || MBBI->getOpcode() == XCore::RETSP_lu6);
int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6; int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
BuildMI(MBB, MBBI, TII.get(Opcode)).addImm(FrameSize); BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
MBB.erase(MBBI); MBB.erase(MBBI);
} else { } else {
int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
BuildMI(MBB, MBBI, TII.get(Opcode), XCore::SP).addImm(FrameSize); BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
} }
} }
} }

6
llvm/lib/Target/XCore/XCoreRegisterInfo.h
View File

@ -27,15 +27,15 @@ private:
void loadConstant(MachineBasicBlock &MBB, void loadConstant(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DstReg, int64_t Value) const; unsigned DstReg, int64_t Value, DebugLoc dl) const;
void storeToStack(MachineBasicBlock &MBB, void storeToStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned SrcReg, int Offset) const; unsigned SrcReg, int Offset, DebugLoc dl) const;
void loadFromStack(MachineBasicBlock &MBB, void loadFromStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DstReg, int Offset) const; unsigned DstReg, int Offset, DebugLoc dl) const;
public: public:
XCoreRegisterInfo(const TargetInstrInfo &tii); XCoreRegisterInfo(const TargetInstrInfo &tii);