forked from OSchip/llvm-project
[X86] Enable RRL part of the LEA optimization pass for -O2.
Enable "Remove Redundant LEAs" part of the LEA optimization pass for -O2. This gives 6.4% performance improve on Broadwell on nnet benchmark from Coremark-pro. There is no significant effect on other benchmarks (Geekbench, Spec2000, Spec2006). Differential Revision: http://reviews.llvm.org/D19659 llvm-svn: 270036
This commit is contained in:
Andrey Turetskiy
parent
3f64bb9618
commit
45b22a4aff
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@ -8,7 +8,7 @@
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//===----------------------------------------------------------------------===//
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//
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// This file defines the pass that performs some optimizations with LEA
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// instructions in order to improve code size.
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// instructions in order to improve performance and code size.
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// Currently, it does two things:
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// 1) If there are two LEA instructions calculating addresses which only differ
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// by displacement inside a basic block, one of them is removed.
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@ -614,9 +614,7 @@ bool OptimizeLEAPass::removeRedundantLEAs(MemOpMap &LEAs) {
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bool OptimizeLEAPass::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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// Perform this optimization only if we care about code size.
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if (DisableX86LEAOpt || skipFunction(*MF.getFunction()) ||
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!MF.getFunction()->optForSize())
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if (DisableX86LEAOpt || skipFunction(*MF.getFunction()))
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return false;
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MRI = &MF.getRegInfo();
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@ -635,13 +633,13 @@ bool OptimizeLEAPass::runOnMachineFunction(MachineFunction &MF) {
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if (LEAs.empty())
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continue;
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// Remove redundant LEA instructions. The optimization may have a negative
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// effect on performance, so do it only for -Oz.
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if (MF.getFunction()->optForMinSize())
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Changed |= removeRedundantLEAs(LEAs);
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// Remove redundant LEA instructions.
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Changed |= removeRedundantLEAs(LEAs);
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// Remove redundant address calculations.
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Changed |= removeRedundantAddrCalc(LEAs);
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// Remove redundant address calculations. Do it only for -Os/-Oz since only
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// a code size gain is expected from this part of the pass.
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if (MF.getFunction()->optForSize())
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Changed |= removeRedundantAddrCalc(LEAs);
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}
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return Changed;
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=ENABLED
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; RUN: llc --disable-x86-lea-opt < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=DISABLED
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%struct.anon1 = type { i32, i32, i32 }
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%struct.anon2 = type { i32, [32 x i32], i32 }
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@ -38,12 +39,14 @@ sw.epilog: ; preds = %sw.bb.2, %sw.bb.1,
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; CHECK: movl arr1([[REG1]],[[REG1]],2), {{.*}}
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; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]]
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; CHECK: subl arr1+4([[REG1]],[[REG1]],2), {{.*}}
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; CHECK: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]]
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; DISABLED: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]]
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; CHECK: addl arr1+8([[REG1]],[[REG1]],2), {{.*}}
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; CHECK: movl ${{[1-4]+}}, ([[REG3]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; CHECK: movl ${{[1-4]+}}, ([[REG3]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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}
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define void @test2(i64 %x) nounwind optsize {
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@ -75,15 +78,20 @@ sw.epilog: ; preds = %sw.bb.2, %sw.bb.1,
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ret void
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; CHECK-LABEL: test2:
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; CHECK: shlq $2, [[REG1:%[a-z]+]]
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; DISABLED: movl arr1([[REG1]],[[REG1]],2), {{.*}}
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; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]]
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; CHECK: movl -4([[REG2]]), {{.*}}
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; CHECK: subl ([[REG2]]), {{.*}}
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; CHECK: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]]
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; CHECK: addl ([[REG3]]), {{.*}}
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; ENABLED: movl -4([[REG2]]), {{.*}}
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; ENABLED: subl ([[REG2]]), {{.*}}
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; ENABLED: addl 4([[REG2]]), {{.*}}
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; DISABLED: subl arr1+4([[REG1]],[[REG1]],2), {{.*}}
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; DISABLED: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]]
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; DISABLED: addl arr1+8([[REG1]],[[REG1]],2), {{.*}}
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; CHECK: movl ${{[1-4]+}}, ([[REG3]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; CHECK: movl ${{[1-4]+}}, ([[REG3]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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}
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; Check that LEA optimization pass takes into account a resultant address
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@ -109,7 +117,9 @@ sw.bb.1: ; preds = %entry
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sw.bb.2: ; preds = %entry
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store i32 333, i32* %a, align 4
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store i32 444, i32* %b, align 4
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; Make sure the REG3's definition LEA won't be removed as redundant.
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%cvt = ptrtoint i32* %b to i32
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store i32 %cvt, i32* %b, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
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@ -122,12 +132,14 @@ sw.epilog: ; preds = %sw.bb.2, %sw.bb.1,
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; REG3's definition is closer to movl than REG2's, but the pass still chooses
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; REG2 because it provides the resultant address displacement fitting 1 byte.
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; CHECK: movl ([[REG2]]), {{.*}}
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; CHECK: addl ([[REG3]]), {{.*}}
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; ENABLED: movl ([[REG2]]), {{.*}}
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; ENABLED: addl ([[REG3]]), {{.*}}
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; DISABLED: movl arr2+132([[REG1]]), {{.*}}
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; DISABLED: addl arr2([[REG1]]), {{.*}}
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; CHECK: movl ${{[1-4]+}}, ([[REG3]])
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; CHECK: movl ${{[1-4]+}}, ([[REG3]])
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; CHECK: movl {{.*}}, ([[REG3]])
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}
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define void @test4(i64 %x) nounwind minsize {
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@ -158,12 +170,19 @@ sw.bb.2: ; preds = %entry
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sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
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ret void
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; CHECK-LABEL: test4:
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; CHECK: leaq arr1+4({{.*}}), [[REG2:%[a-z]+]]
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; CHECK: movl -4([[REG2]]), {{.*}}
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; CHECK: subl ([[REG2]]), {{.*}}
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; CHECK: addl 4([[REG2]]), {{.*}}
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; CHECK: imulq {{.*}}, [[REG1:%[a-z]+]]
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; DISABLED: movl arr1([[REG1]]), {{.*}}
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; CHECK: leaq arr1+4([[REG1]]), [[REG2:%[a-z]+]]
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; ENABLED: movl -4([[REG2]]), {{.*}}
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; ENABLED: subl ([[REG2]]), {{.*}}
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; ENABLED: addl 4([[REG2]]), {{.*}}
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; DISABLED: subl arr1+4([[REG1]]), {{.*}}
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; DISABLED: leaq arr1+8([[REG1]]), [[REG3:%[a-z]+]]
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; DISABLED: addl arr1+8([[REG1]]), {{.*}}
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; CHECK: movl ${{[1-4]+}}, 4([[REG2]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; CHECK: movl ${{[1-4]+}}, 4([[REG2]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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}
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