forked from OSchip/llvm-project
Improve handling of COPY instructions with identical value numbers
Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
This commit is contained in:
Krzysztof Parzyszek
parent
2f5ca59497
commit
4581f37e7c
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@ -233,9 +233,11 @@ namespace {
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void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
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MachineOperand &MO, unsigned SubRegIdx);
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/// Handle copies of undef values.
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/// Returns true if @p CopyMI was a copy of an undef value and eliminated.
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bool eliminateUndefCopy(MachineInstr *CopyMI);
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/// Handle copies of undef values. If the undef value is an incoming
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/// PHI value, it will convert @p CopyMI to an IMPLICIT_DEF.
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/// Returns nullptr if @p CopyMI was not in any way eliminable. Otherwise,
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/// it returns @p CopyMI (which could be an IMPLICIT_DEF at this point).
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MachineInstr *eliminateUndefCopy(MachineInstr *CopyMI);
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/// Check whether or not we should apply the terminal rule on the
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/// destination (Dst) of \p Copy.
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@ -1367,7 +1369,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
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return true;
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}
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bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
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MachineInstr *RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
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// ProcessImplicitDefs may leave some copies of <undef> values, it only
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// removes local variables. When we have a copy like:
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//
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@ -1391,16 +1393,34 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
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if ((SR.LaneMask & SrcMask).none())
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continue;
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if (SR.liveAt(Idx))
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return false;
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return nullptr;
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}
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} else if (SrcLI.liveAt(Idx))
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return false;
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return nullptr;
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LLVM_DEBUG(dbgs() << "\tEliminating copy of <undef> value\n");
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// Remove any DstReg segments starting at the instruction.
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// If the undef copy defines a live-out value (i.e. an input to a PHI def),
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// then replace it with an IMPLICIT_DEF.
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LiveInterval &DstLI = LIS->getInterval(DstReg);
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SlotIndex RegIndex = Idx.getRegSlot();
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LiveRange::Segment *Seg = DstLI.getSegmentContaining(RegIndex);
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assert(Seg != nullptr && "No segment for defining instruction");
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if (VNInfo *V = DstLI.getVNInfoAt(Seg->end)) {
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if (V->isPHIDef()) {
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CopyMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
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for (unsigned i = CopyMI->getNumOperands(); i != 0; --i) {
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MachineOperand &MO = CopyMI->getOperand(i-1);
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if (MO.isReg() && MO.isUse())
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CopyMI->RemoveOperand(i-1);
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}
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LLVM_DEBUG(dbgs() << "\tReplaced copy of <undef> value with an "
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"implicit def\n");
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return CopyMI;
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}
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}
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// Remove any DstReg segments starting at the instruction.
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LLVM_DEBUG(dbgs() << "\tEliminating copy of <undef> value\n");
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// Remove value or merge with previous one in case of a subregister def.
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if (VNInfo *PrevVNI = DstLI.getVNInfoAt(Idx)) {
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VNInfo *VNI = DstLI.getVNInfoAt(RegIndex);
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@ -1456,7 +1476,7 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
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MO.setIsUndef(true);
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LIS->shrinkToUses(&DstLI);
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return true;
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return CopyMI;
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}
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void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
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@ -1622,9 +1642,14 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
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}
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// Eliminate undefs.
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if (!CP.isPhys() && eliminateUndefCopy(CopyMI)) {
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deleteInstr(CopyMI);
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return false; // Not coalescable.
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if (!CP.isPhys()) {
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// If this is an IMPLICIT_DEF, leave it alone, but don't try to coalesce.
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if (MachineInstr *UndefMI = eliminateUndefCopy(CopyMI)) {
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if (UndefMI->isImplicitDef())
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return false;
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deleteInstr(CopyMI);
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return false; // Not coalescable.
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}
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}
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// Coalesced copies are normally removed immediately, but transformations
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@ -2078,6 +2103,13 @@ class JoinVals {
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/// True once Pruned above has been computed.
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bool PrunedComputed = false;
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/// True if this value is determined to be identical to OtherVNI
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/// (in valuesIdentical). This is used with CR_Erase where the erased
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/// copy is redundant, i.e. the source value is already the same as
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/// the destination. In such cases the subranges need to be updated
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/// properly. See comment at pruneSubRegValues for more info.
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bool Identical = false;
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Val() = default;
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bool isAnalyzed() const { return WriteLanes.any(); }
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@ -2212,17 +2244,17 @@ LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
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std::pair<const VNInfo*, unsigned> JoinVals::followCopyChain(
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const VNInfo *VNI) const {
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unsigned Reg = this->Reg;
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unsigned TrackReg = Reg;
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while (!VNI->isPHIDef()) {
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SlotIndex Def = VNI->def;
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MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
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assert(MI && "No defining instruction");
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if (!MI->isFullCopy())
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return std::make_pair(VNI, Reg);
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return std::make_pair(VNI, TrackReg);
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unsigned SrcReg = MI->getOperand(1).getReg();
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if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
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return std::make_pair(VNI, Reg);
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return std::make_pair(VNI, TrackReg);
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const LiveInterval &LI = LIS->getInterval(SrcReg);
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const VNInfo *ValueIn;
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@ -2243,12 +2275,19 @@ std::pair<const VNInfo*, unsigned> JoinVals::followCopyChain(
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break;
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}
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}
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if (ValueIn == nullptr)
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break;
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if (ValueIn == nullptr) {
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// Reaching an undefined value is legitimate, for example:
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//
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// 1 undef %0.sub1 = ... ;; %0.sub0 == undef
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// 2 %1 = COPY %0 ;; %1 is defined here.
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// 3 %0 = COPY %1 ;; Now %0.sub0 has a definition,
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// ;; but it's equivalent to "undef".
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return std::make_pair(nullptr, SrcReg);
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}
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VNI = ValueIn;
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Reg = SrcReg;
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TrackReg = SrcReg;
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}
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return std::make_pair(VNI, Reg);
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return std::make_pair(VNI, TrackReg);
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}
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bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
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@ -2256,12 +2295,17 @@ bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
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const VNInfo *Orig0;
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unsigned Reg0;
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std::tie(Orig0, Reg0) = followCopyChain(Value0);
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if (Orig0 == Value1)
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if (Orig0 == Value1 && Reg0 == Other.Reg)
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return true;
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const VNInfo *Orig1;
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unsigned Reg1;
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std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
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// If both values are undefined, and the source registers are the same
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// register, the values are identical. Filter out cases where only one
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// value is defined.
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if (Orig0 == nullptr || Orig1 == nullptr)
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return Orig0 == Orig1 && Reg0 == Reg1;
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// The values are equal if they are defined at the same place and use the
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// same register. Note that we cannot compare VNInfos directly as some of
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@ -2437,9 +2481,11 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
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// %other = COPY %ext
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// %this = COPY %ext <-- Erase this copy
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//
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if (DefMI->isFullCopy() && !CP.isPartial()
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&& valuesIdentical(VNI, V.OtherVNI, Other))
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if (DefMI->isFullCopy() && !CP.isPartial() &&
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valuesIdentical(VNI, V.OtherVNI, Other)) {
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V.Identical = true;
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return CR_Erase;
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}
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// If the lanes written by this instruction were all undef in OtherVNI, it is
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// still safe to join the live ranges. This can't be done with a simple value
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@ -2743,19 +2789,62 @@ void JoinVals::pruneValues(JoinVals &Other,
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}
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}
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/// Consider the following situation when coalescing the copy between
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/// %31 and %45 at 800. (The vertical lines represent live range segments.)
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///
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/// Main range Subrange 0004 (sub2)
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/// %31 %45 %31 %45
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/// 544 %45 = COPY %28 + +
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/// | v1 | v1
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/// 560B bb.1: + +
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/// 624 = %45.sub2 | v2 | v2
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/// 800 %31 = COPY %45 + + + +
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/// | v0 | v0
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/// 816 %31.sub1 = ... + |
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/// 880 %30 = COPY %31 | v1 +
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/// 928 %45 = COPY %30 | + +
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/// | | v0 | v0 <--+
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/// 992B ; backedge -> bb.1 | + + |
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/// 1040 = %31.sub0 + |
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/// This value must remain
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/// live-out!
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///
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/// Assuming that %31 is coalesced into %45, the copy at 928 becomes
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/// redundant, since it copies the value from %45 back into it. The
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/// conflict resolution for the main range determines that %45.v0 is
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/// to be erased, which is ok since %31.v1 is identical to it.
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/// The problem happens with the subrange for sub2: it has to be live
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/// on exit from the block, but since 928 was actually a point of
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/// definition of %45.sub2, %45.sub2 was not live immediately prior
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/// to that definition. As a result, when 928 was erased, the value v0
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/// for %45.sub2 was pruned in pruneSubRegValues. Consequently, an
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/// IMPLICIT_DEF was inserted as a "backedge" definition for %45.sub2,
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/// providing an incorrect value to the use at 624.
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///
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/// Since the main-range values %31.v1 and %45.v0 were proved to be
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/// identical, the corresponding values in subranges must also be the
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/// same. A redundant copy is removed because it's not needed, and not
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/// because it copied an undefined value, so any liveness that originated
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/// from that copy cannot disappear. When pruning a value that started
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/// at the removed copy, the corresponding identical value must be
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/// extended to replace it.
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void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) {
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// Look for values being erased.
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bool DidPrune = false;
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for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
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Val &V = Vals[i];
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// We should trigger in all cases in which eraseInstrs() does something.
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// match what eraseInstrs() is doing, print a message so
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if (Vals[i].Resolution != CR_Erase &&
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(Vals[i].Resolution != CR_Keep || !Vals[i].ErasableImplicitDef ||
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!Vals[i].Pruned))
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if (V.Resolution != CR_Erase &&
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(V.Resolution != CR_Keep || !V.ErasableImplicitDef || !V.Pruned))
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continue;
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// Check subranges at the point where the copy will be removed.
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SlotIndex Def = LR.getValNumInfo(i)->def;
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SlotIndex OtherDef;
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if (V.Identical)
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OtherDef = V.OtherVNI->def;
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// Print message so mismatches with eraseInstrs() can be diagnosed.
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LLVM_DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def
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<< '\n');
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@ -2768,10 +2857,18 @@ void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) {
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if (ValueOut != nullptr && Q.valueIn() == nullptr) {
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LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)
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<< " at " << Def << "\n");
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LIS->pruneValue(S, Def, nullptr);
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SmallVector<SlotIndex,8> EndPoints;
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LIS->pruneValue(S, Def, &EndPoints);
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DidPrune = true;
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// Mark value number as unused.
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ValueOut->markUnused();
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if (V.Identical && S.Query(OtherDef).valueOut()) {
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// If V is identical to V.OtherVNI (and S was live at OtherDef),
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// then we can't simply prune V from S. V needs to be replaced
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// with V.OtherVNI.
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LIS->extendToIndices(S, EndPoints);
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}
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continue;
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}
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// If a subrange ends at the copy, then a value was copied but only
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@ -2964,7 +3061,8 @@ void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
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LRange.join(RRange, LHSVals.getAssignments(), RHSVals.getAssignments(),
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NewVNInfo);
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LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << LRange << "\n");
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LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << PrintLaneMask(LaneMask)
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<< ' ' << LRange << "\n");
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if (EndPoints.empty())
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return;
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@ -0,0 +1,116 @@
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# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
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# GCN: {{^body}}
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---
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name: foo
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.2
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%0:sreg_32_xm0 = S_MOV_B32 1
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%1:vgpr_32 = COPY %0
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INLINEASM &"; %1", 1, 327690, def %1, 2147483657, %1(tied-def 3)
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%2:sreg_64 = V_CMP_NE_U32_e64 0, %1, implicit $exec
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undef %3.sub0:sreg_128 = COPY %0
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%3.sub1:sreg_128 = COPY %0
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%3.sub2:sreg_128 = COPY %0
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%4:sreg_128 = COPY %3
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%5:vgpr_32 = V_MOV_B32_e32 -64, implicit $exec
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%6:vreg_128 = COPY %4
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%7:sreg_32_xm0 = S_AND_B32 target-flags(amdgpu-gotprel) 1, %2.sub0, implicit-def dead $scc
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%8:sreg_32_xm0 = S_MOV_B32 0
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%9:vgpr_32 = COPY %5
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%10:vreg_128 = COPY %6
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S_BRANCH %bb.2
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bb.1:
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%11:vgpr_32 = V_OR_B32_e32 %12.sub0, %12.sub1, implicit $exec
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%13:vgpr_32 = V_OR_B32_e32 %11, %12.sub2, implicit $exec
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%14:vgpr_32 = V_AND_B32_e32 1, %13, implicit $exec
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%15:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %14, implicit $exec
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%16:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %15, implicit $exec
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BUFFER_STORE_DWORD_OFFEN_exact %16, undef %17:vgpr_32, undef %18:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into constant-pool, align 1, addrspace 4)
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S_ENDPGM
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bb.2:
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successors: %bb.3, %bb.4
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%19:sreg_64 = V_CMP_EQ_U32_e64 1, %7, implicit $exec
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%20:sreg_64 = COPY $exec, implicit-def $exec
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%21:sreg_64 = S_AND_B64 %20, %19, implicit-def dead $scc
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$exec = S_MOV_B64_term %21
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SI_MASK_BRANCH %bb.4, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.4
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undef %22.sub0:sreg_128 = COPY %8
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%22.sub1:sreg_128 = COPY %8
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%22.sub2:sreg_128 = COPY %8
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%23:sreg_128 = COPY %22
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%24:vreg_128 = COPY %23
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%10:vreg_128 = COPY %24
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bb.4:
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successors: %bb.5
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$exec = S_OR_B64 $exec, %20, implicit-def $scc
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bb.5:
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successors: %bb.7, %bb.6
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S_CBRANCH_SCC0 %bb.7, implicit undef $scc
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bb.6:
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successors: %bb.9
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%12:vreg_128 = COPY %10
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S_BRANCH %bb.9
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bb.7:
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successors: %bb.8, %bb.10
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%25:vgpr_32 = V_AND_B32_e32 target-flags(amdgpu-gotprel32-hi) 1, %10.sub2, implicit $exec
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%26:sreg_64 = V_CMP_EQ_U32_e64 1, %25, implicit $exec
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%27:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%28:vreg_1 = COPY %27
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%29:sreg_64 = COPY $exec, implicit-def $exec
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%30:sreg_64 = S_AND_B64 %29, %26, implicit-def dead $scc
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$exec = S_MOV_B64_term %30
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SI_MASK_BRANCH %bb.10, implicit $exec
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S_BRANCH %bb.8
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bb.8:
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successors: %bb.10
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%31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
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%34:sreg_64_xexec = V_CMP_NE_U32_e64 0, %31, implicit $exec
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%35:vgpr_32 = V_CNDMASK_B32_e64 0, -1, %34, implicit $exec
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%28:vreg_1 = COPY %35
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S_BRANCH %bb.10
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bb.9:
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successors: %bb.11
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S_BRANCH %bb.11
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bb.10:
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successors: %bb.9
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$exec = S_OR_B64 $exec, %29, implicit-def $scc
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%36:vreg_1 = COPY %28
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%37:sreg_64_xexec = V_CMP_NE_U32_e64 0, %36, implicit $exec
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%38:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %37, implicit $exec
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%39:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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undef %40.sub0:vreg_128 = COPY %39
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%40.sub1:vreg_128 = COPY %39
|
||||
%40.sub2:vreg_128 = COPY %38
|
||||
%41:vreg_128 = COPY %40
|
||||
%12:vreg_128 = COPY %41
|
||||
S_BRANCH %bb.9
|
||||
|
||||
bb.11:
|
||||
successors: %bb.2, %bb.1
|
||||
%42:vgpr_32 = V_ADD_I32_e32 32, %9, implicit-def dead $vcc, implicit $exec
|
||||
V_CMP_EQ_U32_e32 0, %42, implicit-def $vcc, implicit $exec
|
||||
%43:vgpr_32 = COPY %42
|
||||
$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
|
||||
%44:vreg_128 = COPY %12
|
||||
%9:vgpr_32 = COPY %43
|
||||
%10:vreg_128 = COPY %44
|
||||
S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
|
||||
S_BRANCH %bb.2
|
||||
...
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
# RUN: llc -mtriple=amdgcn--amdpal -run-pass=simple-register-coalescing -o - %s | FileCheck %s
|
||||
|
||||
# Check that this doesn't crash. Check for some legitimate output.
|
||||
# CHECK: S_CBRANCH_SCC1
|
||||
|
||||
---
|
||||
name: fred
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1, %bb.2
|
||||
liveins: $sgpr4
|
||||
undef %0.sub2:sreg_128 = COPY $sgpr4
|
||||
%3 = IMPLICIT_DEF
|
||||
S_CBRANCH_SCC1 %bb.2, implicit undef $scc
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
%0.sub0:sreg_128 = COPY %0.sub2
|
||||
%0.sub1:sreg_128 = COPY %0.sub2
|
||||
%1:sreg_128 = COPY %0
|
||||
%2:sreg_128 = COPY %0
|
||||
%0:sreg_128 = COPY %2
|
||||
%3:sreg_128 = COPY %1
|
||||
|
||||
bb.2:
|
||||
$sgpr1 = COPY %3
|
||||
$sgpr2 = COPY %0.sub2
|
||||
...
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
# With one version of the D48102 fix, this test failed with
|
||||
# Assertion failed: (ValNo && "CopyMI input register not live"), function reMaterializeTrivialDef, file ../lib/CodeGen/RegisterCoalescer.cpp, line 1107.
|
||||
|
||||
# GCN: {{^body}}
|
||||
|
||||
--- |
|
||||
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
|
||||
target triple = "amdgcn--amdpal"
|
||||
|
||||
define amdgpu_cs void @_amdgpu_cs_main(<3 x i32>) #0 {
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="gfx803" }
|
||||
...
|
||||
|
||||
---
|
||||
name: _amdgpu_cs_main
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
%0:vgpr_32 = V_MUL_F32_e32 0, undef %1:vgpr_32, implicit $exec
|
||||
%2:vgpr_32 = V_CVT_U32_F32_e32 killed %0, implicit $exec
|
||||
%3:vgpr_32 = V_CVT_F32_I32_e32 killed %2, implicit $exec
|
||||
%4:vgpr_32 = V_CVT_U32_F32_e32 killed %3, implicit $exec
|
||||
%5:vgpr_32 = V_LSHRREV_B32_e32 4, killed %4, implicit $exec
|
||||
S_CBRANCH_SCC0 %bb.2, implicit undef $scc
|
||||
|
||||
bb.1:
|
||||
successors: %bb.5(0x80000000)
|
||||
undef %6.sub1:vreg_128 = COPY killed %5
|
||||
%7:vreg_128 = COPY killed %6
|
||||
S_BRANCH %bb.5
|
||||
|
||||
bb.2:
|
||||
successors: %bb.3(0x40000000), %bb.4(0x40000000)
|
||||
S_CBRANCH_SCC0 %bb.4, implicit undef $scc
|
||||
|
||||
bb.3:
|
||||
successors: %bb.5(0x80000000)
|
||||
%8:sreg_32_xm0 = S_MOV_B32 0
|
||||
undef %9.sub0:sreg_128 = COPY %8
|
||||
%9.sub1:sreg_128 = COPY %8
|
||||
%9.sub2:sreg_128 = COPY %8
|
||||
%9.sub3:sreg_128 = COPY killed %8
|
||||
%10:vreg_128 = COPY killed %9
|
||||
%7:vreg_128 = COPY killed %10
|
||||
S_BRANCH %bb.5
|
||||
|
||||
bb.4:
|
||||
successors: %bb.5(0x80000000)
|
||||
%11:sreg_32_xm0 = S_MOV_B32 0
|
||||
undef %12.sub0:sreg_128 = COPY %11
|
||||
%12.sub1:sreg_128 = COPY %11
|
||||
%12.sub2:sreg_128 = COPY %11
|
||||
%12.sub3:sreg_128 = COPY killed %11
|
||||
%13:sreg_128 = COPY killed %12
|
||||
%14:vreg_128 = COPY killed %13
|
||||
%7:vreg_128 = COPY killed %14
|
||||
|
||||
bb.5:
|
||||
successors: %bb.8(0x40000000), %bb.6(0x40000000)
|
||||
%15:vreg_128 = COPY killed %7
|
||||
S_CBRANCH_SCC0 %bb.8, implicit undef $scc
|
||||
|
||||
bb.6:
|
||||
successors: %bb.7(0x80000000)
|
||||
%16:vreg_128 = COPY killed %15
|
||||
|
||||
bb.7:
|
||||
successors: %bb.14(0x80000000)
|
||||
%17:vreg_128 = COPY killed %16
|
||||
S_BRANCH %bb.14
|
||||
|
||||
bb.8:
|
||||
successors: %bb.9(0x40000000), %bb.11(0x40000000)
|
||||
%18:vgpr_32 = V_MUL_LO_I32 %15.sub1, target-flags(amdgpu-gotprel32-lo) 7, implicit $exec
|
||||
S_CBRANCH_SCC1 %bb.11, implicit undef $scc
|
||||
S_BRANCH %bb.9
|
||||
|
||||
bb.9:
|
||||
successors: %bb.10(0x80000000)
|
||||
%19:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %18, undef %20:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
|
||||
%21:sreg_64 = V_CMP_NE_U32_e64 target-flags(amdgpu-gotprel) 0, killed %19.sub0, implicit $exec
|
||||
%22:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%23:sreg_64 = S_AND_B64 %22, %21, implicit-def dead $scc
|
||||
$exec = S_MOV_B64_term killed %23
|
||||
|
||||
bb.10:
|
||||
successors: %bb.12(0x80000000)
|
||||
$exec = S_OR_B64 $exec, killed %22, implicit-def $scc
|
||||
S_BRANCH %bb.12
|
||||
|
||||
bb.11:
|
||||
successors: %bb.13(0x80000000)
|
||||
%24:vreg_128 = COPY killed %15
|
||||
%24.sub0:vreg_128 = COPY undef %18
|
||||
S_BRANCH %bb.13
|
||||
|
||||
bb.12:
|
||||
successors: %bb.11(0x80000000)
|
||||
S_BRANCH %bb.11
|
||||
|
||||
bb.13:
|
||||
successors: %bb.7(0x80000000)
|
||||
%16:vreg_128 = COPY killed %24
|
||||
S_BRANCH %bb.7
|
||||
|
||||
bb.14:
|
||||
successors: %bb.15(0x80000000)
|
||||
S_CBRANCH_SCC1 %bb.15, implicit undef $scc
|
||||
S_BRANCH %bb.15
|
||||
|
||||
bb.15:
|
||||
undef %25.sub2:vreg_128 = COPY killed %17.sub2
|
||||
%26:sreg_32_xm0 = S_MOV_B32 0
|
||||
undef %27.sub0:sreg_256 = COPY %26
|
||||
%27.sub1:sreg_256 = COPY %26
|
||||
%27.sub2:sreg_256 = COPY %26
|
||||
%27.sub3:sreg_256 = COPY %26
|
||||
%27.sub4:sreg_256 = COPY %26
|
||||
%27.sub5:sreg_256 = COPY %26
|
||||
%27.sub6:sreg_256 = COPY %26
|
||||
%27.sub7:sreg_256 = COPY killed %26
|
||||
%28:vgpr_32 = IMAGE_LOAD_V1_V4 killed %25, killed %27, 2, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
|
||||
%29:vgpr_32 = V_ADD_F32_e32 0, killed %28, implicit $exec
|
||||
$m0 = S_MOV_B32 -1
|
||||
DS_WRITE_B32 undef %30:vgpr_32, killed %29, 0, 0, implicit $m0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`, addrspace 3)
|
||||
S_ENDPGM
|
||||
...
|
||||
|
|
@ -0,0 +1,268 @@
|
|||
# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
# With one version of the D48102 fix, this test failed with
|
||||
# Assertion failed: (Id != S.end() && T != S.end() && T->valno == Id->valno), function pruneSubRegValues, file ../lib/CodeGen/RegisterCoalescer.cpp, line 2875.
|
||||
|
||||
# GCN: {{^body}}
|
||||
|
||||
--- |
|
||||
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
|
||||
target triple = "amdgcn--amdpal"
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define amdgpu_ps void @_amdgpu_ps_main(float %arg) #0 {
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "InitialPSInputAddr"="3842" "target-cpu"="gfx803" }
|
||||
...
|
||||
|
||||
---
|
||||
name: _amdgpu_ps_main
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
%0:sreg_64 = COPY $exec
|
||||
%1:sgpr_32 = S_MOV_B32 0
|
||||
undef %2.sub0:sreg_128 = COPY %1
|
||||
%2.sub1:sreg_128 = COPY %1
|
||||
%2.sub2:sreg_128 = COPY %1
|
||||
%2.sub3:sreg_128 = COPY %1
|
||||
$exec = S_WQM_B64 $exec, implicit-def dead $scc
|
||||
S_CBRANCH_SCC0 %bb.2, implicit undef $scc
|
||||
|
||||
bb.1:
|
||||
successors: %bb.3(0x80000000)
|
||||
%3:sreg_128 = COPY killed %2
|
||||
%4:vreg_128 = COPY killed %3
|
||||
%5:vreg_128 = COPY killed %4
|
||||
S_BRANCH %bb.3
|
||||
|
||||
bb.2:
|
||||
successors: %bb.4(0x80000000)
|
||||
%6:vgpr_32 = V_MUL_F32_e32 1031798784, undef %7:vgpr_32, implicit $exec
|
||||
%8:vgpr_32 = V_FLOOR_F32_e32 killed %6, implicit $exec
|
||||
%9:vgpr_32 = V_ADD_F32_e32 0, killed %8, implicit $exec
|
||||
%10:vgpr_32 = V_CVT_U32_F32_e32 killed %9, implicit $exec
|
||||
%11:vgpr_32 = V_LSHLREV_B32_e32 1, killed %10, implicit $exec
|
||||
%12:sreg_64 = S_MOV_B64 0
|
||||
%13:sreg_128 = COPY killed %2
|
||||
%14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%15:vreg_128 = COPY killed %13
|
||||
%16:sreg_64 = COPY killed %12
|
||||
%17:vreg_128 = IMPLICIT_DEF
|
||||
%18:vgpr_32 = COPY killed %14
|
||||
%19:vreg_128 = COPY killed %15
|
||||
S_BRANCH %bb.4
|
||||
|
||||
bb.3:
|
||||
successors: %bb.17(0x80000000)
|
||||
%20:vreg_128 = COPY killed %5
|
||||
S_BRANCH %bb.17
|
||||
|
||||
bb.4:
|
||||
successors: %bb.8(0x40000000), %bb.9(0x40000000)
|
||||
%21:vreg_128 = COPY killed %19
|
||||
%22:vgpr_32 = COPY killed %18
|
||||
%23:vreg_128 = COPY killed %17
|
||||
%24:sreg_64 = COPY killed %16
|
||||
%25:vgpr_32 = V_OR_B32_e32 %22, %11, implicit $exec
|
||||
%26:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %25, undef %27:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
|
||||
%28:vgpr_32 = V_LSHRREV_B32_e32 30, killed %26.sub0, implicit $exec
|
||||
%29:vreg_128 = COPY killed %21
|
||||
%29.sub0:vreg_128 = COPY %1
|
||||
%30:sreg_64 = V_CMP_NE_U32_e64 0, %28, implicit $exec
|
||||
%31:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %28, implicit $exec
|
||||
dead %32:vgpr_32 = V_CNDMASK_B32_e64 0, -1, killed %31, implicit $exec
|
||||
%33:vreg_128 = COPY %29
|
||||
%33.sub1:vreg_128 = COPY undef %32
|
||||
%34:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
|
||||
%35:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%36:sreg_64 = COPY %24
|
||||
%37:vreg_128 = COPY %23
|
||||
%38:vreg_128 = IMPLICIT_DEF
|
||||
%39:vreg_128 = IMPLICIT_DEF
|
||||
%40:vgpr_32 = IMPLICIT_DEF
|
||||
%41:vreg_1 = COPY killed %35
|
||||
%42:vreg_1 = COPY killed %34
|
||||
%43:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%44:sreg_64 = S_AND_B64 %43, %30, implicit-def dead $scc
|
||||
%45:sreg_64 = S_XOR_B64 %44, %43, implicit-def dead $scc
|
||||
$exec = S_MOV_B64_term killed %44
|
||||
SI_MASK_BRANCH %bb.9, implicit $exec
|
||||
S_BRANCH %bb.8
|
||||
|
||||
bb.5:
|
||||
successors: %bb.9(0x80000000)
|
||||
$exec = S_OR_B64 $exec, %46, implicit-def $scc
|
||||
%47:vreg_1 = COPY killed %48
|
||||
%49:vgpr_32 = COPY killed %50
|
||||
%51:vreg_128 = COPY killed %52
|
||||
%53:vreg_128 = COPY killed %54
|
||||
%55:sreg_64 = COPY killed %56
|
||||
%57:sreg_64 = S_AND_B64 $exec, %46, implicit-def $scc
|
||||
%57:sreg_64 = S_OR_B64 %57, killed %55, implicit-def $scc
|
||||
%58:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%36:sreg_64 = COPY killed %57
|
||||
%37:vreg_128 = COPY killed %53
|
||||
%38:vreg_128 = COPY killed %59
|
||||
%39:vreg_128 = COPY killed %51
|
||||
%40:vgpr_32 = COPY killed %49
|
||||
%41:vreg_1 = COPY killed %47
|
||||
%42:vreg_1 = COPY killed %58
|
||||
S_BRANCH %bb.9
|
||||
|
||||
bb.6:
|
||||
successors: %bb.7(0x40000000), %bb.13(0x40000000)
|
||||
$exec = S_OR_B64 $exec, killed %60, implicit-def $scc
|
||||
%61:sreg_64 = V_CMP_NE_U32_e64 0, killed %62, implicit $exec
|
||||
%63:vreg_128 = COPY killed %64
|
||||
%65:vreg_1 = COPY killed %66
|
||||
%67:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%68:sreg_64 = S_AND_B64 %67, %61, implicit-def dead $scc
|
||||
$exec = S_MOV_B64_term killed %68
|
||||
SI_MASK_BRANCH %bb.13, implicit $exec
|
||||
S_BRANCH %bb.7
|
||||
|
||||
bb.7:
|
||||
successors: %bb.13(0x80000000)
|
||||
%69:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
|
||||
%70:vreg_128 = COPY killed %33
|
||||
%63:vreg_128 = COPY killed %70
|
||||
%65:vreg_1 = COPY killed %69
|
||||
S_BRANCH %bb.13
|
||||
|
||||
bb.8:
|
||||
successors: %bb.10(0x80000000)
|
||||
%71:sreg_64 = S_MOV_B64 0
|
||||
%72:vreg_128 = COPY %33
|
||||
%73:sreg_64 = COPY killed %71
|
||||
%74:vreg_128 = COPY killed %72
|
||||
%75:vreg_128 = COPY killed %29
|
||||
S_BRANCH %bb.10
|
||||
|
||||
bb.9:
|
||||
successors: %bb.6(0x04000000), %bb.4(0x7c000000)
|
||||
$exec = S_OR_B64 $exec, %45, implicit-def $scc
|
||||
%62:vreg_1 = COPY killed %42
|
||||
%66:vreg_1 = COPY killed %41
|
||||
%76:vgpr_32 = COPY killed %40
|
||||
%77:vreg_128 = COPY killed %39
|
||||
%64:vreg_128 = COPY killed %38
|
||||
%78:vreg_128 = COPY killed %37
|
||||
%79:sreg_64 = COPY killed %36
|
||||
%60:sreg_64 = S_AND_B64 $exec, %45, implicit-def $scc
|
||||
%60:sreg_64 = S_OR_B64 %60, killed %79, implicit-def $scc
|
||||
%80:vreg_128 = COPY %78
|
||||
%16:sreg_64 = COPY %60
|
||||
%17:vreg_128 = COPY killed %80
|
||||
%18:vgpr_32 = COPY killed %76
|
||||
%19:vreg_128 = COPY killed %77
|
||||
$exec = S_ANDN2_B64_term $exec, %60
|
||||
S_CBRANCH_EXECNZ %bb.4, implicit $exec
|
||||
S_BRANCH %bb.6
|
||||
|
||||
bb.10:
|
||||
successors: %bb.11(0x80000000)
|
||||
%81:vreg_128 = COPY killed %75
|
||||
%82:vreg_128 = COPY killed %74
|
||||
%83:sreg_64 = COPY killed %73
|
||||
|
||||
bb.11:
|
||||
successors: %bb.12(0x04000000), %bb.10(0x7c000000)
|
||||
undef %59.sub0:vreg_128 = COPY %81.sub0
|
||||
%59.sub2:vreg_128 = COPY %82.sub2
|
||||
%59.sub3:vreg_128 = COPY killed %82.sub3
|
||||
%84:sreg_64 = V_CMP_GE_U32_e64 killed %81.sub0, %28, implicit $exec
|
||||
%85:sreg_64 = S_OR_B64 killed %84, killed %83, implicit-def $scc
|
||||
%86:vreg_128 = COPY %59
|
||||
%73:sreg_64 = COPY %85
|
||||
%74:vreg_128 = COPY %59
|
||||
%75:vreg_128 = COPY killed %86
|
||||
$exec = S_ANDN2_B64_term $exec, %85
|
||||
S_CBRANCH_EXECNZ %bb.10, implicit $exec
|
||||
S_BRANCH %bb.12
|
||||
|
||||
bb.12:
|
||||
successors: %bb.15(0x40000000), %bb.5(0x40000000)
|
||||
$exec = S_OR_B64 $exec, killed %85, implicit-def $scc
|
||||
%87:sreg_64 = V_CMP_LT_U32_e64 11, killed %28, implicit $exec
|
||||
%88:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
|
||||
%56:sreg_64 = COPY %24
|
||||
%54:vreg_128 = COPY killed %23
|
||||
%52:vreg_128 = IMPLICIT_DEF
|
||||
%50:vgpr_32 = IMPLICIT_DEF
|
||||
%48:vreg_1 = COPY killed %88
|
||||
%89:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%90:sreg_64 = S_AND_B64 %89, %87, implicit-def dead $scc
|
||||
%46:sreg_64 = S_XOR_B64 %90, %89, implicit-def dead $scc
|
||||
$exec = S_MOV_B64_term killed %90
|
||||
SI_MASK_BRANCH %bb.5, implicit $exec
|
||||
S_BRANCH %bb.15
|
||||
|
||||
bb.13:
|
||||
successors: %bb.14(0x40000000), %bb.16(0x40000000)
|
||||
$exec = S_OR_B64 $exec, killed %67, implicit-def $scc
|
||||
%91:vreg_1 = COPY killed %65
|
||||
%92:vreg_128 = COPY killed %63
|
||||
%93:sreg_64 = V_CMP_NE_U32_e64 0, killed %91, implicit $exec
|
||||
%94:vreg_128 = COPY killed %78
|
||||
%95:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%96:sreg_64 = S_AND_B64 %95, %93, implicit-def dead $scc
|
||||
$exec = S_MOV_B64_term killed %96
|
||||
SI_MASK_BRANCH %bb.16, implicit $exec
|
||||
S_BRANCH %bb.14
|
||||
|
||||
bb.14:
|
||||
successors: %bb.16(0x80000000)
|
||||
%97:vreg_128 = COPY killed %92
|
||||
%94:vreg_128 = COPY killed %97
|
||||
S_BRANCH %bb.16
|
||||
|
||||
bb.15:
|
||||
successors: %bb.5(0x80000000)
|
||||
%98:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%99:sreg_64 = V_CMP_NE_U32_e64 0, killed %22, implicit $exec
|
||||
%100:sreg_64 = S_OR_B64 killed %99, killed %24, implicit-def $scc
|
||||
%101:vreg_128 = COPY %59
|
||||
%102:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
|
||||
%56:sreg_64 = COPY killed %100
|
||||
%54:vreg_128 = COPY killed %101
|
||||
%52:vreg_128 = COPY %59
|
||||
%50:vgpr_32 = COPY killed %102
|
||||
%48:vreg_1 = COPY killed %98
|
||||
S_BRANCH %bb.5
|
||||
|
||||
bb.16:
|
||||
successors: %bb.3(0x80000000)
|
||||
$exec = S_OR_B64 $exec, killed %95, implicit-def $scc
|
||||
%103:vreg_128 = COPY killed %94
|
||||
%104:vreg_128 = COPY killed %103
|
||||
%5:vreg_128 = COPY killed %104
|
||||
S_BRANCH %bb.3
|
||||
|
||||
bb.17:
|
||||
%105:vgpr_32 = V_ADD_F32_e32 target-flags(amdgpu-rel32-lo) 0, %20.sub3, implicit $exec
|
||||
%106:vgpr_32 = V_ADD_F32_e32 target-flags(amdgpu-gotprel32-hi) 0, killed %20.sub2, implicit $exec
|
||||
undef %107.sub0:vreg_64 = COPY killed %106
|
||||
%107.sub1:vreg_64 = COPY killed %105
|
||||
$exec = S_AND_B64 $exec, killed %0, implicit-def dead $scc
|
||||
%108:sreg_32_xm0 = S_MOV_B32 0
|
||||
undef %109.sub0:sreg_256 = COPY %108
|
||||
%109.sub1:sreg_256 = COPY %108
|
||||
%109.sub2:sreg_256 = COPY %108
|
||||
%109.sub3:sreg_256 = COPY %108
|
||||
%109.sub4:sreg_256 = COPY %108
|
||||
%109.sub5:sreg_256 = COPY %108
|
||||
%109.sub6:sreg_256 = COPY %108
|
||||
%109.sub7:sreg_256 = COPY killed %108
|
||||
%110:vgpr_32 = IMAGE_SAMPLE_V1_V2 killed %107, killed %109, undef %111:sreg_128, 8, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
|
||||
%112:vgpr_32 = V_MUL_F32_e32 0, killed %110, implicit $exec
|
||||
%113:vgpr_32 = V_MUL_F32_e32 0, killed %112, implicit $exec
|
||||
%114:vgpr_32 = V_MAD_F32 0, killed %113, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%115:vgpr_32 = V_MAX_F32_e32 0, killed %114, implicit $exec
|
||||
%116:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, killed %115, 0, 1065353216, 0, implicit $exec
|
||||
EXP 0, undef %117:vgpr_32, killed %116, undef %118:vgpr_32, undef %119:vgpr_32, -1, -1, 15, implicit $exec
|
||||
S_ENDPGM
|
||||
...
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
|
||||
#
|
||||
# See bug http://llvm.org/PR33152 for details of the bug this test is checking
|
||||
# for.
|
||||
# This test will provoke a subrange join during simple register
|
||||
# coalescing. Withough a fix for PR33152 this causes an unreachable in SubRange
|
||||
# Join
|
||||
#
|
||||
# The lines where the problem exhibits are the last 2 copy instructions in the
|
||||
# BB (bb.25)
|
||||
#
|
||||
# GCN-LABEL: bb.6:
|
||||
# GCN: successors: %bb.7(0x{{[0-9]+}}), %bb.18(0x{{[0-9]+}})
|
||||
# GCN: %{{[0-9]+}}:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %{{[0-9]+}}, 0, 0, 0, 0, 0, implicit $exec
|
||||
#
|
||||
|
||||
--- |
|
||||
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
|
||||
target triple = "amdgcn--amdpal"
|
||||
|
||||
define amdgpu_ps void @main() #0 {
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "target-cpu"="gfx803" }
|
||||
...
|
||||
|
||||
---
|
||||
name: main
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
S_CBRANCH_SCC0 %bb.2, implicit undef $scc
|
||||
|
||||
bb.1:
|
||||
successors: %bb.9(0x80000000)
|
||||
%0:vreg_128 = IMPLICIT_DEF
|
||||
S_BRANCH %bb.9
|
||||
|
||||
bb.2:
|
||||
successors: %bb.4(0x40000000), %bb.3(0x40000000)
|
||||
S_CBRANCH_SCC0 %bb.4, implicit undef $scc
|
||||
|
||||
bb.3:
|
||||
successors: %bb.5(0x80000000)
|
||||
%1:vreg_128 = IMPLICIT_DEF
|
||||
S_BRANCH %bb.5
|
||||
|
||||
bb.4:
|
||||
successors: %bb.6(0x80000000)
|
||||
%2:sreg_64 = S_MOV_B64 0
|
||||
%3:sreg_32_xm0 = S_MOV_B32 61440
|
||||
%4:sreg_32_xm0 = S_MOV_B32 -1
|
||||
%5:sreg_64 = COPY killed %2
|
||||
%6:vreg_128 = IMPLICIT_DEF
|
||||
S_BRANCH %bb.6
|
||||
|
||||
bb.5:
|
||||
successors: %bb.9(0x80000000)
|
||||
%7:vreg_128 = COPY killed %1
|
||||
%8:vreg_128 = COPY killed %7
|
||||
%0:vreg_128 = COPY killed %8
|
||||
S_BRANCH %bb.9
|
||||
|
||||
bb.6:
|
||||
successors: %bb.7(0x40000000), %bb.18(0x40000000)
|
||||
%9:vreg_128 = COPY killed %6
|
||||
%10:sreg_64 = COPY killed %5
|
||||
undef %11.sub2:sreg_128 = COPY %4
|
||||
%11.sub3:sreg_128 = COPY %3
|
||||
%12:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET killed %11, 0, 0, 0, 0, 0, implicit $exec
|
||||
undef %13.sub1:vreg_128 = COPY %9.sub1
|
||||
%13.sub2:vreg_128 = COPY %9.sub2
|
||||
%14:sreg_64 = V_CMP_GT_F32_e64 0, target-flags(amdgpu-rel32-lo) 0, 0, killed %12.sub3, 0, implicit $exec
|
||||
%15:vgpr_32 = V_ADD_F32_e32 1065353216, undef %16:vgpr_32, implicit $exec
|
||||
%17:sreg_64 = V_CMP_GT_F32_e64 0, 0, 0, killed %15, 0, implicit $exec
|
||||
%18:sreg_64 = S_AND_B64 killed %17, killed %14, implicit-def dead $scc
|
||||
%19:sreg_64 = COPY %10
|
||||
%20:vreg_128 = COPY %13
|
||||
%21:vreg_128 = IMPLICIT_DEF
|
||||
%22:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%23:sreg_64 = S_AND_B64 %22, %18, implicit-def dead $scc
|
||||
%24:sreg_64 = S_XOR_B64 %23, %22, implicit-def dead $scc
|
||||
$exec = S_MOV_B64_term killed %23
|
||||
SI_MASK_BRANCH %bb.7, implicit $exec
|
||||
S_BRANCH %bb.18
|
||||
|
||||
bb.7:
|
||||
successors: %bb.6(0x40000000), %bb.8(0x40000000)
|
||||
$exec = S_OR_B64 $exec, %24, implicit-def $scc
|
||||
%25:vreg_128 = COPY killed %21
|
||||
%26:vreg_128 = COPY killed %20
|
||||
%27:sreg_64 = COPY killed %19
|
||||
%28:sreg_64 = S_OR_B64 %24, killed %27, implicit-def dead $scc
|
||||
%5:sreg_64 = COPY %28
|
||||
%6:vreg_128 = COPY killed %25
|
||||
$exec = S_ANDN2_B64_term $exec, %28
|
||||
S_CBRANCH_EXECNZ %bb.6, implicit $exec
|
||||
S_BRANCH %bb.8
|
||||
|
||||
bb.8:
|
||||
successors: %bb.5(0x80000000)
|
||||
$exec = S_OR_B64 $exec, killed %28, implicit-def $scc
|
||||
%29:vreg_128 = COPY killed %26
|
||||
%1:vreg_128 = COPY killed %29
|
||||
S_BRANCH %bb.5
|
||||
|
||||
bb.9:
|
||||
successors: %bb.10(0x80000000)
|
||||
%30:vreg_128 = COPY killed %0
|
||||
S_BRANCH %bb.10
|
||||
|
||||
bb.10:
|
||||
successors: %bb.12(0x40000000), %bb.11(0x40000000)
|
||||
S_CBRANCH_SCC0 %bb.12, implicit undef $scc
|
||||
|
||||
bb.11:
|
||||
successors: %bb.14(0x80000000)
|
||||
%31:vreg_128 = IMPLICIT_DEF
|
||||
S_BRANCH %bb.14
|
||||
|
||||
bb.12:
|
||||
successors: %bb.13(0x80000000)
|
||||
S_CBRANCH_SCC1 %bb.13, implicit undef $scc
|
||||
S_BRANCH %bb.13
|
||||
|
||||
bb.13:
|
||||
successors: %bb.14(0x80000000)
|
||||
%32:vgpr_32 = V_MUL_F32_e32 undef %33:vgpr_32, killed %30.sub1, implicit $exec
|
||||
%34:vgpr_32 = V_MUL_F32_e32 undef %35:vgpr_32, killed %32, implicit $exec
|
||||
undef %36.sub0:vreg_128 = COPY %34
|
||||
%31:vreg_128 = COPY killed %36
|
||||
|
||||
bb.14:
|
||||
successors: %bb.16(0x40000000), %bb.15(0x40000000)
|
||||
%37:vreg_128 = COPY killed %31
|
||||
S_CBRANCH_SCC0 %bb.16, implicit undef $scc
|
||||
|
||||
bb.15:
|
||||
successors: %bb.17(0x80000000)
|
||||
%38:vreg_128 = IMPLICIT_DEF
|
||||
S_BRANCH %bb.17
|
||||
|
||||
bb.16:
|
||||
successors: %bb.17(0x80000000)
|
||||
%39:vgpr_32 = V_FMA_F32 0, undef %40:vgpr_32, 0, killed %37.sub0, 0, undef %41:vgpr_32, 0, 0, implicit $exec
|
||||
%42:vgpr_32 = V_FMA_F32 0, undef %43:vgpr_32, 0, undef %44:vgpr_32, 0, killed %39, 0, 0, implicit $exec
|
||||
%45:vgpr_32 = V_FMA_F32 0, undef %46:vgpr_32, 0, undef %47:vgpr_32, 0, killed %42, 0, 0, implicit $exec
|
||||
dead %48:vgpr_32 = V_MUL_F32_e32 undef %49:vgpr_32, killed %45, implicit $exec
|
||||
%50:vgpr_32 = V_MUL_F32_e32 undef %51:vgpr_32, undef %52:vgpr_32, implicit $exec
|
||||
undef %53.sub1:vreg_128 = COPY %50
|
||||
%38:vreg_128 = COPY killed %53
|
||||
|
||||
bb.17:
|
||||
%54:vreg_128 = COPY killed %38
|
||||
%55:vgpr_32 = V_FMA_F32 0, killed %54.sub1, 0, target-flags(amdgpu-gotprel32-lo) 1056964608, 0, 1056964608, 0, 0, implicit $exec
|
||||
EXP 1, undef %56:vgpr_32, killed %55, undef %57:vgpr_32, undef %58:vgpr_32, -1, 0, 15, implicit $exec
|
||||
S_ENDPGM
|
||||
|
||||
bb.18:
|
||||
successors: %bb.7(0x80000000)
|
||||
dead %59:vgpr_32 = V_FMA_F32 0, killed %9.sub2, 0, undef %60:vgpr_32, 0, undef %61:vgpr_32, 0, 0, implicit $exec
|
||||
dead %62:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %63:vgpr_32, undef %64:sreg_128, undef %65:sreg_32, 0, 0, 0, 0, implicit $exec
|
||||
undef %66.sub1:vreg_128 = COPY %13.sub1
|
||||
%66.sub2:vreg_128 = COPY %13.sub2
|
||||
%67:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, undef %68:vgpr_32, 0, implicit $exec
|
||||
%69:vgpr_32 = V_ADD_F32_e32 1065353216, undef %70:vgpr_32, implicit $exec
|
||||
%71:vgpr_32 = V_ADD_F32_e32 1065353216, killed %69, implicit $exec
|
||||
%72:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, killed %71, 0, implicit $exec
|
||||
%73:sreg_64 = S_OR_B64 killed %72, killed %67, implicit-def dead $scc
|
||||
%74:sreg_64 = S_OR_B64 killed %73, killed %10, implicit-def dead $scc
|
||||
%19:sreg_64 = COPY killed %74
|
||||
%20:vreg_128 = COPY %66
|
||||
%21:vreg_128 = COPY killed %66
|
||||
S_BRANCH %bb.7
|
||||
...
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
# With one version of the D48102 fix, this test failed with
|
||||
# Assertion failed: (Id != S.end() && T != S.end() && T->valno == Id->valno), function pruneSubRegValues, file ../lib/CodeGen/RegisterCoalescer.cpp, line 2870.
|
||||
|
||||
# GCN: {{^body}}
|
||||
|
||||
--- |
|
||||
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
|
||||
target triple = "amdgcn--amdpal"
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define amdgpu_cs void @_amdgpu_cs_main(<3 x i32> %arg) #0 {
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="gfx803" }
|
||||
...
|
||||
|
||||
---
|
||||
name: _amdgpu_cs_main
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$vgpr0', virtual-reg: '%0' }
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1(0x40000000), %bb.21(0x40000000)
|
||||
liveins: $vgpr0, $vgpr1, $vgpr2
|
||||
%0:vgpr_32 = COPY killed $vgpr0
|
||||
S_CBRANCH_SCC1 %bb.21, implicit undef $scc
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2(0x40000000), %bb.17(0x40000000)
|
||||
S_CBRANCH_SCC1 %bb.17, implicit undef $scc
|
||||
|
||||
bb.2:
|
||||
successors: %bb.4(0x40000000), %bb.3(0x40000000)
|
||||
%1:sreg_32_xm0 = S_MOV_B32 0
|
||||
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
undef %3.sub0:vreg_128 = COPY killed %0
|
||||
%3.sub2:vreg_128 = COPY killed %2
|
||||
undef %4.sub0:sreg_256 = COPY %1
|
||||
%4.sub1:sreg_256 = COPY %1
|
||||
%4.sub2:sreg_256 = COPY %1
|
||||
%4.sub3:sreg_256 = COPY %1
|
||||
%4.sub4:sreg_256 = COPY %1
|
||||
%4.sub5:sreg_256 = COPY %1
|
||||
%4.sub6:sreg_256 = COPY %1
|
||||
%4.sub7:sreg_256 = COPY killed %1
|
||||
%5:vgpr_32 = IMAGE_LOAD_V1_V4 killed %3, killed %4, 1, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
|
||||
%6:vgpr_32 = V_MAD_F32 0, killed %5, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%7:vgpr_32 = V_RCP_F32_e32 killed %6, implicit $exec
|
||||
%8:vgpr_32 = V_MUL_F32_e32 0, killed %7, implicit $exec
|
||||
%9:vgpr_32 = V_MAD_F32 0, killed %8, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
dead %10:vgpr_32 = V_MAC_F32_e32 undef %11:vgpr_32, undef %12:vgpr_32, undef %10, implicit $exec
|
||||
undef %13.sub0:vreg_128 = COPY %9
|
||||
%14:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
|
||||
S_CBRANCH_SCC0 %bb.4, implicit undef $scc
|
||||
|
||||
bb.3:
|
||||
successors: %bb.6(0x80000000)
|
||||
%15:vreg_128 = IMPLICIT_DEF
|
||||
%16:vreg_1 = COPY killed %14
|
||||
S_BRANCH %bb.6
|
||||
|
||||
bb.4:
|
||||
successors: %bb.5(0x40000000), %bb.7(0x40000000)
|
||||
%17:vgpr_32 = V_MAD_F32 0, killed %9, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%18:vgpr_32 = V_MIN_F32_e32 1065353216, killed %17, implicit $exec
|
||||
%19:sreg_64_xexec = V_CMP_NEQ_F32_e64 0, 1065353216, 0, killed %18, 0, implicit $exec
|
||||
%20:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
|
||||
%21:vgpr_32 = V_CNDMASK_B32_e64 0, killed %20, killed %19, implicit $exec
|
||||
%22:sreg_64 = V_CMP_LT_F32_e64 0, 0, 0, killed %21, 0, implicit $exec
|
||||
%23:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%24:sreg_64 = S_AND_B64 %23, %22, implicit-def dead $scc
|
||||
$exec = S_MOV_B64_term killed %24
|
||||
SI_MASK_BRANCH %bb.7, implicit $exec
|
||||
S_BRANCH %bb.5
|
||||
|
||||
bb.5:
|
||||
successors: %bb.7(0x80000000)
|
||||
S_BRANCH %bb.7
|
||||
|
||||
bb.6:
|
||||
successors: %bb.8(0x40000000), %bb.10(0x40000000)
|
||||
%25:vreg_1 = COPY killed %16
|
||||
%26:vreg_128 = COPY killed %15
|
||||
%27:sreg_64 = V_CMP_NE_U32_e64 0, killed %25, implicit $exec
|
||||
%28:sreg_64 = S_AND_B64 $exec, killed %27, implicit-def dead $scc
|
||||
$vcc = COPY killed %28
|
||||
%29:vreg_128 = COPY killed %26
|
||||
S_CBRANCH_VCCNZ %bb.8, implicit killed $vcc
|
||||
S_BRANCH %bb.10
|
||||
|
||||
bb.7:
|
||||
successors: %bb.6(0x80000000)
|
||||
$exec = S_OR_B64 $exec, killed %23, implicit-def $scc
|
||||
%30:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%15:vreg_128 = COPY %13
|
||||
%16:vreg_1 = COPY killed %30
|
||||
S_BRANCH %bb.6
|
||||
|
||||
bb.8:
|
||||
successors: %bb.9(0x40000000), %bb.11(0x40000000)
|
||||
%31:vreg_128 = COPY killed %13
|
||||
S_CBRANCH_SCC1 %bb.11, implicit undef $scc
|
||||
S_BRANCH %bb.9
|
||||
|
||||
bb.9:
|
||||
successors: %bb.11(0x80000000)
|
||||
%32:sreg_32_xm0 = S_MOV_B32 0
|
||||
undef %33.sub0:sreg_128 = COPY %32
|
||||
%33.sub1:sreg_128 = COPY %32
|
||||
%33.sub2:sreg_128 = COPY %32
|
||||
%33.sub3:sreg_128 = COPY killed %32
|
||||
%34:sreg_128 = COPY killed %33
|
||||
%35:vreg_128 = COPY killed %34
|
||||
%31:vreg_128 = COPY killed %35
|
||||
S_BRANCH %bb.11
|
||||
|
||||
bb.10:
|
||||
successors: %bb.14(0x80000000)
|
||||
%36:vreg_128 = COPY killed %29
|
||||
S_BRANCH %bb.14
|
||||
|
||||
bb.11:
|
||||
successors: %bb.13(0x40000000), %bb.12(0x40000000)
|
||||
%37:vreg_128 = COPY killed %31
|
||||
S_CBRANCH_SCC0 %bb.13, implicit undef $scc
|
||||
|
||||
bb.12:
|
||||
successors: %bb.10(0x80000000)
|
||||
%29:vreg_128 = COPY killed %37
|
||||
S_BRANCH %bb.10
|
||||
|
||||
bb.13:
|
||||
successors: %bb.10(0x80000000)
|
||||
%29:vreg_128 = COPY killed %37
|
||||
S_BRANCH %bb.10
|
||||
|
||||
bb.14:
|
||||
successors: %bb.15(0x40000000), %bb.16(0x40000000)
|
||||
%38:vgpr_32 = V_MAD_F32 0, killed %36.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec
|
||||
%39:vgpr_32 = V_MAD_F32 0, killed %38, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%40:vgpr_32 = V_MAD_F32 0, killed %39, 0, -1090519040, 0, 1056964608, 0, 0, implicit $exec
|
||||
%41:vgpr_32 = V_MAD_F32 0, killed %40, 0, 0, 0, -1090519040, 0, 0, implicit $exec
|
||||
%42:vgpr_32 = V_CVT_I32_F32_e32 killed %41, implicit $exec
|
||||
%43:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %44:sreg_128, 12, 0 :: (dereferenceable invariant load 4)
|
||||
%45:vgpr_32 = V_MUL_LO_I32 killed %42, killed %43, implicit $exec
|
||||
%46:vgpr_32 = V_LSHLREV_B32_e32 2, killed %45, implicit $exec
|
||||
%47:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %46, undef %48:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
|
||||
%49:sreg_64 = V_CMP_NE_U32_e64 0, killed %47, implicit $exec
|
||||
%50:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%51:sreg_64 = S_AND_B64 %50, %49, implicit-def dead $scc
|
||||
$exec = S_MOV_B64_term killed %51
|
||||
SI_MASK_BRANCH %bb.16, implicit $exec
|
||||
S_BRANCH %bb.15
|
||||
|
||||
bb.15:
|
||||
successors: %bb.16(0x80000000)
|
||||
|
||||
bb.16:
|
||||
successors: %bb.17(0x80000000)
|
||||
$exec = S_OR_B64 $exec, killed %50, implicit-def $scc
|
||||
S_BRANCH %bb.17
|
||||
|
||||
bb.17:
|
||||
successors: %bb.21(0x40000000), %bb.18(0x40000000)
|
||||
S_CBRANCH_SCC1 %bb.21, implicit undef $scc
|
||||
|
||||
bb.18:
|
||||
successors: %bb.19(0x40000000), %bb.20(0x40000000)
|
||||
S_CBRANCH_SCC1 %bb.19, implicit undef $scc
|
||||
S_BRANCH %bb.20
|
||||
|
||||
bb.19:
|
||||
successors: %bb.20(0x80000000)
|
||||
|
||||
bb.20:
|
||||
successors: %bb.21(0x80000000)
|
||||
|
||||
bb.21:
|
||||
S_ENDPGM
|
||||
...
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing,rename-independent-subregs %s -o - | FileCheck -check-prefix=GCN %s
|
||||
|
||||
# This test is for a bug where the following happens:
|
||||
#
|
||||
# Inside the loop, %29.sub2 is used in a V_LSHLREV whose result is then used
|
||||
# in an LDS read. %29 is a 128 bit value that is linked by copies to
|
||||
# %45 (from phi elimination), %28 (the value in the loop pre-header),
|
||||
# %31 (defined and subreg-modified in the loop, and used after the loop)
|
||||
# and %30:
|
||||
#
|
||||
# %45:vreg_128 = COPY killed %28
|
||||
# bb.1:
|
||||
# %29:vreg_128 = COPY killed %45
|
||||
# %39:vgpr_32 = V_LSHLREV_B32_e32 2, %29.sub2, implicit $exec
|
||||
# %31:vreg_128 = COPY killed %29
|
||||
# %31.sub1:vreg_128 = COPY %34
|
||||
# %30:vreg_128 = COPY %31
|
||||
# %45:vreg_128 = COPY killed %30
|
||||
# S_CBRANCH_EXECNZ %bb.39, implicit $exec
|
||||
# S_BRANCH %bb.40
|
||||
# bb.2:
|
||||
# undef %32.sub0:vreg_128 = COPY killed %31.sub0
|
||||
#
|
||||
# So this coalesces together into a single 128 bit value whose sub1 is modified
|
||||
# in the loop, but the sub2 used in the V_LSHLREV is not modified in the loop.
|
||||
#
|
||||
# The bug is that the coalesced value has a L00000004 subrange (for sub2) that
|
||||
# says that it is not live up to the end of the loop block. The symptom is that
|
||||
# Rename Independent Subregs separates sub2 into its own register, and it is
|
||||
# not live round the loop, so that pass adds an IMPLICIT_DEF for it just before
|
||||
# the loop backedge.
|
||||
|
||||
# GCN: bb.1:
|
||||
# GCN: V_LSHLREV_B32_e32 2, [[val:%[0-9][0-9]*]].sub2
|
||||
# GCN-NOT: [[val]]:vreg_128 = IMPLICIT_DEF
|
||||
|
||||
---
|
||||
name: _amdgpu_cs_main
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
|
||||
%3:sgpr_32 = S_MOV_B32 0
|
||||
undef %19.sub1:vreg_128 = COPY undef %3
|
||||
%4:sgpr_32 = S_MOV_B32 1
|
||||
%5:sgpr_32 = S_MOV_B32 2
|
||||
%11:sreg_32_xm0 = S_MOV_B32 255
|
||||
undef %28.sub0:vreg_128 = COPY killed %3
|
||||
%28.sub1:vreg_128 = COPY killed %4
|
||||
%28.sub2:vreg_128 = COPY killed %11
|
||||
%28.sub3:vreg_128 = COPY killed %5
|
||||
%2:sreg_64 = S_MOV_B64 0
|
||||
%34:sreg_32 = S_MOV_B32 7
|
||||
%37:vreg_128 = COPY undef %42:vreg_128
|
||||
%43:sreg_64 = COPY killed %2
|
||||
%44:vreg_128 = COPY killed %37
|
||||
%45:vreg_128 = COPY killed %28
|
||||
|
||||
bb.1:
|
||||
successors: %bb.1, %bb.2
|
||||
|
||||
%29:vreg_128 = COPY killed %45
|
||||
%36:vreg_128 = COPY killed %44
|
||||
%0:sreg_64 = COPY killed %43
|
||||
%39:vgpr_32 = V_LSHLREV_B32_e32 2, %29.sub2, implicit $exec
|
||||
%41:vgpr_32 = V_ADD_I32_e32 1152, %39, implicit-def dead $vcc, implicit $exec
|
||||
$m0 = S_MOV_B32 -1
|
||||
%12:vreg_64 = DS_READ2_B32 killed %41, 0, 1, 0, implicit $m0, implicit $exec
|
||||
%13:vreg_64 = DS_READ2_B32 %39, -112, -111, 0, implicit $m0, implicit $exec
|
||||
%14:vreg_64 = DS_READ2_B32 %39, 0, 1, 0, implicit $m0, implicit $exec
|
||||
%40:vgpr_32 = V_ADD_I32_e32 1160, %39, implicit-def dead $vcc, implicit $exec
|
||||
%15:vreg_64 = DS_READ2_B32 killed %40, 0, 1, 0, implicit $m0, implicit $exec
|
||||
%16:vreg_64 = DS_READ2_B32 %39, -110, -109, 0, implicit $m0, implicit $exec
|
||||
%17:vreg_64 = DS_READ2_B32 %39, 2, 3, 0, implicit $m0, implicit $exec
|
||||
undef %35.sub1:vreg_128 = COPY undef %34
|
||||
%31:vreg_128 = COPY killed %29
|
||||
%31.sub1:vreg_128 = COPY %34
|
||||
%38:vgpr_32 = V_ADD_I32_e32 1, %36.sub0, implicit-def dead $vcc, implicit $exec
|
||||
%18:sreg_64 = V_CMP_LT_I32_e64 5, %38, implicit $exec
|
||||
%1:sreg_64 = S_OR_B64 killed %18, killed %0, implicit-def $scc
|
||||
%30:vreg_128 = COPY %31
|
||||
%43:sreg_64 = COPY %1
|
||||
%44:vreg_128 = COPY %35
|
||||
%45:vreg_128 = COPY killed %30
|
||||
$exec = S_ANDN2_B64_term $exec, %1
|
||||
S_CBRANCH_EXECNZ %bb.1, implicit $exec
|
||||
S_BRANCH %bb.2
|
||||
|
||||
bb.2:
|
||||
$exec = S_OR_B64 $exec, killed %1, implicit-def $scc
|
||||
%33:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
undef %32.sub0:vreg_128 = COPY killed %31.sub0
|
||||
%32.sub2:vreg_128 = COPY %33
|
||||
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %32:vreg_128
|
||||
S_ENDPGM
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue