forked from OSchip/llvm-project
[WebAssembly] Implement i64x2 comparisons
Removes the prototype builtin and intrinsic for i64x2.eq and implements that instruction as well as the other i64x2 comparison instructions in the final SIMD spec. Unsigned comparisons were not included in the final spec, so they still need to be scalarized via a custom lowering. Differential Revision: https://reviews.llvm.org/D99623
This commit is contained in:
Thomas Lively
parent
df0b97dab0
commit
45783d0e8a
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@ -215,7 +215,5 @@ TARGET_BUILTIN(__builtin_wasm_store16_lane, "vs*V8sIi", "n", "simd128")
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TARGET_BUILTIN(__builtin_wasm_store32_lane, "vi*V4iIi", "n", "simd128")
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TARGET_BUILTIN(__builtin_wasm_store64_lane, "vLLi*V2LLiIi", "n", "simd128")
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TARGET_BUILTIN(__builtin_wasm_eq_i64x2, "V2LLiV2LLiV2LLi", "nc", "simd128")
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#undef BUILTIN
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#undef TARGET_BUILTIN
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@ -17400,12 +17400,6 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
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Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_popcnt);
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return Builder.CreateCall(Callee, {Vec});
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}
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case WebAssembly::BI__builtin_wasm_eq_i64x2: {
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Value *LHS = EmitScalarExpr(E->getArg(0));
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Value *RHS = EmitScalarExpr(E->getArg(1));
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Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_eq);
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return Builder.CreateCall(Callee, {LHS, RHS});
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}
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case WebAssembly::BI__builtin_wasm_any_true_i8x16:
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case WebAssembly::BI__builtin_wasm_any_true_i16x8:
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case WebAssembly::BI__builtin_wasm_any_true_i32x4:
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@ -650,12 +650,6 @@ i8x16 popcnt(i8x16 x) {
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// WEBASSEMBLY-NEXT: ret
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}
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i64x2 eq_i64x2(i64x2 x, i64x2 y) {
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return __builtin_wasm_eq_i64x2(x, y);
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// WEBASSEMBLY: call <2 x i64> @llvm.wasm.eq(<2 x i64> %x, <2 x i64> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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int any_true_i8x16(i8x16 x) {
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return __builtin_wasm_any_true_i8x16(x);
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// WEBASSEMBLY: call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
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@ -294,13 +294,6 @@ def int_wasm_extadd_pairwise_unsigned :
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[LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Remove this intrinsic and the associated builtin if i64x2.eq gets
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// merged to the proposal.
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def int_wasm_eq :
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Intrinsic<[llvm_v2i64_ty],
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[llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Remove these if possible if they are merged to the spec.
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def int_wasm_convert_low_signed :
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Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty],
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@ -186,9 +186,9 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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for (auto T : {MVT::v4f32, MVT::v2f64})
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setOperationAction(Op, T, Expand);
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// Expand operations not supported for i64x2 vectors
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for (unsigned CC = 0; CC < ISD::SETCC_INVALID; ++CC)
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setCondCodeAction(static_cast<ISD::CondCode>(CC), MVT::v2i64, Custom);
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// Unsigned comparison operations are unavailable for i64x2 vectors.
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for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE})
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setCondCodeAction(CC, MVT::v2i64, Custom);
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// 64x2 conversions are not in the spec
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for (auto Op :
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@ -1779,11 +1779,8 @@ WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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SDValue WebAssemblyTargetLowering::LowerSETCC(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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// The legalizer does not know how to expand the comparison modes of i64x2
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// vectors because no comparison modes are supported. We could solve this by
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// expanding all i64x2 SETCC nodes, but that seems to expand f64x2 SETCC nodes
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// (which return i64x2 results) as well. So instead we manually unroll i64x2
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// comparisons here.
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// The legalizer does not know how to expand the unsupported comparison modes
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// of i64x2 vectors, so we manually unroll them here.
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assert(Op->getOperand(0)->getSimpleValueType(0) == MVT::v2i64);
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SmallVector<SDValue, 2> LHS, RHS;
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DAG.ExtractVectorElements(Op->getOperand(0), LHS);
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@ -650,32 +650,38 @@ multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
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// Equality: eq
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let isCommutable = 1 in {
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defm EQ : SIMDConditionInt<"eq", SETEQ, 35>;
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defm EQ : SIMDCondition<I64x2, "eq", SETEQ, 214>;
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defm EQ : SIMDConditionFP<"eq", SETOEQ, 65>;
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} // isCommutable = 1
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// Non-equality: ne
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let isCommutable = 1 in {
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defm NE : SIMDConditionInt<"ne", SETNE, 36>;
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defm NE : SIMDCondition<I64x2, "ne", SETNE, 215>;
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defm NE : SIMDConditionFP<"ne", SETUNE, 66>;
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} // isCommutable = 1
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// Less than: lt_s / lt_u / lt
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defm LT_S : SIMDConditionInt<"lt_s", SETLT, 37>;
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defm LT_S : SIMDCondition<I64x2, "lt_s", SETLT, 216>;
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defm LT_U : SIMDConditionInt<"lt_u", SETULT, 38>;
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defm LT : SIMDConditionFP<"lt", SETOLT, 67>;
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// Greater than: gt_s / gt_u / gt
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defm GT_S : SIMDConditionInt<"gt_s", SETGT, 39>;
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defm GT_S : SIMDCondition<I64x2, "gt_s", SETGT, 217>;
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defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 40>;
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defm GT : SIMDConditionFP<"gt", SETOGT, 68>;
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// Less than or equal: le_s / le_u / le
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defm LE_S : SIMDConditionInt<"le_s", SETLE, 41>;
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defm LE_S : SIMDCondition<I64x2, "le_s", SETLE, 218>;
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defm LE_U : SIMDConditionInt<"le_u", SETULE, 42>;
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defm LE : SIMDConditionFP<"le", SETOLE, 69>;
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// Greater than or equal: ge_s / ge_u / ge
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defm GE_S : SIMDConditionInt<"ge_s", SETGE, 43>;
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defm GE_S : SIMDCondition<I64x2, "ge_s", SETGE, 219>;
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defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 44>;
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defm GE : SIMDConditionFP<"ge", SETOGE, 70>;
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@ -692,14 +698,6 @@ foreach nodes = [[seteq, EQ_F64x2], [setne, NE_F64x2], [setlt, LT_F64x2],
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def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
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(nodes[1] $lhs, $rhs)>;
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// Prototype i64x2.eq
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defm EQ_v2i64 :
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SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
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[(set (v2i64 V128:$dst),
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(int_wasm_eq (v2i64 V128:$lhs), (v2i64 V128:$rhs)))],
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"i64x2.eq\t$dst, $lhs, $rhs", "i64x2.eq", 192>;
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//===----------------------------------------------------------------------===//
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// Bitwise operations
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//===----------------------------------------------------------------------===//
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@ -637,14 +637,20 @@ define <4 x i32> @compare_sext_uge_v4i32 (<4 x i32> %x, <4 x i32> %y) {
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}
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; CHECK-LABEL: compare_eq_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_eq_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i1> @compare_eq_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%res = icmp eq <2 x i64> %x, %y
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ret <2 x i1> %res
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}
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; CHECK-LABEL: compare_sext_eq_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_sext_eq_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i64> @compare_sext_eq_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%cmp = icmp eq <2 x i64> %x, %y
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%res = sext <2 x i1> %cmp to <2 x i64>
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@ -652,14 +658,20 @@ define <2 x i64> @compare_sext_eq_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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}
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; CHECK-LABEL: compare_ne_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_ne_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i1> @compare_ne_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%res = icmp ne <2 x i64> %x, %y
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ret <2 x i1> %res
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}
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; CHECK-LABEL: compare_sext_ne_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_sext_ne_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i64> @compare_sext_ne_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%cmp = icmp ne <2 x i64> %x, %y
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%res = sext <2 x i1> %cmp to <2 x i64>
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@ -667,14 +679,20 @@ define <2 x i64> @compare_sext_ne_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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}
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; CHECK-LABEL: compare_slt_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_slt_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i1> @compare_slt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%res = icmp slt <2 x i64> %x, %y
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ret <2 x i1> %res
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}
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; CHECK-LABEL: compare_sext_slt_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_sext_slt_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.lt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i64> @compare_sext_slt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%cmp = icmp slt <2 x i64> %x, %y
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%res = sext <2 x i1> %cmp to <2 x i64>
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@ -683,6 +701,7 @@ define <2 x i64> @compare_sext_slt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: compare_ult_v2i64:
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; SIMD128-NEXT: .functype compare_ult_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128: i64.lt_u
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define <2 x i1> @compare_ult_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%res = icmp ult <2 x i64> %x, %y
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ret <2 x i1> %res
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@ -690,6 +709,7 @@ define <2 x i1> @compare_ult_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: compare_sext_ult_v2i64:
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; SIMD128-NEXT: .functype compare_sext_ult_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128: i64.lt_u
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define <2 x i64> @compare_sext_ult_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%cmp = icmp ult <2 x i64> %x, %y
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%res = sext <2 x i1> %cmp to <2 x i64>
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@ -697,14 +717,20 @@ define <2 x i64> @compare_sext_ult_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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}
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; CHECK-LABEL: compare_sle_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_sle_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i1> @compare_sle_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%res = icmp sle <2 x i64> %x, %y
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ret <2 x i1> %res
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}
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; CHECK-LABEL: compare_sext_sle_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_sext_sle_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.le_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i64> @compare_sext_sle_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%cmp = icmp sle <2 x i64> %x, %y
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%res = sext <2 x i1> %cmp to <2 x i64>
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@ -713,6 +739,7 @@ define <2 x i64> @compare_sext_sle_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: compare_ule_v2i64:
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; SIMD128-NEXT: .functype compare_ule_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128: i64.le_u
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define <2 x i1> @compare_ule_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%res = icmp ule <2 x i64> %x, %y
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ret <2 x i1> %res
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@ -720,6 +747,7 @@ define <2 x i1> @compare_ule_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: compare_sext_ule_v2i64:
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; SIMD128-NEXT: .functype compare_sext_ule_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128: i64.le_u
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define <2 x i64> @compare_sext_ule_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%cmp = icmp ule <2 x i64> %x, %y
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%res = sext <2 x i1> %cmp to <2 x i64>
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@ -727,14 +755,20 @@ define <2 x i64> @compare_sext_ule_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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}
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; CHECK-LABEL: compare_sgt_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_sgt_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i1> @compare_sgt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%res = icmp sgt <2 x i64> %x, %y
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ret <2 x i1> %res
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}
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; CHECK-LABEL: compare_sext_sgt_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_sext_sgt_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.gt_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i64> @compare_sext_sgt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%cmp = icmp sgt <2 x i64> %x, %y
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%res = sext <2 x i1> %cmp to <2 x i64>
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@ -743,6 +777,7 @@ define <2 x i64> @compare_sext_sgt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: compare_ugt_v2i64:
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; SIMD128-NEXT: .functype compare_ugt_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128: i64.gt_u
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define <2 x i1> @compare_ugt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%res = icmp ugt <2 x i64> %x, %y
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ret <2 x i1> %res
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@ -750,6 +785,7 @@ define <2 x i1> @compare_ugt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: compare_sext_ugt_v2i64:
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; SIMD128-NEXT: .functype compare_sext_ugt_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128: i64.gt_u
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define <2 x i64> @compare_sext_ugt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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%cmp = icmp ugt <2 x i64> %x, %y
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%res = sext <2 x i1> %cmp to <2 x i64>
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@ -757,14 +793,20 @@ define <2 x i64> @compare_sext_ugt_v2i64 (<2 x i64> %x, <2 x i64> %y) {
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}
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; CHECK-LABEL: compare_sge_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-NEXT: .functype compare_sge_v2i64 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i64x2.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; SIMD128-NEXT: return $pop[[R]]{{$}}
|
||||
define <2 x i1> @compare_sge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
|
||||
%res = icmp sge <2 x i64> %x, %y
|
||||
ret <2 x i1> %res
|
||||
}
|
||||
|
||||
; CHECK-LABEL: compare_sext_sge_v2i64:
|
||||
; NO-SIMD128-NOT: i64x2
|
||||
; SIMD128-NEXT: .functype compare_sext_sge_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128-NEXT: i64x2.ge_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; SIMD128-NEXT: return $pop[[R]]{{$}}
|
||||
define <2 x i64> @compare_sext_sge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
|
||||
%cmp = icmp sge <2 x i64> %x, %y
|
||||
%res = sext <2 x i1> %cmp to <2 x i64>
|
||||
|
|
@ -773,6 +815,7 @@ define <2 x i64> @compare_sext_sge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
|
|||
|
||||
; CHECK-LABEL: compare_uge_v2i64:
|
||||
; SIMD128-NEXT: .functype compare_uge_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128: i64.ge_u
|
||||
define <2 x i1> @compare_uge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
|
||||
%res = icmp uge <2 x i64> %x, %y
|
||||
ret <2 x i1> %res
|
||||
|
|
@ -780,6 +823,7 @@ define <2 x i1> @compare_uge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
|
|||
|
||||
; CHECK-LABEL: compare_sext_uge_v2i64:
|
||||
; SIMD128-NEXT: .functype compare_sext_uge_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128: i64.ge_u
|
||||
define <2 x i64> @compare_sext_uge_v2i64 (<2 x i64> %x, <2 x i64> %y) {
|
||||
%cmp = icmp uge <2 x i64> %x, %y
|
||||
%res = sext <2 x i1> %cmp to <2 x i64>
|
||||
|
|
|
|||
|
|
@ -553,16 +553,6 @@ define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) {
|
|||
; ==============================================================================
|
||||
; 2 x i64
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: eq_v2i64:
|
||||
; CHECK-NEXT: .functype eq_v2i64 (v128, v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
declare <2 x i64> @llvm.wasm.eq(<2 x i64>, <2 x i64>)
|
||||
define <2 x i64> @eq_v2i64(<2 x i64> %x, <2 x i64> %y) {
|
||||
%a = call <2 x i64> @llvm.wasm.eq(<2 x i64> %x, <2 x i64> %y)
|
||||
ret <2 x i64> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: extend_low_s_v2i64:
|
||||
; CHECK-NEXT: .functype extend_low_s_v2i64 (v128) -> (v128){{$}}
|
||||
; CHECK-NEXT: i64x2.extend_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
|
||||
|
|
|
|||
|
|
@ -299,33 +299,17 @@ define <2 x i64> @vselect_v2i64(<2 x i1> %c, <2 x i64> %x, <2 x i64> %y) {
|
|||
ret <2 x i64> %res
|
||||
}
|
||||
|
||||
define <2 x i64> @vselect_cmp_v2i64(<2 x i64> %a, <2 x i64> %b,
|
||||
define <2 x i64> @vselect_cmp_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %x, <2 x i64> %y) {
|
||||
; CHECK-LABEL: vselect_cmp_v2i64:
|
||||
; CHECK: .functype vselect_cmp_v2i64 (v128, v128, v128, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 2
|
||||
; CHECK-NEXT: local.get 3
|
||||
; CHECK-NEXT: i64.const -1
|
||||
; CHECK-NEXT: i64.const 0
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i64x2.extract_lane 0
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i64x2.extract_lane 0
|
||||
; CHECK-NEXT: i64.lt_s
|
||||
; CHECK-NEXT: i64.select
|
||||
; CHECK-NEXT: i64x2.splat
|
||||
; CHECK-NEXT: i64.const -1
|
||||
; CHECK-NEXT: i64.const 0
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i64x2.extract_lane 1
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i64x2.extract_lane 1
|
||||
; CHECK-NEXT: i64.lt_s
|
||||
; CHECK-NEXT: i64.select
|
||||
; CHECK-NEXT: i64x2.replace_lane 1
|
||||
; CHECK-NEXT: i64x2.lt_s
|
||||
; CHECK-NEXT: v128.bitselect
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
<2 x i64> %x, <2 x i64> %y) {
|
||||
%c = icmp slt <2 x i64> %a, %b
|
||||
%res = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %y
|
||||
ret <2 x i64> %res
|
||||
|
|
|
|||
|
|
@ -653,17 +653,23 @@ main:
|
|||
# CHECK: i64x2.mul # encoding: [0xfd,0xd5,0x01]
|
||||
i64x2.mul
|
||||
|
||||
# TODO: i64x2.eq # encoding: [0xfd,0xd6,0x01]
|
||||
# CHECK: i64x2.eq # encoding: [0xfd,0xd6,0x01]
|
||||
i64x2.eq
|
||||
|
||||
# TODO: i64x2.ne # encoding: [0xfd,0xd7,0x01]
|
||||
# CHECK: i64x2.ne # encoding: [0xfd,0xd7,0x01]
|
||||
i64x2.ne
|
||||
|
||||
# TODO: i64x2.lt_s # encoding: [0xfd,0xd8,0x01]
|
||||
# CHECK: i64x2.lt_s # encoding: [0xfd,0xd8,0x01]
|
||||
i64x2.lt_s
|
||||
|
||||
# TODO: i64x2.gt_s # encoding: [0xfd,0xd9,0x01]
|
||||
# CHECK: i64x2.gt_s # encoding: [0xfd,0xd9,0x01]
|
||||
i64x2.gt_s
|
||||
|
||||
# TODO: i64x2.le_s # encoding: [0xfd,0xda,0x01]
|
||||
# CHECK: i64x2.le_s # encoding: [0xfd,0xda,0x01]
|
||||
i64x2.le_s
|
||||
|
||||
# TODO: i64x2.ge_s # encoding: [0xfd,0xdb,0x01]
|
||||
# CHECK: i64x2.ge_s # encoding: [0xfd,0xdb,0x01]
|
||||
i64x2.ge_s
|
||||
|
||||
# CHECK: i64x2.extmul_low_i32x4_s # encoding: [0xfd,0xdc,0x01]
|
||||
i64x2.extmul_low_i32x4_s
|
||||
|
|
|
|||
Loading…
Reference in New Issue