forked from OSchip/llvm-project
[X86] Add X86ISD::VMFPROUND to handle the masked case of VCVTPD2PSZ128 which only produces 2 result elements and zeroes the upper elements.
We can't represent this properly with vselect like we normally do. We also have to update the instruction definition to use a VK2WM mask instead of VK4WM to represent this. Fixes another case from PR34877. llvm-svn: 351017
This commit is contained in:
Craig Topper
parent
b17d2136ea
commit
4561edbec0
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@ -21796,7 +21796,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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// does not change the value. Set it to 0 since it can change.
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return DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
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DAG.getIntPtrConstant(0, dl));
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case CVTPD2PS_MASK: {
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case CVTPD2PS_RND_MASK: {
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SDValue Src = Op.getOperand(1);
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SDValue PassThru = Op.getOperand(2);
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SDValue Mask = Op.getOperand(3);
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@ -22058,6 +22058,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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SDValue Results[] = { SetCC, Res };
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return DAG.getMergeValues(Results, dl);
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}
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case CVTPD2PS_MASK:
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case TRUNCATE_TO_REG: {
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SDValue Src = Op.getOperand(1);
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SDValue PassThru = Op.getOperand(2);
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@ -27217,6 +27218,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VFPEXT_RND: return "X86ISD::VFPEXT_RND";
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case X86ISD::VFPEXTS_RND: return "X86ISD::VFPEXTS_RND";
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case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
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case X86ISD::VMFPROUND: return "X86ISD::VMFPROUND";
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case X86ISD::VFPROUND_RND: return "X86ISD::VFPROUND_RND";
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case X86ISD::VFPROUNDS_RND: return "X86ISD::VFPROUNDS_RND";
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case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
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@ -304,6 +304,10 @@ namespace llvm {
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// Vector FP round.
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VFPROUND, VFPROUND_RND, VFPROUNDS_RND,
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// Masked version of above. Used for v2f64->v4f32.
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// SRC, PASSTHRU, MASK
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VMFPROUND,
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// 128-bit vector logical left / right shift
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VSHLDQ, VSRLDQ,
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@ -7969,26 +7969,53 @@ multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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X86VectorVTInfo _Src, SDNode OpNode,
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X86FoldableSchedWrite sched,
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string Broadcast = _.BroadcastStr,
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string Alias = "", X86MemOperand MemOp = _Src.MemOp> {
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string Alias = "", X86MemOperand MemOp = _Src.MemOp,
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RegisterClass MaskRC = _.KRCWM> {
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defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _Src.RC:$src), OpcodeStr, "$src", "$src",
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(_.VT (OpNode (_Src.VT _Src.RC:$src)))>,
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defm rr : AVX512_maskable_common<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _Src.RC:$src),
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(ins _.RC:$src0, MaskRC:$mask, _Src.RC:$src),
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(ins MaskRC:$mask, _Src.RC:$src),
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OpcodeStr, "$src", "$src",
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(_.VT (OpNode (_Src.VT _Src.RC:$src))),
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(vselect MaskRC:$mask,
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(_.VT (OpNode (_Src.VT _Src.RC:$src))),
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_.RC:$src0),
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vselect, "$src0 = $dst">,
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EVEX, Sched<[sched]>;
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defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins MemOp:$src), OpcodeStr#Alias, "$src", "$src",
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defm rm : AVX512_maskable_common<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins MemOp:$src),
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(ins _.RC:$src0, MaskRC:$mask, MemOp:$src),
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(ins MaskRC:$mask, MemOp:$src),
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OpcodeStr#Alias, "$src", "$src",
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(_.VT (OpNode (_Src.VT
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(_Src.LdFrag addr:$src))))>,
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(_Src.LdFrag addr:$src)))),
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(vselect MaskRC:$mask,
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(_.VT (OpNode (_Src.VT
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(_Src.LdFrag addr:$src)))),
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_.RC:$src0),
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vselect, "$src0 = $dst">,
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EVEX, Sched<[sched.Folded]>;
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defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _Src.ScalarMemOp:$src), OpcodeStr,
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defm rmb : AVX512_maskable_common<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _Src.ScalarMemOp:$src),
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(ins _.RC:$src0, MaskRC:$mask, _Src.ScalarMemOp:$src),
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(ins MaskRC:$mask, _Src.ScalarMemOp:$src),
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OpcodeStr,
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"${src}"##Broadcast, "${src}"##Broadcast,
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(_.VT (OpNode (_Src.VT
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(X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
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))>, EVEX, EVEX_B,
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Sched<[sched.Folded]>;
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)),
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(vselect MaskRC:$mask,
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(_.VT
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(OpNode
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(_Src.VT
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(X86VBroadcast
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(_Src.ScalarLdFrag addr:$src))))),
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_.RC:$src0),
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vselect, "$src0 = $dst">,
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EVEX, EVEX_B, Sched<[sched.Folded]>;
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}
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// Coversion with SAE - suppress all exceptions
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multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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@ -8039,7 +8066,8 @@ multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr, X86SchedWriteWidths sc
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}
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let Predicates = [HasVLX] in {
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
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X86vfpround, sched.XMM, "{1to2}", "{x}">, EVEX_V128;
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null_frag, sched.XMM, "{1to2}", "{x}", f128mem, VK2WM>,
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EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fpround,
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sched.YMM, "{1to4}", "{y}">, EVEX_V256;
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@ -8073,6 +8101,35 @@ let Predicates = [HasVLX] in {
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(VCVTPS2PDZ128rm addr:$src)>;
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def : Pat<(v4f64 (extloadv4f32 addr:$src)),
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(VCVTPS2PDZ256rm addr:$src)>;
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// Special patterns to allow use of X86vmfpround for masking. Instruction
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// patterns have been disabled with null_frag.
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def : Pat<(X86vfpround (v2f64 VR128X:$src)),
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(VCVTPD2PSZ128rr VR128X:$src)>;
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def : Pat<(X86vmfpround (v2f64 VR128X:$src), (v4f32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTPD2PSZ128rrk VR128X:$src0, VK2WM:$mask, VR128X:$src)>;
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def : Pat<(X86vmfpround (v2f64 VR128X:$src), v4f32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTPD2PSZ128rrkz VK2WM:$mask, VR128X:$src)>;
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def : Pat<(X86vfpround (loadv2f64 addr:$src)),
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(VCVTPD2PSZ128rm addr:$src)>;
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def : Pat<(X86vmfpround (loadv2f64 addr:$src), (v4f32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTPD2PSZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86vmfpround (loadv2f64 addr:$src), v4f32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTPD2PSZ128rmkz VK2WM:$mask, addr:$src)>;
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def : Pat<(X86vfpround (v2f64 (X86VBroadcast (loadf64 addr:$src)))),
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(VCVTPD2PSZ128rmb addr:$src)>;
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def : Pat<(X86vmfpround (v2f64 (X86VBroadcast (loadf64 addr:$src))),
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(v4f32 VR128X:$src0), VK2WM:$mask),
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(VCVTPD2PSZ128rmbk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86vmfpround (v2f64 (X86VBroadcast (loadf64 addr:$src))),
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v4f32x_info.ImmAllZerosV, VK2WM:$mask),
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(VCVTPD2PSZ128rmbkz VK2WM:$mask, addr:$src)>;
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}
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// Convert Signed/Unsigned Doubleword to Double
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@ -143,6 +143,14 @@ def X86fpextRnd : SDNode<"X86ISD::VFPEXTS_RND",
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SDTCisSameSizeAs<0, 2>,
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SDTCisVT<3, i32>]>>;
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def X86vmfpround: SDNode<"X86ISD::VMFPROUND",
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SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
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SDTCVecEltisVT<1, f64>,
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SDTCisSameSizeAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<1, 3>]>>;
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def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i8>, SDTCisInt<0>]>;
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@ -24,7 +24,7 @@ enum IntrinsicType : uint16_t {
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INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_3OP, INTR_TYPE_4OP,
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INTR_TYPE_2OP_IMM8, INTR_TYPE_3OP_IMM8,
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CMP_MASK, CMP_MASK_CC,CMP_MASK_SCALAR_CC, VSHIFT, COMI, COMI_RM,
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CVTPD2PS, CVTPD2PS_MASK,
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CVTPD2PS, CVTPD2PS_MASK, CVTPD2PS_RND_MASK,
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INTR_TYPE_1OP_MASK, INTR_TYPE_1OP_MASK_RM,
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INTR_TYPE_2OP_MASK, INTR_TYPE_2OP_MASK_RM,
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INTR_TYPE_3OP_MASK,
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@ -461,10 +461,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps, INTR_TYPE_1OP_MASK,
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X86ISD::VFPROUND, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_512, CVTPD2PS_MASK,
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X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps, CVTPD2PS_MASK,
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X86ISD::VFPROUND, X86ISD::VMFPROUND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_512, CVTPD2PS_RND_MASK,
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ISD::FP_ROUND, X86ISD::VFPROUND_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2qq_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, 0),
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