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[AArch64][SVE2] Asm: support FCVTX/FLOGB instructions 

Summary:

Patch completes SVE2 support for:

    SVE Floating Point Unary Operations - Predicated Group

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62526

llvm-svn: 362071
This commit is contained in:
Cullen Rhodes 2019-05-30 08:35:12 +00:00
parent 028413f5ae
commit 455c529f77
6 changed files with 187 additions and 0 deletions
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6
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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@ -1327,6 +1327,12 @@ let Predicates = [HasSVE2] in {
// SVE2 extract vector (immediate offset, constructive)
def EXT_ZZI_B : sve2_int_perm_extract_i_cons<"ext">;
// SVE floating-point convert precision
def FCVTX_ZPmZ_DtoS : sve_fp_2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32, ElementSizeD>;
// SVE floating-point convert to integer
defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb">;
// Predicated shifts
defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;

6
llvm/lib/Target/AArch64/SVEInstrFormats.td
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@ -1676,6 +1676,12 @@ multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm> {
def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>;
}
multiclass sve2_fp_flogb<string asm> {
def _H : sve_fp_2op_p_zd<0b0011010, asm, ZPR16, ZPR16, ElementSizeH>;
def _S : sve_fp_2op_p_zd<0b0011100, asm, ZPR32, ZPR32, ElementSizeS>;
def _D : sve_fp_2op_p_zd<0b0011110, asm, ZPR64, ZPR64, ElementSizeD>;
}
//===----------------------------------------------------------------------===//
// SVE Floating Point Unary Operations - Unpredicated Group
//===----------------------------------------------------------------------===//

43
llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s Normal file
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@ -0,0 +1,43 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
fcvtx z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtx z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtx z0.h, p0/m, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtx z0.h, p0/m, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtx z0.s, p0/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtx z0.s, p0/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtx z0.d, p0/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtx z0.d, p0/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid predicate operation
fcvtx z0.s, p0/z, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtx z0.s, p0/z, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
fcvtx z0.s, p8/m, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: fcvtx z0.s, p8/m, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

50
llvm/test/MC/AArch64/SVE2/fcvtx.s Normal file
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@ -0,0 +1,50 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
fcvtx z0.s, p0/m, z0.d
// CHECK-INST: fcvtx z0.s, p0/m, z0.d
// CHECK-ENCODING: [0x00,0xa0,0x0a,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 00 a0 0a 65 <unknown>
fcvtx z30.s, p7/m, z31.d
// CHECK-INST: fcvtx z30.s, p7/m, z31.d
// CHECK-ENCODING: [0xfe,0xbf,0x0a,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: fe bf 0a 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z5.d, p0/z, z7.d
// CHECK-INST: movprfx z5.d, p0/z, z7.d
// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
fcvtx z5.s, p0/m, z0.d
// CHECK-INST: fcvtx z5.s, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0x0a,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 05 a0 0a 65 <unknown>
movprfx z5, z7
// CHECK-INST: movprfx z5, z7
// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
fcvtx z5.s, p0/m, z0.d
// CHECK-INST: fcvtx z5.s, p0/m, z0.d
// CHECK-ENCODING: [0x05,0xa0,0x0a,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 05 a0 0a 65 <unknown>

28
llvm/test/MC/AArch64/SVE2/flogb-diagnostics.s Normal file
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@ -0,0 +1,28 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid element width
flogb z0.b, p0/m, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: flogb z0.b, p0/m, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid predicate operation
flogb z0.s, p0/z, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: flogb z0.s, p0/z, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Predicate not in restricted predicate range
flogb z0.s, p8/m, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]
// CHECK-NEXT: flogb z0.s, p8/m, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

54
llvm/test/MC/AArch64/SVE2/flogb.s Normal file
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@ -0,0 +1,54 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
flogb z31.h, p7/m, z31.h
// CHECK-INST: flogb z31.h, p7/m, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x1a,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 1a 65 <unknown>
flogb z31.s, p7/m, z31.s
// CHECK-INST: flogb z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x1c,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 1c 65 <unknown>
flogb z31.d, p7/m, z31.d
// CHECK-INST: flogb z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0x1e,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 1e 65 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
flogb z4.d, p7/m, z31.d
// CHECK-INST: flogb z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0x1e,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 1e 65 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
flogb z4.d, p7/m, z31.d
// CHECK-INST: flogb z4.d, p7/m, z31.d
// CHECK-ENCODING: [0xe4,0xbf,0x1e,0x65]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 1e 65 <unknown>