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[x86] clean up setcc with negated operand transform and add missing test; NFCI 

llvm-svn: 298118
This commit is contained in:
Sanjay Patel 2017-03-17 20:29:40 +00:00
parent eb44542f69
commit 455703a0c6
2 changed files with 52 additions and 23 deletions
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29
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -33954,8 +33954,6 @@ static SDValue combineZext(SDNode *N, SelectionDAG &DAG,
return SDValue(); return SDValue();
} }
/// Optimize x == -y --> x+y == 0
/// x != -y --> x+y != 0
static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG, static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) { const X86Subtarget &Subtarget) {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
@ -33964,20 +33962,23 @@ static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDLoc DL(N); SDLoc DL(N);
if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB) if (CC == ISD::SETNE || CC == ISD::SETEQ) {
if (isNullConstant(LHS.getOperand(0)) && LHS.hasOneUse()) { EVT OpVT = LHS.getValueType();
SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS, // 0-x == y --> x+y == 0
LHS.getOperand(1)); // 0-x != y --> x+y != 0
return DAG.getSetCC(DL, N->getValueType(0), addV, if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
DAG.getConstant(0, DL, addV.getValueType()), CC); LHS.hasOneUse()) {
SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, RHS, LHS.getOperand(1));
return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
} }
if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB) // x == 0-y --> x+y == 0
if (isNullConstant(RHS.getOperand(0)) && RHS.hasOneUse()) { // x != 0-y --> x+y != 0
SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS, if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
RHS.getOperand(1)); RHS.hasOneUse()) {
return DAG.getSetCC(DL, N->getValueType(0), addV, SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
DAG.getConstant(0, DL, addV.getValueType()), CC); return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
} }
}
if (VT.getScalarType() == MVT::i1 && if (VT.getScalarType() == MVT::i1 &&
(CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) { (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {

46
llvm/test/CodeGen/X86/neg_cmp.ll
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@ -1,22 +1,50 @@
; RUN: llc < %s -march=x86-64 | FileCheck %s ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; rdar://11245199 ; rdar://11245199
; PR12545 ; PR12545
define void @f(i32 %x, i32 %y) nounwind uwtable ssp {
entry: declare void @g()
; CHECK-LABEL: f:
; CHECK-NOT: neg define void @neg_cmp(i32 %x, i32 %y) nounwind {
; CHECK: add ; CHECK-LABEL: neg_cmp:
; CHECK: # BB#0:
; CHECK-NEXT: addl %esi, %edi
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # BB#2: # %if.then
; CHECK-NEXT: jmp g # TAILCALL
; CHECK-NEXT: .LBB0_1: # %if.end
; CHECK-NEXT: retq
%sub = sub i32 0, %y %sub = sub i32 0, %y
%cmp = icmp eq i32 %x, %sub %cmp = icmp eq i32 %x, %sub
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then:
tail call void @g() nounwind tail call void @g() nounwind
br label %if.end br label %if.end
if.end: ; preds = %if.then, %entry if.end:
ret void
}
define void @neg_cmp_commuted(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: neg_cmp_commuted:
; CHECK: # BB#0:
; CHECK-NEXT: addl %esi, %edi
; CHECK-NEXT: jne .LBB1_1
; CHECK-NEXT: # BB#2: # %if.then
; CHECK-NEXT: jmp g # TAILCALL
; CHECK-NEXT: .LBB1_1: # %if.end
; CHECK-NEXT: retq
%sub = sub i32 0, %y
%cmp = icmp eq i32 %sub, %x
br i1 %cmp, label %if.then, label %if.end
if.then:
tail call void @g() nounwind
br label %if.end
if.end:
ret void ret void
} }
declare void @g()