maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[DAGCombiner] Add general constant vector support to (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 

We already supported scalar constant / splatted constant vector - now accepts any (non opaque) constant scalar / vector

llvm-svn: 284608
This commit is contained in:
Simon Pilgrim 2016-10-19 16:15:30 +00:00
parent c2e9724909
commit 4554e161be
2 changed files with 8 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -4653,16 +4653,15 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
} }
} }
} }
// fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
isConstantOrConstantVector(N1, /* No Opaques */ true)) {
unsigned BitSize = VT.getScalarSizeInBits(); unsigned BitSize = VT.getScalarSizeInBits();
SDLoc DL(N); SDLoc DL(N);
SDValue HiBitsMask = SDValue AllBits = DAG.getConstant(APInt::getAllOnesValue(BitSize), DL, VT);
DAG.getConstant(APInt::getHighBitsSet(BitSize, SDValue HiBitsMask = DAG.getNode(ISD::SHL, DL, VT, AllBits, N1);
BitSize - N1C->getZExtValue()), return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), HiBitsMask);
DL, VT);
return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
HiBitsMask);
} }
// fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)

16
llvm/test/CodeGen/X86/combine-shl.ll
View File

@ -486,24 +486,12 @@ define <4 x i32> @combine_vec_shl_ashr0(<4 x i32> %x) {
define <4 x i32> @combine_vec_shl_ashr1(<4 x i32> %x) { define <4 x i32> @combine_vec_shl_ashr1(<4 x i32> %x) {
; SSE-LABEL: combine_vec_shl_ashr1: ; SSE-LABEL: combine_vec_shl_ashr1:
; SSE: # BB#0: ; SSE: # BB#0:
; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: psrad $8, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: psrad $6, %xmm2
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrad $7, %xmm1
; SSE-NEXT: psrad $5, %xmm0
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: combine_vec_shl_ashr1: ; AVX-LABEL: combine_vec_shl_ashr1:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [5,6,7,8] ; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpsravd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = ashr <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8> %1 = ashr <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
%2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8> %2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8>