forked from OSchip/llvm-project
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
This commit is contained in:
Dan Gohman
parent
ba91b89711
commit
453d64c9f5
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@ -151,7 +151,7 @@ file prints this (at the time of this writing):</p>
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<b>bit</b> isReMaterializable = 0;
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<b>bit</b> isPredicable = 0;
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<b>bit</b> hasDelaySlot = 0;
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<b>bit</b> usesCustomDAGSchedInserter = 0;
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<b>bit</b> usesCustomInserter = 0;
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<b>bit</b> hasCtrlDep = 0;
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<b>bit</b> isNotDuplicable = 0;
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<b>bit</b> hasSideEffects = 0;
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@ -199,7 +199,7 @@ class Instruction {
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bit isReMaterializable = 0; // Is this instruction re-materializable?
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bit isPredicable = 0; // Is this instruction predicable?
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bit hasDelaySlot = 0; // Does this instruction have an delay slot?
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bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
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bit usesCustomInserter = 0; // Pseudo instr needing special help.
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bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
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bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
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bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
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@ -109,7 +109,7 @@ namespace TID {
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UnmodeledSideEffects,
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Commutable,
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ConvertibleTo3Addr,
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UsesCustomDAGSchedInserter,
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UsesCustomInserter,
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Rematerializable,
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CheapAsAMove,
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ExtraSrcRegAllocReq,
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@ -416,7 +416,7 @@ public:
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return Flags & (1 << TID::ConvertibleTo3Addr);
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}
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/// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
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/// usesCustomInsertionHook - Return true if this instruction requires
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/// custom insertion support when the DAG scheduler is inserting it into a
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/// machine basic block. If this is true for the instruction, it basically
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/// means that it is a pseudo instruction used at SelectionDAG time that is
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@ -424,8 +424,8 @@ public:
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///
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/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
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/// is used to insert this into the MachineBasicBlock.
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bool usesCustomDAGSchedInsertionHook() const {
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return Flags & (1 << TID::UsesCustomDAGSchedInserter);
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bool usesCustomInsertionHook() const {
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return Flags & (1 << TID::UsesCustomInserter);
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}
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/// isRematerializable - Returns true if this instruction is a candidate for
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@ -1425,14 +1425,15 @@ public:
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SelectionDAG &DAG) const;
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//===--------------------------------------------------------------------===//
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// Scheduler hooks
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// Instruction Emitting Hooks
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//
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// EmitInstrWithCustomInserter - This method should be implemented by targets
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// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
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// that mark instructions with the 'usesCustomInserter' flag. These
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// instructions are special in various ways, which require special support to
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// insert. The specified MachineInstr is created but not inserted into any
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// basic blocks, and the scheduler passes ownership of it to this method.
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// basic blocks, and this method is called to expand it into a sequence of
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// instructions, potentially also creating new basic blocks and control flow.
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// When new basic blocks are inserted and the edges from MBB to its successors
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// are modified, the method should insert pairs of <OldSucc, NewSucc> into the
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// DenseMap.
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@ -556,7 +556,7 @@ void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
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cast<MachineSDNode>(Node)->memoperands_end());
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if (II.usesCustomDAGSchedInsertionHook()) {
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if (II.usesCustomInsertionHook()) {
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// Insert this instruction into the basic block using a target
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// specific inserter which may returns a new basic block.
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MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
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@ -150,16 +150,20 @@ namespace llvm {
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}
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// EmitInstrWithCustomInserter - This method should be implemented by targets
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// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
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// that mark instructions with the 'usesCustomInserter' flag. These
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// instructions are special in various ways, which require special support to
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// insert. The specified MachineInstr is created but not inserted into any
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// basic blocks, and the scheduler passes ownership of it to this method.
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// basic blocks, and this method is called to expand it into a sequence of
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// instructions, potentially also creating new basic blocks and control flow.
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// When new basic blocks are inserted and the edges from MBB to its successors
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// are modified, the method should insert pairs of <OldSucc, NewSucc> into the
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// DenseMap.
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MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
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#ifndef NDEBUG
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errs() << "If a target marks an instruction with "
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"'usesCustomDAGSchedInserter', it must implement "
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"'usesCustomInserter', it must implement "
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"TargetLowering::EmitInstrWithCustomInserter!";
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#endif
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llvm_unreachable(0);
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@ -158,7 +158,7 @@ def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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"add\t$dst, $rhs", []>;
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// Pseudo instruction that will expand into a tSUBspi + a copy.
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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let usesCustomInserter = 1 in { // Expanded after instruction selection.
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def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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NoItinerary, "@ sub\t$dst, $rhs * 4", []>;
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@ -168,7 +168,7 @@ def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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let Defs = [CPSR] in
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def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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NoItinerary, "@ and\t$dst, $rhs", []>;
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} // usesCustomDAGSchedInserter
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} // usesCustomInserter
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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@ -617,8 +617,8 @@ def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
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// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
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// Expanded by the scheduler into a branch sequence.
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let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
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// Expanded after instruction selection into a branch sequence.
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let usesCustomInserter = 1 in // Expanded after instruction selection.
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def tMOVCCr_pseudo :
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PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
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NoItinerary, "@ tMOVCCr $cc",
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@ -454,14 +454,14 @@ def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
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// Pseudo instruction that will expand into a t2SUBrSPi + a copy.
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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let usesCustomInserter = 1 in { // Expanded after instruction selection.
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def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
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NoItinerary, "@ sub.w\t$dst, $sp, $imm", []>;
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def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
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NoItinerary, "@ subw\t$dst, $sp, $imm", []>;
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def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
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NoItinerary, "@ sub\t$dst, $sp, $rhs", []>;
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} // usesCustomDAGSchedInserter
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} // usesCustomInserter
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//===----------------------------------------------------------------------===//
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@ -164,7 +164,7 @@ def MEMLABEL : PseudoInstAlpha<(outs), (ins s64imm:$i, s64imm:$j, s64imm:$k, s64
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"LSMARKER$$$i$$$j$$$k$$$m:", [], s_pseudo>;
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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let usesCustomInserter = 1 in { // Expanded after instruction selection.
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def CAS32 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$cmp, GPRC:$swp), "",
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[(set GPRC:$dst, (atomic_cmp_swap_32 GPRC:$ptr, GPRC:$cmp, GPRC:$swp))], s_pseudo>;
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def CAS64 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$cmp, GPRC:$swp), "",
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@ -108,7 +108,7 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
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[(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
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}
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let usesCustomDAGSchedInserter = 1 in {
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let usesCustomInserter = 1 in {
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def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cc),
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"# Select8 PSEUDO",
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[(set GR8:$dst,
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@ -253,7 +253,7 @@ let hasDelaySlot = 1, Defs=[FCR31] in {
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// For some explanation, see Select_CC at MipsInstrInfo.td. We also embedd a
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// condiciton code to enable easy handling by the Custom Inserter.
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let usesCustomDAGSchedInserter = 1, Uses=[FCR31] in {
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let usesCustomInserter = 1, Uses=[FCR31] in {
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class PseudoFPSelCC<RegisterClass RC, string asmstr> :
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MipsPseudo<(outs RC:$dst),
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(ins CPURegs:$CmpRes, RC:$T, RC:$F, condcode:$cc), asmstr,
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@ -417,7 +417,7 @@ def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
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// operation. The solution is to create a Mips pseudo SELECT_CC instruction
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// (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
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// replace it for real supported nodes into EmitInstrWithCustomInserter
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let usesCustomDAGSchedInserter = 1 in {
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let usesCustomInserter = 1 in {
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class PseudoSelCC<RegisterClass RC, string asmstr>:
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MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr,
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[(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
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@ -467,9 +467,9 @@ def br_uncond: ControlFormat<0x0, (outs), (ins brtarget:$dst),
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"goto $dst",
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[(br bb:$dst)]>;
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
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// scheduler into a branch sequence.
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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// instruction selection into a branch sequence.
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let usesCustomInserter = 1 in { // Expanded after instruction selection.
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def SELECT_CC_Int_ICC
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: Pseudo<(outs GPR:$dst), (ins GPR:$T, GPR:$F, i8imm:$Cond),
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"; SELECT_CC_Int_ICC PSEUDO!",
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@ -127,7 +127,7 @@ def : Pat<(PPCnop),
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(NOP)>;
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// Atomic operations
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let usesCustomDAGSchedInserter = 1 in {
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let usesCustomInserter = 1 in {
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let Uses = [CR0] in {
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def ATOMIC_LOAD_ADD_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
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@ -363,9 +363,9 @@ def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
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[(set GPRC:$result,
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(PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
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// scheduler into a branch sequence.
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let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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// instruction selection into a branch sequence.
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let usesCustomInserter = 1, // Expanded after instruction selection.
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PPC970_Single = 1 in {
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def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
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i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
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@ -539,7 +539,7 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
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PPC970_DGroup_Single;
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// Atomic operations
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let usesCustomDAGSchedInserter = 1 in {
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let usesCustomInserter = 1 in {
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let Uses = [CR0] in {
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def ATOMIC_LOAD_ADD_I8 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
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@ -238,10 +238,10 @@ let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
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[(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
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}
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
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// scheduler into a branch sequence. This has to handle all permutations of
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// selection between i32/f32/f64 on ICC and FCC.
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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// instruction selection into a branch sequence. This has to handle all
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// permutations of selection between i32/f32/f64 on ICC and FCC.
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let usesCustomInserter = 1 in { // Expanded after instruction selection.
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def SELECT_CC_Int_ICC
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_ICC PSEUDO!",
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@ -25,7 +25,7 @@ def fpimmneg0 : PatLeaf<(fpimm), [{
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return N->isExactlyValue(-0.0);
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}]>;
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let Uses = [PSW], usesCustomDAGSchedInserter = 1 in {
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let Uses = [PSW], usesCustomInserter = 1 in {
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def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
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"# SelectF32 PSEUDO",
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[(set FP32:$dst,
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@ -74,7 +74,7 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
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"#ADJCALLSTACKUP",
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[(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
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let Uses = [PSW], usesCustomDAGSchedInserter = 1 in {
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let Uses = [PSW], usesCustomInserter = 1 in {
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def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
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"# Select32 PSEUDO",
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[(set GR32:$dst,
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@ -1541,7 +1541,7 @@ def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
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}
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// Atomic exchange, and, or, xor
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let Constraints = "$val = $dst", Defs = [EFLAGS],
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usesCustomDAGSchedInserter = 1 in {
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usesCustomInserter = 1 in {
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def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
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"#ATOMAND64 PSEUDO!",
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[(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
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@ -69,7 +69,7 @@ def fpimmneg1 : PatLeaf<(fpimm), [{
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}]>;
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// Some 'special' instructions
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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let usesCustomInserter = 1 in { // Expanded after instruction selection.
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def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
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(outs), (ins i16mem:$dst, RFP32:$src),
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"##FP32_TO_INT16_IN_MEM PSEUDO!",
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@ -524,7 +524,7 @@ def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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}
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// x86-64 va_start lowering magic.
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let usesCustomDAGSchedInserter = 1 in
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let usesCustomInserter = 1 in
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def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
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(outs),
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(ins GR8:$al,
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@ -1129,13 +1129,13 @@ let isTwoAddress = 1 in {
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// Conditional moves
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let Uses = [EFLAGS] in {
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// X86 doesn't have 8-bit conditional moves. Use a customDAGSchedInserter to
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// X86 doesn't have 8-bit conditional moves. Use a customInserter to
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// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
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// however that requires promoting the operands, and can induce additional
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// i8 register pressure. Note that CMOV_GR8 is conservatively considered to
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// clobber EFLAGS, because if one of the operands is zero, the expansion
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// could involve an xor.
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let usesCustomDAGSchedInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
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let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
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def CMOV_GR8 : I<0, Pseudo,
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(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
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"#CMOV_GR8 PSEUDO!",
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@ -3667,7 +3667,7 @@ def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
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// Atomic exchange, and, or, xor
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let Constraints = "$val = $dst", Defs = [EFLAGS],
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usesCustomDAGSchedInserter = 1 in {
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usesCustomInserter = 1 in {
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def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
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"#ATOMAND32 PSEUDO!",
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[(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
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@ -3736,7 +3736,7 @@ let Constraints = "$val1 = $dst1, $val2 = $dst2",
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Defs = [EFLAGS, EAX, EBX, ECX, EDX],
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Uses = [EAX, EBX, ECX, EDX],
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mayLoad = 1, mayStore = 1,
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usesCustomDAGSchedInserter = 1 in {
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usesCustomInserter = 1 in {
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def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
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(ins i64mem:$ptr, GR32:$val1, GR32:$val2),
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||||
"#ATOMAND6432 PSEUDO!", []>;
|
||||
|
|
|
|||
|
|
@ -706,10 +706,9 @@ def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, VR64:$src2)),
|
|||
def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
|
||||
(MMX_PCMPGTDrm VR64:$src1, addr:$src2)>;
|
||||
|
||||
// CMOV* - Used to implement the SELECT DAG operation. Expanded by the
|
||||
// scheduler into a branch sequence.
|
||||
// These are expanded by the scheduler.
|
||||
let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
|
||||
// CMOV* - Used to implement the SELECT DAG operation. Expanded after
|
||||
// instruction selection into a branch sequence.
|
||||
let Uses = [EFLAGS], usesCustomInserter = 1 in {
|
||||
def CMOV_V1I64 : I<0, Pseudo,
|
||||
(outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond),
|
||||
"#CMOV_V1I64 PSEUDO!",
|
||||
|
|
|
|||
|
|
@ -299,10 +299,9 @@ def palign : PatFrag<(ops node:$lhs, node:$rhs),
|
|||
// SSE scalar FP Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
|
||||
// scheduler into a branch sequence.
|
||||
// These are expanded by the scheduler.
|
||||
let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
|
||||
// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
|
||||
// instruction selection into a branch sequence.
|
||||
let Uses = [EFLAGS], usesCustomInserter = 1 in {
|
||||
def CMOV_FR32 : I<0, Pseudo,
|
||||
(outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
|
||||
"#CMOV_FR32 PSEUDO!",
|
||||
|
|
@ -3807,7 +3806,7 @@ let Constraints = "$src1 = $dst" in {
|
|||
}
|
||||
|
||||
// String/text processing instructions.
|
||||
let Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
|
||||
let Defs = [EFLAGS], usesCustomInserter = 1 in {
|
||||
def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
|
||||
"#PCMPISTRM128rr PSEUDO!",
|
||||
|
|
@ -3835,7 +3834,7 @@ def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
|
|||
}
|
||||
|
||||
let Defs = [EFLAGS], Uses = [EAX, EDX],
|
||||
usesCustomDAGSchedInserter = 1 in {
|
||||
usesCustomInserter = 1 in {
|
||||
def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src3, i8imm:$src5),
|
||||
"#PCMPESTRM128rr PSEUDO!",
|
||||
|
|
|
|||
|
|
@ -357,9 +357,9 @@ def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
|
|||
"${:comment} STWFI $src, $addr",
|
||||
[(store GRRegs:$src, ADDRspii:$addr)]>;
|
||||
|
||||
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
|
||||
// scheduler into a branch sequence.
|
||||
let usesCustomDAGSchedInserter = 1 in {
|
||||
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
|
||||
// instruction selection into a branch sequence.
|
||||
let usesCustomInserter = 1 in {
|
||||
def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
|
||||
(ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
|
||||
"${:comment} SELECT_CC PSEUDO!",
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
|
|||
isTerminator = R->getValueAsBit("isTerminator");
|
||||
isReMaterializable = R->getValueAsBit("isReMaterializable");
|
||||
hasDelaySlot = R->getValueAsBit("hasDelaySlot");
|
||||
usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
|
||||
usesCustomInserter = R->getValueAsBit("usesCustomInserter");
|
||||
hasCtrlDep = R->getValueAsBit("hasCtrlDep");
|
||||
isNotDuplicable = R->getValueAsBit("isNotDuplicable");
|
||||
hasSideEffects = R->getValueAsBit("hasSideEffects");
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@ namespace llvm {
|
|||
bool isTerminator;
|
||||
bool isReMaterializable;
|
||||
bool hasDelaySlot;
|
||||
bool usesCustomDAGSchedInserter;
|
||||
bool usesCustomInserter;
|
||||
bool isVariadic;
|
||||
bool hasCtrlDep;
|
||||
bool isNotDuplicable;
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ static unsigned getResultPatternCost(TreePatternNode *P,
|
|||
if (Op->isSubClassOf("Instruction")) {
|
||||
Cost++;
|
||||
CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
|
||||
if (II.usesCustomDAGSchedInserter)
|
||||
if (II.usesCustomInserter)
|
||||
Cost += 10;
|
||||
}
|
||||
for (unsigned i = 0, e = P->getNumChildren(); i != e; ++i)
|
||||
|
|
|
|||
|
|
@ -275,8 +275,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
|||
if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
|
||||
if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
|
||||
if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
|
||||
if (Inst.usesCustomDAGSchedInserter)
|
||||
OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
|
||||
if (Inst.usesCustomInserter) OS << "|(1<<TID::UsesCustomInserter)";
|
||||
if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
|
||||
if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)";
|
||||
if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)";
|
||||
|
|
|
|||
Loading…
Reference in New Issue