forked from OSchip/llvm-project
R600: Make FMIN/MAXNUM legal on all asics
v2: Add tests Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> reviewer: arsenm llvm-svn: 234716
This commit is contained in:
Jan Vesely
parent
811ef52db7
commit
452b036697
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@ -126,6 +126,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
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setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
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setOperationAction(ISD::FRINT, MVT::f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
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setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
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setOperationAction(ISD::FROUND, MVT::f32, Custom);
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setOperationAction(ISD::FROUND, MVT::f64, Custom);
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@ -683,6 +683,11 @@ def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
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// TODO: Do these actually match the regular fmin/fmax behavior?
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def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax_legacy>;
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def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin_legacy>;
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// According to https://msdn.microsoft.com/en-us/library/windows/desktop/cc308050%28v=vs.85%29.aspx
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// DX10 min/max returns the other operand if one is NaN,
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// this matches http://llvm.org/docs/LangRef.html#llvm-minnum-intrinsic
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def MAX_DX10 : R600_2OP_Helper <0x5, "MAX_DX10", fmaxnum>;
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def MIN_DX10 : R600_2OP_Helper <0x6, "MIN_DX10", fminnum>;
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// For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
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// so some of the instruction names don't match the asm string.
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@ -76,8 +76,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM,
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setOperationAction(ISD::FSIN, MVT::f32, Custom);
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setOperationAction(ISD::FCOS, MVT::f32, Custom);
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setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
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setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
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@ -11,6 +11,9 @@ declare double @llvm.maxnum.f64(double, double)
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; FUNC-LABEL: @test_fmax_f32
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; SI: v_max_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG: MAX_DX10 {{.*}}[[OUT]]
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define void @test_fmax_f32(float addrspace(1)* %out, float %a, float %b) nounwind {
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%val = call float @llvm.maxnum.f32(float %a, float %b) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -20,6 +23,10 @@ define void @test_fmax_f32(float addrspace(1)* %out, float %a, float %b) nounwin
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; FUNC-LABEL: @test_fmax_v2f32
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; SI: v_max_f32_e32
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; SI: v_max_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
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; EG: MAX_DX10 {{.*}}[[OUT]]
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; EG: MAX_DX10 {{.*}}[[OUT]]
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define void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind {
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%val = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b) #0
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store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8
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@ -31,6 +38,12 @@ define void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2
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; SI: v_max_f32_e32
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; SI: v_max_f32_e32
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; SI: v_max_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
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; EG: MAX_DX10 {{.*}}[[OUT]]
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; EG: MAX_DX10 {{.*}}[[OUT]]
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; EG: MAX_DX10 {{.*}}[[OUT]]
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; EG: MAX_DX10 {{.*}}[[OUT]]
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define void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind {
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%val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b) #0
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store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16
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@ -46,6 +59,17 @@ define void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4
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; SI: v_max_f32_e32
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; SI: v_max_f32_e32
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; SI: v_max_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
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; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].X
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; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Y
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; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Z
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; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].W
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; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].X
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; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Y
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; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Z
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; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].W
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define void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind {
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%val = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b) #0
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store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32
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@ -69,6 +93,27 @@ define void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8
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; SI: v_max_f32_e32
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; SI: v_max_f32_e32
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; SI: v_max_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]]
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; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].X
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; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Y
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; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Z
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; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].W
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; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].X
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; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Y
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; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Z
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; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].W
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; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].X
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; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].Y
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; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].Z
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; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].W
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; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].X
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; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].Y
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; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].Z
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; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].W
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define void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind {
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%val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b) #0
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store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64
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@ -79,6 +124,10 @@ define void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a,
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; SI-NOT: v_max_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MAX_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define void @constant_fold_fmax_f32(float addrspace(1)* %out) nounwind {
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%val = call float @llvm.maxnum.f32(float 1.0, float 2.0) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -89,6 +138,11 @@ define void @constant_fold_fmax_f32(float addrspace(1)* %out) nounwind {
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; SI-NOT: v_max_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MAX_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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; EG: 2143289344(nan)
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define void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) nounwind {
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%val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -99,6 +153,10 @@ define void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) nounwind {
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; SI-NOT: v_max_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MAX_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) nounwind {
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%val = call float @llvm.maxnum.f32(float 1.0, float 0x7FF8000000000000) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -109,6 +167,10 @@ define void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) nounwind {
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; SI-NOT: v_max_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MAX_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) nounwind {
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%val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 1.0) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -119,6 +181,10 @@ define void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) nounwind {
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; SI-NOT: v_max_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MAX_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) nounwind {
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%val = call float @llvm.maxnum.f32(float 0.0, float 0.0) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -129,6 +195,10 @@ define void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) nounwind {
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; SI-NOT: v_max_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MAX_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) nounwind {
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%val = call float @llvm.maxnum.f32(float 0.0, float -0.0) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -139,6 +209,10 @@ define void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) nounwind {
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; SI-NOT: v_max_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MAX_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) nounwind {
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%val = call float @llvm.maxnum.f32(float -0.0, float 0.0) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -149,6 +223,10 @@ define void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) nounwind {
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; SI-NOT: v_max_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MAX_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) nounwind {
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%val = call float @llvm.maxnum.f32(float -0.0, float -0.0) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -157,6 +235,10 @@ define void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) nounwind {
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; FUNC-LABEL: @fmax_var_immediate_f32
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; SI: v_max_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MAX_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define void @fmax_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind {
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%val = call float @llvm.maxnum.f32(float %a, float 2.0) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -165,6 +247,9 @@ define void @fmax_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind
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; FUNC-LABEL: @fmax_immediate_var_f32
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; SI: v_max_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
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define void @fmax_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind {
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%val = call float @llvm.maxnum.f32(float 2.0, float %a) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -174,6 +259,9 @@ define void @fmax_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind
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; FUNC-LABEL: @fmax_var_literal_f32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
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; SI: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
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define void @fmax_var_literal_f32(float addrspace(1)* %out, float %a) nounwind {
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%val = call float @llvm.maxnum.f32(float %a, float 99.0) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -183,6 +271,9 @@ define void @fmax_var_literal_f32(float addrspace(1)* %out, float %a) nounwind {
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; FUNC-LABEL: @fmax_literal_var_f32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
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; SI: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
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define void @fmax_literal_var_f32(float addrspace(1)* %out, float %a) nounwind {
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%val = call float @llvm.maxnum.f32(float 99.0, float %a) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -1,5 +1,6 @@
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; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare float @llvm.minnum.f32(float, float) #0
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declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #0
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@ -9,6 +10,9 @@ declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #0
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; FUNC-LABEL: @test_fmin_f32
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; SI: v_min_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG: MIN_DX10 {{.*}}[[OUT]]
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define void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) nounwind {
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%val = call float @llvm.minnum.f32(float %a, float %b) #0
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store float %val, float addrspace(1)* %out, align 4
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@ -18,6 +22,10 @@ define void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) nounwin
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; FUNC-LABEL: @test_fmin_v2f32
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; SI: v_min_f32_e32
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; SI: v_min_f32_e32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
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; EG: MIN_DX10 {{.*}}[[OUT]]
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; EG: MIN_DX10 {{.*}}[[OUT]]
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define void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind {
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%val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b) #0
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store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8
|
||||
|
|
@ -29,6 +37,12 @@ define void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2
|
|||
; SI: v_min_f32_e32
|
||||
; SI: v_min_f32_e32
|
||||
; SI: v_min_f32_e32
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
|
||||
; EG: MIN_DX10 {{.*}}[[OUT]]
|
||||
; EG: MIN_DX10 {{.*}}[[OUT]]
|
||||
; EG: MIN_DX10 {{.*}}[[OUT]]
|
||||
; EG: MIN_DX10 {{.*}}[[OUT]]
|
||||
define void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind {
|
||||
%val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) #0
|
||||
store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16
|
||||
|
|
@ -44,6 +58,17 @@ define void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4
|
|||
; SI: v_min_f32_e32
|
||||
; SI: v_min_f32_e32
|
||||
; SI: v_min_f32_e32
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W
|
||||
define void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind {
|
||||
%val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b) #0
|
||||
store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32
|
||||
|
|
@ -67,6 +92,27 @@ define void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8
|
|||
; SI: v_min_f32_e32
|
||||
; SI: v_min_f32_e32
|
||||
; SI: v_min_f32_e32
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]]
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]]
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].X
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Y
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Z
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].W
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].X
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Y
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Z
|
||||
; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].W
|
||||
define void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind {
|
||||
%val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b) #0
|
||||
store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64
|
||||
|
|
@ -77,6 +123,10 @@ define void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a,
|
|||
; SI-NOT: v_min_f32_e32
|
||||
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
|
||||
; SI: buffer_store_dword [[REG]]
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG-NOT: MIN_DX10
|
||||
; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
|
||||
define void @constant_fold_fmin_f32(float addrspace(1)* %out) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float 1.0, float 2.0) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -87,6 +137,11 @@ define void @constant_fold_fmin_f32(float addrspace(1)* %out) nounwind {
|
|||
; SI-NOT: v_min_f32_e32
|
||||
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000
|
||||
; SI: buffer_store_dword [[REG]]
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG-NOT: MIN_DX10
|
||||
; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
|
||||
; EG: 2143289344(nan)
|
||||
define void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -97,6 +152,10 @@ define void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) nounwind {
|
|||
; SI-NOT: v_min_f32_e32
|
||||
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
|
||||
; SI: buffer_store_dword [[REG]]
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG-NOT: MIN_DX10
|
||||
; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
|
||||
define void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -107,6 +166,10 @@ define void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) nounwind {
|
|||
; SI-NOT: v_min_f32_e32
|
||||
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
|
||||
; SI: buffer_store_dword [[REG]]
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG-NOT: MIN_DX10
|
||||
; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
|
||||
define void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -117,6 +180,10 @@ define void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) nounwind {
|
|||
; SI-NOT: v_min_f32_e32
|
||||
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[REG]]
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG-NOT: MIN_DX10
|
||||
; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
|
||||
define void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float 0.0, float 0.0) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -127,6 +194,10 @@ define void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) nounwind {
|
|||
; SI-NOT: v_min_f32_e32
|
||||
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0
|
||||
; SI: buffer_store_dword [[REG]]
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG-NOT: MIN_DX10
|
||||
; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
|
||||
define void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float 0.0, float -0.0) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -137,6 +208,10 @@ define void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind {
|
|||
; SI-NOT: v_min_f32_e32
|
||||
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
|
||||
; SI: buffer_store_dword [[REG]]
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG-NOT: MIN_DX10
|
||||
; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
|
||||
define void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float -0.0, float 0.0) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -147,6 +222,10 @@ define void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind {
|
|||
; SI-NOT: v_min_f32_e32
|
||||
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
|
||||
; SI: buffer_store_dword [[REG]]
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG-NOT: MIN_DX10
|
||||
; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
|
||||
define void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float -0.0, float -0.0) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -155,6 +234,9 @@ define void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) nounwind {
|
|||
|
||||
; FUNC-LABEL: @fmin_var_immediate_f32
|
||||
; SI: v_min_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
|
||||
define void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float %a, float 2.0) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -163,6 +245,9 @@ define void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind
|
|||
|
||||
; FUNC-LABEL: @fmin_immediate_var_f32
|
||||
; SI: v_min_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}}
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
|
||||
define void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float 2.0, float %a) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -172,6 +257,9 @@ define void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind
|
|||
; FUNC-LABEL: @fmin_var_literal_f32
|
||||
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
|
||||
; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
|
||||
define void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float %a, float 99.0) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
@ -181,6 +269,9 @@ define void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) nounwind {
|
|||
; FUNC-LABEL: @fmin_literal_var_f32
|
||||
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
|
||||
; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
|
||||
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
|
||||
; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
|
||||
define void @fmin_literal_var_f32(float addrspace(1)* %out, float %a) nounwind {
|
||||
%val = call float @llvm.minnum.f32(float 99.0, float %a) #0
|
||||
store float %val, float addrspace(1)* %out, align 4
|
||||
|
|
|
|||
Loading…
Reference in New Issue