forked from OSchip/llvm-project
split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
llvm-svn: 117769
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5a477cfd90
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@ -49,7 +49,8 @@ private:
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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ARMOperand *MaybeParseRegister(bool ParseWriteBack);
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int TryParseRegister();
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ARMOperand *TryParseRegisterWithWriteBack();
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ARMOperand *ParseRegisterList();
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ARMOperand *ParseMemory();
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@ -362,41 +363,45 @@ static unsigned MatchRegisterName(StringRef Name);
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/// }
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/// Try to parse a register name. The token must be an Identifier when called,
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/// and if it is a register name the token is eaten and a Reg operand is created
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/// and returned. Otherwise return null.
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/// and if it is a register name the token is eaten and the register number is
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/// returned. Otherwise return -1.
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///
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int ARMAsmParser::TryParseRegister() {
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const AsmToken &Tok = Parser.getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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// FIXME: Validate register for the current architecture; we have to do
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// validation later, so maybe there is no need for this here.
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int RegNum = MatchRegisterName(Tok.getString());
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if (RegNum == -1)
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return -1;
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Parser.Lex(); // Eat identifier token.
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return RegNum;
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}
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/// Try to parse a register name. The token must be an Identifier when called,
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/// and if it is a register name the token is eaten and the register number is
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/// returned. Otherwise return -1.
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///
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/// TODO this is likely to change to allow different register types and or to
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/// parse for a specific register type.
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ARMOperand *ARMAsmParser::MaybeParseRegister(bool ParseWriteBack) {
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SMLoc S, E;
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const AsmToken &Tok = Parser.getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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// FIXME: Validate register for the current architecture; we have to do
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// validation later, so maybe there is no need for this here.
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int RegNum;
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RegNum = MatchRegisterName(Tok.getString());
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if (RegNum == -1)
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return 0;
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S = Tok.getLoc();
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Parser.Lex(); // Eat identifier token.
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E = Parser.getTok().getLoc();
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ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
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SMLoc S = Parser.getTok().getLoc();
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int RegNo = TryParseRegister();
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if (RegNo == -1) return 0;
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SMLoc E = Parser.getTok().getLoc();
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bool Writeback = false;
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if (ParseWriteBack) {
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const AsmToken &ExclaimTok = Parser.getTok();
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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E = ExclaimTok.getLoc();
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Writeback = true;
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Parser.Lex(); // Eat exclaim token
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}
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const AsmToken &ExclaimTok = Parser.getTok();
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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E = ExclaimTok.getLoc();
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Writeback = true;
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Parser.Lex(); // Eat exclaim token
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}
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return ARMOperand::CreateReg(RegNum, Writeback, S, E);
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return ARMOperand::CreateReg(RegNo, Writeback, S, E);
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}
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/// Parse a register list, return it if successful else return null. The first
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@ -478,11 +483,8 @@ ARMOperand *ARMAsmParser::ParseMemory() {
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Error(BaseRegTok.getLoc(), "register expected");
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return 0;
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}
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int BaseRegNum = 0;
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if (ARMOperand *Op = MaybeParseRegister(false)) {
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BaseRegNum = Op->getReg();
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delete Op;
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} else {
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int BaseRegNum = TryParseRegister();
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if (BaseRegNum == -1) {
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Error(BaseRegTok.getLoc(), "register expected");
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return 0;
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}
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@ -593,13 +595,14 @@ bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
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// See if there is a register following the "[Rn," or "[Rn]," we have so far.
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const AsmToken &OffsetRegTok = Parser.getTok();
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if (OffsetRegTok.is(AsmToken::Identifier)) {
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if (ARMOperand *Op = MaybeParseRegister(false)) {
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SMLoc CurLoc = OffsetRegTok.getLoc();
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OffsetRegNum = TryParseRegister();
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if (OffsetRegNum != -1) {
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OffsetIsReg = true;
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E = Op->getEndLoc();
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OffsetRegNum = Op->getReg();
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delete Op;
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E = CurLoc;
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}
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}
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// If we parsed a register as the offset then their can be a shift after that
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if (OffsetRegNum != -1) {
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// Look for a comma then a shift
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@ -675,7 +678,7 @@ ARMOperand *ARMAsmParser::ParseOperand() {
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switch (getLexer().getKind()) {
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case AsmToken::Identifier:
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if (ARMOperand *Op = MaybeParseRegister(true))
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if (ARMOperand *Op = TryParseRegisterWithWriteBack())
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return Op;
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// This was not a register so parse other operands that start with an
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