forked from OSchip/llvm-project
[RISCV] Use register class VR for V instruction operands directly.
@tangxingxin1008 found a bug that regard vadd.vv v1, v3, a0 as a valid V instruction. We should remove the VRegAsmOperand operand class and use VR register class directly. Patched by: tangxingxin1008, Hsiangkai Differential Revision: https://reviews.llvm.org/D91712
This commit is contained in:
Hsiangkai Wang
parent
be00e8893f
commit
44cd03ad04
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@ -31,18 +31,6 @@ def VTypeIOp : Operand<XLenVT> {
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let DecoderMethod = "decodeUImmOperand<11>";
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}
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def VRegAsmOperand : AsmOperandClass {
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let Name = "RVVRegOpOperand";
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let RenderMethod = "addRegOperands";
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let PredicateMethod = "isReg";
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let ParserMethod = "parseRegister";
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}
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def VRegOp : RegisterOperand<VR> {
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let ParserMatchClass = VRegAsmOperand;
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let PrintMethod = "printOperand";
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}
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def VMaskAsmOperand : AsmOperandClass {
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let Name = "RVVMaskRegOpOperand";
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let RenderMethod = "addRegOperands";
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@ -99,27 +87,27 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
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class VUnitStrideLoad<RISCVLSUMOP lumop, RISCVWidth width,
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string opcodestr>
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: RVInstVLU<0b000, width.Value{3}, lumop, width.Value{2-0},
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(outs VRegOp:$vd),
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(outs VR:$vd),
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(ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">;
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// load vd, (rs1), rs2, vm
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class VStridedLoad<RISCVWidth width, string opcodestr>
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: RVInstVLS<0b000, width.Value{3}, width.Value{2-0},
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(outs VRegOp:$vd),
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(outs VR:$vd),
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(ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
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"$vd, (${rs1}), $rs2$vm">;
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// load vd, (rs1), vs2, vm
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class VIndexedLoad<RISCVWidth width, string opcodestr>
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: RVInstVLX<0b000, width.Value{3}, width.Value{2-0},
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(outs VRegOp:$vd),
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(ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr,
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(outs VR:$vd),
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(ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
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"$vd, (${rs1}), $vs2$vm">;
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// vl<nf>r.v vd, (rs1)
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class VWholeLoad<bits<3> nf, string opcodestr>
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: RVInstVLU<nf, 0b0, LUMOPUnitStrideWholeReg,
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0b000, (outs VRegOp:$vd), (ins GPR:$rs1),
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0b000, (outs VR:$vd), (ins GPR:$rs1),
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opcodestr, "$vd, (${rs1})"> {
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let vm = 1;
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let Uses = [];
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@ -129,21 +117,21 @@ class VWholeLoad<bits<3> nf, string opcodestr>
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class VUnitStrideSegmentLoad<bits<3> nf, RISCVLSUMOP lumop,
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RISCVWidth width, string opcodestr>
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: RVInstVLU<nf, width.Value{3}, lumop, width.Value{2-0},
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(outs VRegOp:$vd),
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(outs VR:$vd),
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(ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">;
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// segment load vd, (rs1), rs2, vm
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class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
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: RVInstVLS<nf, width.Value{3}, width.Value{2-0},
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(outs VRegOp:$vd),
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(outs VR:$vd),
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(ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
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"$vd, (${rs1}), $rs2$vm">;
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// segment load vd, (rs1), vs2, vm
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class VIndexedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
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: RVInstVLX<nf, width.Value{3}, width.Value{2-0},
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(outs VRegOp:$vd),
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(ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr,
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(outs VR:$vd),
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(ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
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"$vd, (${rs1}), $vs2$vm">;
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} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
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@ -152,25 +140,25 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
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class VUnitStrideStore<RISCVLSUMOP sumop, RISCVWidth width,
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string opcodestr>
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: RVInstVSU<0b000, width.Value{3}, sumop, width.Value{2-0},
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(outs), (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
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(outs), (ins VR:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
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"$vs3, (${rs1})$vm">;
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// store vd, vs3, (rs1), rs2, vm
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class VStridedStore<RISCVWidth width, string opcodestr>
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: RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs),
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(ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
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(ins VR:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
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opcodestr, "$vs3, (${rs1}), $rs2$vm">;
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// store vd, vs3, (rs1), vs2, vm
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class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
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: RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs),
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(ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
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(ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
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opcodestr, "$vs3, (${rs1}), $vs2$vm">;
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// vs<nf>r.v vd, (rs1)
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class VWholeStore<bits<3> nf, string opcodestr>
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: RVInstVSU<nf, 0b0, SUMOPUnitStrideWholeReg,
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0b000, (outs), (ins VRegOp:$vs3, GPR:$rs1),
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0b000, (outs), (ins VR:$vs3, GPR:$rs1),
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opcodestr, "$vs3, (${rs1})"> {
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let vm = 1;
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let Uses = [];
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@ -179,125 +167,125 @@ class VWholeStore<bits<3> nf, string opcodestr>
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// segment store vd, vs3, (rs1), vm
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class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
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: RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
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(outs), (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
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(outs), (ins VR:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
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"$vs3, (${rs1})$vm">;
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// segment store vd, vs3, (rs1), rs2, vm
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class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
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: RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs),
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(ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
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(ins VR:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
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opcodestr, "$vs3, (${rs1}), $rs2$vm">;
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// segment store vd, vs3, (rs1), vs2, vm
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class VIndexedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
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: RVInstVSX<nf, width.Value{3}, MOPSTIndexedOrder, width.Value{2-0}, (outs),
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(ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
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(ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
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opcodestr, "$vs3, (${rs1}), $vs2$vm">;
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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// op vd, vs2, vs1, vm
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class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVV<funct6, opv, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, VRegOp:$vs1, VMaskOp:$vm),
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: RVInstVV<funct6, opv, (outs VR:$vd),
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(ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
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opcodestr, "$vd, $vs2, $vs1$vm">;
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// op vd, vs2, vs1, v0 (without mask, use v0 as carry input)
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class VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVV<funct6, opv, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, VRegOp:$vs1, VMV0:$v0),
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: RVInstVV<funct6, opv, (outs VR:$vd),
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(ins VR:$vs2, VR:$vs1, VMV0:$v0),
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opcodestr, "$vd, $vs2, $vs1, v0"> {
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let vm = 0;
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}
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// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
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class VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVV<funct6, opv, (outs VRegOp:$vd),
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(ins VRegOp:$vs1, VRegOp:$vs2, VMaskOp:$vm),
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: RVInstVV<funct6, opv, (outs VR:$vd),
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(ins VR:$vs1, VR:$vs2, VMaskOp:$vm),
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opcodestr, "$vd, $vs1, $vs2$vm">;
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// op vd, vs2, vs1
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class VALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVV<funct6, opv, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, VRegOp:$vs1),
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: RVInstVV<funct6, opv, (outs VR:$vd),
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(ins VR:$vs2, VR:$vs1),
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opcodestr, "$vd, $vs2, $vs1"> {
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let vm = 1;
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}
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// op vd, vs2, rs1, vm
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class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVX<funct6, opv, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
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: RVInstVX<funct6, opv, (outs VR:$vd),
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(ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
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opcodestr, "$vd, $vs2, $rs1$vm">;
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// op vd, vs2, rs1, v0 (without mask, use v0 as carry input)
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class VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVX<funct6, opv, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, GPR:$rs1, VMV0:$v0),
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: RVInstVX<funct6, opv, (outs VR:$vd),
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(ins VR:$vs2, GPR:$rs1, VMV0:$v0),
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opcodestr, "$vd, $vs2, $rs1, v0"> {
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let vm = 0;
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}
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// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
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class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVX<funct6, opv, (outs VRegOp:$vd),
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(ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
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: RVInstVX<funct6, opv, (outs VR:$vd),
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(ins GPR:$rs1, VR:$vs2, VMaskOp:$vm),
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opcodestr, "$vd, $rs1, $vs2$vm">;
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// op vd, vs1, vs2
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class VALUVXNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVX<funct6, opv, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, GPR:$rs1),
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: RVInstVX<funct6, opv, (outs VR:$vd),
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(ins VR:$vs2, GPR:$rs1),
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opcodestr, "$vd, $vs2, $rs1"> {
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let vm = 1;
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}
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// op vd, vs2, imm, vm
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class VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
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: RVInstIVI<funct6, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, optype:$imm, VMaskOp:$vm),
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: RVInstIVI<funct6, (outs VR:$vd),
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(ins VR:$vs2, optype:$imm, VMaskOp:$vm),
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opcodestr, "$vd, $vs2, $imm$vm">;
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// op vd, vs2, imm, v0 (without mask, use v0 as carry input)
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class VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
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: RVInstIVI<funct6, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, optype:$imm, VMV0:$v0),
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: RVInstIVI<funct6, (outs VR:$vd),
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(ins VR:$vs2, optype:$imm, VMV0:$v0),
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opcodestr, "$vd, $vs2, $imm, v0"> {
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let vm = 0;
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}
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// op vd, vs2, imm, vm
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class VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
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: RVInstIVI<funct6, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, optype:$imm),
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: RVInstIVI<funct6, (outs VR:$vd),
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(ins VR:$vs2, optype:$imm),
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opcodestr, "$vd, $vs2, $imm"> {
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let vm = 1;
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}
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// op vd, vs2, rs1, vm (Float)
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class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVX<funct6, opv, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, FPR32:$rs1, VMaskOp:$vm),
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: RVInstVX<funct6, opv, (outs VR:$vd),
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(ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm),
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opcodestr, "$vd, $vs2, $rs1$vm">;
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// op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2)
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class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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: RVInstVX<funct6, opv, (outs VRegOp:$vd),
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(ins FPR32:$rs1, VRegOp:$vs2, VMaskOp:$vm),
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: RVInstVX<funct6, opv, (outs VR:$vd),
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(ins FPR32:$rs1, VR:$vs2, VMaskOp:$vm),
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opcodestr, "$vd, $rs1, $vs2$vm">;
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// op vd, vs2, vm (use vs1 as instruction encoding)
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class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
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: RVInstV<funct6, vs1, opv, (outs VRegOp:$vd),
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(ins VRegOp:$vs2, VMaskOp:$vm),
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: RVInstV<funct6, vs1, opv, (outs VR:$vd),
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(ins VR:$vs2, VMaskOp:$vm),
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opcodestr, "$vd, $vs2$vm">;
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
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// vamo vd, (rs1), vs2, vd, vm
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class VAMOWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr>
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: RVInstVAMO<amoop, width.Value{2-0}, (outs VRegOp:$vd_wd),
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(ins GPR:$rs1, VRegOp:$vs2, VRegOp:$vd, VMaskOp:$vm),
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: RVInstVAMO<amoop, width.Value{2-0}, (outs VR:$vd_wd),
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(ins GPR:$rs1, VR:$vs2, VR:$vd, VMaskOp:$vm),
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opcodestr, "$vd_wd, (${rs1}), $vs2, $vd$vm"> {
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let Constraints = "$vd_wd = $vd";
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let wd = 1;
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@ -308,7 +296,7 @@ class VAMOWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr>
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// vamo x0, (rs1), vs2, vs3, vm
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class VAMONoWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr>
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: RVInstVAMO<amoop, width.Value{2-0}, (outs),
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(ins GPR:$rs1, VRegOp:$vs2, VRegOp:$vs3, VMaskOp:$vm),
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(ins GPR:$rs1, VR:$vs2, VR:$vs3, VMaskOp:$vm),
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opcodestr, "x0, (${rs1}), $vs2, $vs3$vm"> {
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bits<5> vs3;
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let Inst{11-7} = vs3;
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@ -549,9 +537,9 @@ defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">;
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} // Constraints = "@earlyclobber $vd"
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def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm",
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(VWADD_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>;
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(VWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
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def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm",
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(VWADDU_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>;
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(VWADDU_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
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// Vector Integer Extension
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defm VZEXT_VF8 : VALU_MV_VS2<"vzext.vf8", 0b010010, 0b00010>;
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@ -579,7 +567,7 @@ defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>;
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defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>;
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def : InstAlias<"vnot.v $vd, $vs$vm",
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(VXOR_VI VRegOp:$vd, VRegOp:$vs, -1, VMaskOp:$vm)>;
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(VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>;
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// Vector Single-Width Bit Shift Instructions
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defm VSLL_V : VALU_IV_V_X_I<"vsll", 0b100101, uimm5>;
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@ -609,64 +597,64 @@ defm VMSGT_V : VALU_IV_X_I<"vmsgt", 0b011111>;
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} // RVVConstraint = NoConstraint
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def : InstAlias<"vmsgtu.vv $vd, $va, $vb$vm",
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(VMSLTU_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
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(VMSLTU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
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def : InstAlias<"vmsgt.vv $vd, $va, $vb$vm",
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(VMSLT_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
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(VMSLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
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def : InstAlias<"vmsgeu.vv $vd, $va, $vb$vm",
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(VMSLEU_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
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(VMSLEU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
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def : InstAlias<"vmsge.vv $vd, $va, $vb$vm",
|
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(VMSLE_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
|
||||
(VMSLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
|
||||
def : InstAlias<"vmsltu.vi $vd, $va, $imm$vm",
|
||||
(VMSLEU_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm,
|
||||
(VMSLEU_VI VR:$vd, VR:$va, simm5_plus1:$imm,
|
||||
VMaskOp:$vm), 0>;
|
||||
def : InstAlias<"vmslt.vi $vd, $va, $imm$vm",
|
||||
(VMSLE_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm,
|
||||
(VMSLE_VI VR:$vd, VR:$va, simm5_plus1:$imm,
|
||||
VMaskOp:$vm), 0>;
|
||||
def : InstAlias<"vmsgeu.vi $vd, $va, $imm$vm",
|
||||
(VMSGTU_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm,
|
||||
(VMSGTU_VI VR:$vd, VR:$va, simm5_plus1:$imm,
|
||||
VMaskOp:$vm), 0>;
|
||||
def : InstAlias<"vmsge.vi $vd, $va, $imm$vm",
|
||||
(VMSGT_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm,
|
||||
(VMSGT_VI VR:$vd, VR:$va, simm5_plus1:$imm,
|
||||
VMaskOp:$vm), 0>;
|
||||
|
||||
let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
|
||||
def PseudoVMSGEU_VX : Pseudo<(outs VRegOp:$vd),
|
||||
(ins VRegOp:$vs2, GPR:$rs1),
|
||||
def PseudoVMSGEU_VX : Pseudo<(outs VR:$vd),
|
||||
(ins VR:$vs2, GPR:$rs1),
|
||||
[], "vmsgeu.vx", "$vd, $vs2, $rs1">;
|
||||
def PseudoVMSGE_VX : Pseudo<(outs VRegOp:$vd),
|
||||
(ins VRegOp:$vs2, GPR:$rs1),
|
||||
def PseudoVMSGE_VX : Pseudo<(outs VR:$vd),
|
||||
(ins VR:$vs2, GPR:$rs1),
|
||||
[], "vmsge.vx", "$vd, $vs2, $rs1">;
|
||||
def PseudoVMSGEU_VX_M : Pseudo<(outs VRNoV0:$vd),
|
||||
(ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
|
||||
(ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
|
||||
[], "vmsgeu.vx", "$vd, $vs2, $rs1$vm">;
|
||||
def PseudoVMSGE_VX_M : Pseudo<(outs VRNoV0:$vd),
|
||||
(ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
|
||||
(ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
|
||||
[], "vmsge.vx", "$vd, $vs2, $rs1$vm">;
|
||||
def PseudoVMSGEU_VX_M_T : Pseudo<(outs VMV0:$vd, VRegOp:$scratch),
|
||||
(ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
|
||||
def PseudoVMSGEU_VX_M_T : Pseudo<(outs VMV0:$vd, VR:$scratch),
|
||||
(ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
|
||||
[], "vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">;
|
||||
def PseudoVMSGE_VX_M_T : Pseudo<(outs VMV0:$vd, VRegOp:$scratch),
|
||||
(ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
|
||||
def PseudoVMSGE_VX_M_T : Pseudo<(outs VMV0:$vd, VR:$scratch),
|
||||
(ins VR:$vs2, GPR:$rs1, VMaskOp:$vm),
|
||||
[], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">;
|
||||
}
|
||||
|
||||
// This apparently unnecessary alias prevents matching `vmsge{u}.vx vd, vs2, vs1` as if
|
||||
// it were an unmasked (i.e. $vm = RISCV::NoRegister) PseudoVMSGE{U}_VX_M.
|
||||
def : InstAlias<"vmsgeu.vx $vd, $va, $rs1",
|
||||
(PseudoVMSGEU_VX VRegOp:$vd, VRegOp:$va, GPR:$rs1), 0>;
|
||||
(PseudoVMSGEU_VX VR:$vd, VR:$va, GPR:$rs1), 0>;
|
||||
def : InstAlias<"vmsge.vx $vd, $va, $rs1",
|
||||
(PseudoVMSGE_VX VRegOp:$vd, VRegOp:$va, GPR:$rs1), 0>;
|
||||
(PseudoVMSGE_VX VR:$vd, VR:$va, GPR:$rs1), 0>;
|
||||
def : InstAlias<"vmsgeu.vx v0, $va, $rs1, $vm, $vt",
|
||||
(PseudoVMSGEU_VX_M_T V0, VRegOp:$vt, VRegOp:$va, GPR:$rs1,
|
||||
(PseudoVMSGEU_VX_M_T V0, VR:$vt, VR:$va, GPR:$rs1,
|
||||
VMaskOp:$vm), 0>;
|
||||
def : InstAlias<"vmsge.vx v0, $va, $rs1, $vm, $vt",
|
||||
(PseudoVMSGE_VX_M_T V0, VRegOp:$vt, VRegOp:$va, GPR:$rs1,
|
||||
(PseudoVMSGE_VX_M_T V0, VR:$vt, VR:$va, GPR:$rs1,
|
||||
VMaskOp:$vm), 0>;
|
||||
def : InstAlias<"vmsgeu.vx $vd, $va, $rs1, $vm",
|
||||
(PseudoVMSGEU_VX_M VRNoV0:$vd, VRegOp:$va, GPR:$rs1,
|
||||
(PseudoVMSGEU_VX_M VRNoV0:$vd, VR:$va, GPR:$rs1,
|
||||
VMaskOp:$vm), 0>;
|
||||
def : InstAlias<"vmsge.vx $vd, $va, $rs1, $vm",
|
||||
(PseudoVMSGE_VX_M VRNoV0:$vd, VRegOp:$va, GPR:$rs1,
|
||||
(PseudoVMSGE_VX_M VRNoV0:$vd, VR:$va, GPR:$rs1,
|
||||
VMaskOp:$vm), 0>;
|
||||
|
||||
// Vector Integer Min/Max Instructions
|
||||
|
|
@ -714,13 +702,13 @@ defm VMERGE_V : VALUm_IV_V_X_I<"vmerge", 0b010111>;
|
|||
// Vector Integer Move Instructions
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1 in {
|
||||
// op vd, vs1
|
||||
def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VRegOp:$vd),
|
||||
(ins VRegOp:$vs1), "vmv.v.v", "$vd, $vs1">;
|
||||
def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd),
|
||||
(ins VR:$vs1), "vmv.v.v", "$vd, $vs1">;
|
||||
// op vd, rs1
|
||||
def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VRegOp:$vd),
|
||||
def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd),
|
||||
(ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">;
|
||||
// op vd, imm
|
||||
def VMV_V_I : RVInstIVI<0b010111, (outs VRegOp:$vd),
|
||||
def VMV_V_I : RVInstIVI<0b010111, (outs VR:$vd),
|
||||
(ins simm5:$imm), "vmv.v.i", "$vd, $imm">;
|
||||
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
|
||||
|
||||
|
|
@ -821,23 +809,23 @@ defm VMFGE_V : VALU_FV_F<"vmfge", 0b011111>;
|
|||
} // RVVConstraint = NoConstraint
|
||||
|
||||
def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm",
|
||||
(VMFLT_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
|
||||
(VMFLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
|
||||
def : InstAlias<"vmfge.vv $vd, $va, $vb$vm",
|
||||
(VMFLE_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
|
||||
(VMFLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>;
|
||||
|
||||
// Vector Floating-Point Classify Instruction
|
||||
defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b010011, 0b10000>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
|
||||
// Vector Floating-Point Merge Instruction
|
||||
def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
|
||||
(ins VRegOp:$vs2, FPR32:$rs1, VMV0:$v0),
|
||||
def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
|
||||
(ins VR:$vs2, FPR32:$rs1, VMV0:$v0),
|
||||
"vfmerge.vfm", "$vd, $vs2, $rs1, v0"> {
|
||||
let vm = 0;
|
||||
}
|
||||
|
||||
// Vector Floating-Point Move Instruction
|
||||
def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
|
||||
def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
|
||||
(ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1"> {
|
||||
let vs2 = 0;
|
||||
let vm = 1;
|
||||
|
|
@ -926,23 +914,23 @@ defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">;
|
|||
defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">;
|
||||
|
||||
def : InstAlias<"vmmv.m $vd, $vs",
|
||||
(VMAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>;
|
||||
(VMAND_MM VR:$vd, VR:$vs, VR:$vs)>;
|
||||
def : InstAlias<"vmclr.m $vd",
|
||||
(VMXOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>;
|
||||
(VMXOR_MM VR:$vd, VR:$vd, VR:$vd)>;
|
||||
def : InstAlias<"vmset.m $vd",
|
||||
(VMXNOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>;
|
||||
(VMXNOR_MM VR:$vd, VR:$vd, VR:$vd)>;
|
||||
def : InstAlias<"vmnot.m $vd, $vs",
|
||||
(VMNAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>;
|
||||
(VMNAND_MM VR:$vd, VR:$vs, VR:$vs)>;
|
||||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
|
||||
// Vector mask population count vpopc
|
||||
def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
|
||||
(ins VRegOp:$vs2, VMaskOp:$vm),
|
||||
(ins VR:$vs2, VMaskOp:$vm),
|
||||
"vpopc.m", "$vd, $vs2$vm">;
|
||||
|
||||
// vfirst find-first-set mask bit
|
||||
def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
|
||||
(ins VRegOp:$vs2, VMaskOp:$vm),
|
||||
(ins VR:$vs2, VMaskOp:$vm),
|
||||
"vfirst.m", "$vd, $vs2$vm">;
|
||||
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
|
||||
|
||||
|
|
@ -962,7 +950,7 @@ defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>;
|
|||
|
||||
// Vector Element Index Instruction
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
|
||||
def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VRegOp:$vd),
|
||||
def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
|
||||
(ins VMaskOp:$vm), "vid.v", "$vd$vm"> {
|
||||
let vs2 = 0;
|
||||
}
|
||||
|
|
@ -970,8 +958,8 @@ def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VRegOp:$vd),
|
|||
// Integer Scalar Move Instructions
|
||||
let vm = 1 in {
|
||||
def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
|
||||
(ins VRegOp:$vs2), "vmv.x.s", "$vd, $vs2">;
|
||||
def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VRegOp:$vd),
|
||||
(ins VR:$vs2), "vmv.x.s", "$vd, $vs2">;
|
||||
def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd),
|
||||
(ins GPR:$rs1), "vmv.s.x", "$vd, $rs1">;
|
||||
|
||||
}
|
||||
|
|
@ -980,8 +968,8 @@ def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VRegOp:$vd),
|
|||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 in {
|
||||
// Floating-Point Scalar Move Instructions
|
||||
def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
|
||||
(ins VRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">;
|
||||
def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VRegOp:$vd),
|
||||
(ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">;
|
||||
def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd),
|
||||
(ins FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">;
|
||||
|
||||
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
|
||||
|
|
@ -1011,8 +999,8 @@ defm VCOMPRESS_V : VALU_MV_Mask<"vcompress", 0b010111>;
|
|||
|
||||
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
|
||||
foreach nf = [1, 2, 4, 8] in {
|
||||
def VMV#nf#R_V : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VRegOp:$vd),
|
||||
(ins VRegOp:$vs2), "vmv" # nf # "r.v",
|
||||
def VMV#nf#R_V : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VR:$vd),
|
||||
(ins VR:$vs2), "vmv" # nf # "r.v",
|
||||
"$vd, $vs2"> {
|
||||
let Uses = [];
|
||||
let vm = 1;
|
||||
|
|
|
|||
|
|
@ -37,6 +37,9 @@ vadd.vv v1, v3, v2, v4.t
|
|||
vadd.vv v1, v3, v2, v0
|
||||
# CHECK-ERROR: expected '.t' suffix
|
||||
|
||||
vadd.vv v1, v3, a0
|
||||
# CHECK-ERROR: invalid operand for instruction
|
||||
|
||||
vmslt.vi v1, v2, -16
|
||||
# CHECK-ERROR: immediate must be in the range [-15, 16]
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue