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Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. 

llvm-svn: 139610
This commit is contained in:
Owen Anderson 2011-09-13 17:59:19 +00:00
parent 2cb4e3c554
commit 44ae2da4ec
2 changed files with 12 additions and 1 deletions
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5
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -3532,7 +3532,10 @@ validateInstruction(MCInst &Inst,
MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
SMLoc Loc = Operands[0]->getStartLoc(); SMLoc Loc = Operands[0]->getStartLoc();
// Check the IT block state first. // Check the IT block state first.
if (inITBlock()) { // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
// being allowed in IT blocks, but not being predicable. It just always
// executes.
if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
unsigned bit = 1; unsigned bit = 1;
if (ITState.FirstCond) if (ITState.FirstCond)
ITState.FirstCond = false; ITState.FirstCond = false;

8
llvm/test/MC/ARM/basic-thumb2-instructions.s
View File

@ -259,6 +259,14 @@ _func:
@ CHECK: bic.w r8, r8, r5, asr #15 @ encoding: [0x28,0xea,0xe5,0x38] @ CHECK: bic.w r8, r8, r5, asr #15 @ encoding: [0x28,0xea,0xe5,0x38]
@ CHECK: bic.w r12, r12, r6, ror #29 @ encoding: [0x2c,0xea,0x76,0x7c] @ CHECK: bic.w r12, r12, r6, ror #29 @ encoding: [0x2c,0xea,0x76,0x7c]
@------------------------------------------------------------------------------
@ BKPT
@------------------------------------------------------------------------------
it pl
bkpt #234
@ CHECK: it pl @ encoding: [0x58,0xbf]
@ CHECK: bkpt #234 @ encoding: [0xea,0xbe]
@------------------------------------------------------------------------------ @------------------------------------------------------------------------------
@ BXJ @ BXJ