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revert r95949, it turns out that adding new prefixes is not a 

great solution for the disassembler, we'll go with "plan b".

llvm-svn: 95957
This commit is contained in:
Chris Lattner 2010-02-12 01:55:31 +00:00
parent 692d06fb77
commit 44ac89f517
2 changed files with 10 additions and 10 deletions
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6
llvm/lib/Target/X86/X86.td
View File

@ -168,11 +168,11 @@ def X86InstrInfo : InstrInfo {
6, 6,
7, 7,
8, 8,
12,
13, 13,
14, 16,
17, 19,
20, 20,
21,
24]; 24];
} }

14
llvm/lib/Target/X86/X86InstrInfo.h
View File

@ -291,7 +291,7 @@ namespace X86II {
// set, there is no prefix byte for obtaining a multibyte opcode. // set, there is no prefix byte for obtaining a multibyte opcode.
// //
Op0Shift = 8, Op0Shift = 8,
Op0Mask = 0x1F << Op0Shift, Op0Mask = 0xF << Op0Shift,
// TB - TwoByte - Set if this instruction has a two byte opcode, which // TB - TwoByte - Set if this instruction has a two byte opcode, which
// starts with a 0x0F byte before the real opcode. // starts with a 0x0F byte before the real opcode.
@ -324,13 +324,13 @@ namespace X86II {
// etc. We only cares about REX.W and REX.R bits and only the former is // etc. We only cares about REX.W and REX.R bits and only the former is
// statically determined. // statically determined.
// //
REXShift = 13, REXShift = 12,
REX_W = 1 << REXShift, REX_W = 1 << REXShift,
//===------------------------------------------------------------------===// //===------------------------------------------------------------------===//
// This three-bit field describes the size of an immediate operand. Zero is // This three-bit field describes the size of an immediate operand. Zero is
// unused so that we can tell if we forgot to set a value. // unused so that we can tell if we forgot to set a value.
ImmShift = 14, ImmShift = 13,
ImmMask = 7 << ImmShift, ImmMask = 7 << ImmShift,
Imm8 = 1 << ImmShift, Imm8 = 1 << ImmShift,
Imm16 = 2 << ImmShift, Imm16 = 2 << ImmShift,
@ -341,7 +341,7 @@ namespace X86II {
// FP Instruction Classification... Zero is non-fp instruction. // FP Instruction Classification... Zero is non-fp instruction.
// FPTypeMask - Mask for all of the FP types... // FPTypeMask - Mask for all of the FP types...
FPTypeShift = 17, FPTypeShift = 16,
FPTypeMask = 7 << FPTypeShift, FPTypeMask = 7 << FPTypeShift,
// NotFP - The default, set for instructions that do not use FP registers. // NotFP - The default, set for instructions that do not use FP registers.
@ -374,17 +374,17 @@ namespace X86II {
SpecialFP = 7 << FPTypeShift, SpecialFP = 7 << FPTypeShift,
// Lock prefix // Lock prefix
LOCKShift = 20, LOCKShift = 19,
LOCK = 1 << LOCKShift, LOCK = 1 << LOCKShift,
// Segment override prefixes. Currently we just need ability to address // Segment override prefixes. Currently we just need ability to address
// stuff in gs and fs segments. // stuff in gs and fs segments.
SegOvrShift = 21, SegOvrShift = 20,
SegOvrMask = 3 << SegOvrShift, SegOvrMask = 3 << SegOvrShift,
FS = 1 << SegOvrShift, FS = 1 << SegOvrShift,
GS = 2 << SegOvrShift, GS = 2 << SegOvrShift,
// Bit 23 is unused. // Bits 22 -> 23 are unused
OpcodeShift = 24, OpcodeShift = 24,
OpcodeMask = 0xFF << OpcodeShift OpcodeMask = 0xFF << OpcodeShift
}; };