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[VE] Optimize leaf functions 

Optimize leaf functions by not generating save/restore for callee saved
registers.  Update regression tests also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91539
This commit is contained in:
Kazushi (Jam) Marukawa 2020-11-15 10:08:10 +09:00
parent 843525075b
commit 44a4f93925
99 changed files with 3420 additions and 3368 deletions
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34
llvm/lib/Target/VE/VEFrameLowering.cpp
View File

@ -198,6 +198,7 @@ void VEFrameLowering::emitSPExtend(MachineFunction &MF, MachineBasicBlock &MBB,
void VEFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
MachineFrameInfo &MFI = MF.getFrameInfo();
const VEInstrInfo &TII = *STI.getInstrInfo();
@ -234,6 +235,9 @@ void VEFrameLowering::emitPrologue(MachineFunction &MF,
// Update stack size with corrected value.
MFI.setStackSize(NumBytes);
if (FuncInfo->isLeafProc())
return;
// Emit Prologue instructions to save multiple registers.
emitPrologueInsns(MF, MBB, MBBI, NumBytes, true);
@ -283,20 +287,22 @@ MachineBasicBlock::iterator VEFrameLowering::eliminateCallFramePseudoInstr(
void VEFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
MachineFrameInfo &MFI = MF.getFrameInfo();
uint64_t NumBytes = MFI.getStackSize();
if (FuncInfo->isLeafProc())
return;
// Emit Epilogue instructions to restore multiple registers.
emitEpilogueInsns(MF, MBB, MBBI, NumBytes, true);
}
// hasFP - Return true if the specified function should have a dedicated frame
// pointer register. This is true if the function has variable sized allocas
// or if frame pointer elimination is disabled. For the case of VE, we don't
// implement FP eliminator yet, but we returns false from this function to
// not refer fp from generated code.
// or if frame pointer elimination is disabled.
bool VEFrameLowering::hasFP(const MachineFunction &MF) const {
const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
@ -318,22 +324,19 @@ StackOffset VEFrameLowering::getFrameIndexReference(const MachineFunction &MF,
Register &FrameReg) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const VERegisterInfo *RegInfo = STI.getRegisterInfo();
const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
bool isFixed = MFI.isFixedObjectIndex(FI);
int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI);
if (FuncInfo->isLeafProc()) {
// If there's a leaf proc, all offsets need to be %sp-based,
// because we haven't caused %fp to actually point to our frame.
if (!hasFP(MF)) {
// If FP is not used, frame indexies are based on a %sp regiter.
FrameReg = VE::SX11; // %sp
return StackOffset::getFixed(FrameOffset +
MF.getFrameInfo().getStackSize());
}
if (RegInfo->needsStackRealignment(MF) && !isFixed) {
// If there is dynamic stack realignment, all local object
// references need to be via %sp or %s17 (bp), to take account
// of the re-alignment.
// If data on stack require realignemnt, frame indexies are based on a %sp
// or %s17 (bp) register. If there is a variable sized object, bp is used.
if (hasBP(MF))
FrameReg = VE::SX17; // %bp
else
@ -341,7 +344,7 @@ StackOffset VEFrameLowering::getFrameIndexReference(const MachineFunction &MF,
return StackOffset::getFixed(FrameOffset +
MF.getFrameInfo().getStackSize());
}
// Finally, default to using %fp.
// Use %fp by default.
FrameReg = RegInfo->getFrameRegister(MF);
return StackOffset::getFixed(FrameOffset);
}
@ -362,9 +365,12 @@ void VEFrameLowering::determineCalleeSaves(MachineFunction &MF,
BitVector &SavedRegs,
RegScavenger *RS) const {
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
const MachineFrameInfo &MFI = MF.getFrameInfo();
if (isLeafProc(MF)) {
VEMachineFunctionInfo *MFI = MF.getInfo<VEMachineFunctionInfo>();
MFI->setLeafProc(true);
// Functions having BP or stack objects need to emit prologue and epilogue
// to allocate local buffer on the stack.
if (isLeafProc(MF) && !hasBP(MF) && !MFI.hasStackObjects()) {
VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
FuncInfo->setLeafProc(true);
}
}

3
llvm/lib/Target/VE/VEFrameLowering.h
View File

@ -39,8 +39,9 @@ public:
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const override;
bool hasBP(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const override;
bool hasBP(const MachineFunction &MF) const;
// VE reserves argument space always for call sites in the function
// immediately on entry of the current function.
bool hasReservedCallFrame(const MachineFunction &MF) const override {

88
llvm/test/CodeGen/VE/Scalar/addition.ll
View File

@ -2,48 +2,48 @@
define signext i8 @func8s(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = add i8 %1, %0
ret i8 %3
}
define signext i16 @func16s(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = add i16 %1, %0
ret i16 %3
}
define signext i32 @func32s(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = add nsw i32 %1, %0
ret i32 %3
}
define i64 @func64s(i64 %0, i64 %1) {
; CHECK-LABEL: func64s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = add nsw i64 %1, %0
ret i64 %3
}
define i128 @func128s(i128 %0, i128 %1) {
; CHECK-LABEL: func128s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.l %s1, %s3, %s1
; CHECK-NEXT: adds.l %s0, %s2, %s0
; CHECK-NEXT: cmpu.l %s2, %s0, %s2
@ -51,53 +51,53 @@ define i128 @func128s(i128 %0, i128 %1) {
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2
; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = add nsw i128 %1, %0
ret i128 %3
}
define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = add i8 %1, %0
ret i8 %3
}
define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = add i16 %1, %0
ret i16 %3
}
define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = add i32 %1, %0
ret i32 %3
}
define i64 @func64z(i64 %0, i64 %1) {
; CHECK-LABEL: func64z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = add i64 %1, %0
ret i64 %3
}
define i128 @func128z(i128 %0, i128 %1) {
; CHECK-LABEL: func128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.l %s1, %s3, %s1
; CHECK-NEXT: adds.l %s0, %s2, %s0
; CHECK-NEXT: cmpu.l %s2, %s0, %s2
@ -105,55 +105,55 @@ define i128 @func128z(i128 %0, i128 %1) {
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2
; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = add i128 %1, %0
ret i128 %3
}
define signext i8 @funci8s(i8 signext %0) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add i8 %0, 5
ret i8 %2
}
define signext i16 @funci16s(i16 signext %0) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add i16 %0, 5
ret i16 %2
}
define signext i32 @funci32s(i32 signext %0) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i32 %0, 5
ret i32 %2
}
define i64 @funci64s(i64 %0) {
; CHECK-LABEL: funci64s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i64 %0, 5
ret i64 %2
}
define i128 @funci128s(i128 %0) {
; CHECK-LABEL: funci128s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
@ -161,53 +161,53 @@ define i128 @funci128s(i128 %0) {
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i128 %0, 5
ret i128 %2
}
define zeroext i8 @funci8z(i8 zeroext %0) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add i8 %0, 5
ret i8 %2
}
define zeroext i16 @funci16z(i16 zeroext %0) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add i16 %0, 5
ret i16 %2
}
define zeroext i32 @funci32z(i32 zeroext %0) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add i32 %0, 5
ret i32 %2
}
define i64 @funci64z(i64 %0) {
; CHECK-LABEL: funci64z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add i64 %0, 5
ret i64 %2
}
define i128 @funci128z(i128 %0) {
; CHECK-LABEL: funci128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
@ -215,25 +215,25 @@ define i128 @funci128z(i128 %0) {
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add i128 %0, 5
ret i128 %2
}
define i64 @funci64_2(i64 %0) {
; CHECK-LABEL: funci64_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: adds.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i64 %0, 2147483648
ret i64 %2
}
define i128 @funci128_2(i128 %0) {
; CHECK-LABEL: funci128_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, -2147483648
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: adds.l %s2, %s0, %s2
@ -243,7 +243,7 @@ define i128 @funci128_2(i128 %0) {
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: adds.l %s1, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i128 %0, 2147483648
ret i128 %2
}

64
llvm/test/CodeGen/VE/Scalar/and.ll
View File

@ -2,146 +2,146 @@
define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i8 %a, %b
ret i8 %res
}
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i8 %b, %a
ret i8 %res
}
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i8 %a, 5
ret i8 %res
}
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i8 -5, %a
ret i8 %res
}
define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i16 %a, %b
ret i16 %res
}
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i16 %b, %a
ret i16 %res
}
define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK: # %bb.0:
; CHECK-NEXT: b.l.t (, %s10)
%res = and i16 %a, 65535
ret i16 %res
}
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (52)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i16 4095, %a
ret i16 %res
}
define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i32 %a, %b
ret i32 %res
}
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i32 %a, %b
ret i32 %res
}
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i32 %a, 268435455
ret i32 %res
}
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i32 %a, 268435455
ret i32 %res
}
define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i64 %a, %b
ret i64 %res
}
define i64 @func64i(i64 %a) {
; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (24)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i64 %a, 1099511627775
ret i64 %res
}
define i128 @func128(i128 %a, i128 %b) {
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s2, %s0
; CHECK-NEXT: and %s1, %s3, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i128 %b, %a
ret i128 %res
}
define i128 @funci128(i128 %a) {
; CHECK-LABEL: funci128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, 5, %s0
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = and i128 %a, 5
ret i128 %res
}

24
llvm/test/CodeGen/VE/Scalar/atomic_fence.ll
View File

@ -5,17 +5,17 @@
; Function Attrs: norecurse nounwind readnone
define void @_Z20atomic_fence_relaxedv() {
; CHECK-LABEL: _Z20atomic_fence_relaxedv:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK: # %bb.0:
; CHECK-NEXT: b.l.t (, %s10)
ret void
}
; Function Attrs: nofree norecurse nounwind
define void @_Z20atomic_fence_consumev() {
; CHECK-LABEL: _Z20atomic_fence_consumev:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
fence acquire
ret void
}
@ -23,9 +23,9 @@ define void @_Z20atomic_fence_consumev() {
; Function Attrs: nofree norecurse nounwind
define void @_Z20atomic_fence_acquirev() {
; CHECK-LABEL: _Z20atomic_fence_acquirev:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
fence acquire
ret void
}
@ -33,9 +33,9 @@ define void @_Z20atomic_fence_acquirev() {
; Function Attrs: nofree norecurse nounwind
define void @_Z20atomic_fence_releasev() {
; CHECK-LABEL: _Z20atomic_fence_releasev:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
fence release
ret void
}
@ -43,9 +43,9 @@ define void @_Z20atomic_fence_releasev() {
; Function Attrs: nofree norecurse nounwind
define void @_Z20atomic_fence_acq_relv() {
; CHECK-LABEL: _Z20atomic_fence_acq_relv:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
fence acq_rel
ret void
}
@ -53,9 +53,9 @@ define void @_Z20atomic_fence_acq_relv() {
; Function Attrs: nofree norecurse nounwind
define void @_Z20atomic_fence_seq_cstv() {
; CHECK-LABEL: _Z20atomic_fence_seq_cstv:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
fence seq_cst
ret void
}

144
llvm/test/CodeGen/VE/Scalar/atomic_load.ll
View File

@ -64,10 +64,10 @@
; Function Attrs: nofree norecurse nounwind
define zeroext i1 @_Z22atomic_load_relaxed_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_relaxed_i1RNSt3__16atomicIbEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: and %s0, 1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 monotonic, align 1
%4 = and i8 %3, 1
@ -78,9 +78,9 @@ define zeroext i1 @_Z22atomic_load_relaxed_i1RNSt3__16atomicIbEE(%"struct.std::_
; Function Attrs: nofree norecurse nounwind
define signext i8 @_Z22atomic_load_relaxed_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_relaxed_i8RNSt3__16atomicIcEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 monotonic, align 1
ret i8 %3
@ -89,9 +89,9 @@ define signext i8 @_Z22atomic_load_relaxed_i8RNSt3__16atomicIcEE(%"struct.std::_
; Function Attrs: nofree norecurse nounwind
define zeroext i8 @_Z22atomic_load_relaxed_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_relaxed_u8RNSt3__16atomicIhEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 monotonic, align 1
ret i8 %3
@ -100,9 +100,9 @@ define zeroext i8 @_Z22atomic_load_relaxed_u8RNSt3__16atomicIhEE(%"struct.std::_
; Function Attrs: nofree norecurse nounwind
define signext i16 @_Z23atomic_load_relaxed_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_i16RNSt3__16atomicIsEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 monotonic, align 2
ret i16 %3
@ -111,9 +111,9 @@ define signext i16 @_Z23atomic_load_relaxed_i16RNSt3__16atomicIsEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define zeroext i16 @_Z23atomic_load_relaxed_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_u16RNSt3__16atomicItEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 monotonic, align 2
ret i16 %3
@ -122,9 +122,9 @@ define zeroext i16 @_Z23atomic_load_relaxed_u16RNSt3__16atomicItEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define signext i32 @_Z23atomic_load_relaxed_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_i32RNSt3__16atomicIiEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 monotonic, align 4
ret i32 %3
@ -133,9 +133,9 @@ define signext i32 @_Z23atomic_load_relaxed_i32RNSt3__16atomicIiEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define zeroext i32 @_Z23atomic_load_relaxed_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_u32RNSt3__16atomicIjEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldl.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 monotonic, align 4
ret i32 %3
@ -144,9 +144,9 @@ define zeroext i32 @_Z23atomic_load_relaxed_u32RNSt3__16atomicIjEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_relaxed_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_i64RNSt3__16atomicIlEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 monotonic, align 8
ret i64 %3
@ -155,9 +155,9 @@ define i64 @_Z23atomic_load_relaxed_i64RNSt3__16atomicIlEE(%"struct.std::__1::at
; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_relaxed_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_relaxed_u64RNSt3__16atomicImEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 monotonic, align 8
ret i64 %3
@ -171,12 +171,12 @@ define i128 @_Z24atomic_load_relaxed_i128RNSt3__16atomicInEE(%"struct.std::__1::
; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9)
; CHECK-NEXT: ld %s0, -16(, %s9)
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8*
@ -196,12 +196,12 @@ define i128 @_Z24atomic_load_relaxed_u128RNSt3__16atomicIoEE(%"struct.std::__1::
; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9)
; CHECK-NEXT: ld %s0, -16(, %s9)
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8*
@ -216,11 +216,11 @@ define i128 @_Z24atomic_load_relaxed_u128RNSt3__16atomicIoEE(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define zeroext i1 @_Z22atomic_load_acquire_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_acquire_i1RNSt3__16atomicIbEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: and %s0, 1, %s0
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 acquire, align 1
%4 = and i8 %3, 1
@ -231,10 +231,10 @@ define zeroext i1 @_Z22atomic_load_acquire_i1RNSt3__16atomicIbEE(%"struct.std::_
; Function Attrs: nofree norecurse nounwind
define signext i8 @_Z22atomic_load_acquire_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_acquire_i8RNSt3__16atomicIcEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.sx %s0, (, %s0)
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 acquire, align 1
ret i8 %3
@ -243,10 +243,10 @@ define signext i8 @_Z22atomic_load_acquire_i8RNSt3__16atomicIcEE(%"struct.std::_
; Function Attrs: nofree norecurse nounwind
define zeroext i8 @_Z22atomic_load_acquire_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_acquire_u8RNSt3__16atomicIhEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 acquire, align 1
ret i8 %3
@ -255,10 +255,10 @@ define zeroext i8 @_Z22atomic_load_acquire_u8RNSt3__16atomicIhEE(%"struct.std::_
; Function Attrs: nofree norecurse nounwind
define signext i16 @_Z23atomic_load_acquire_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_i16RNSt3__16atomicIsEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.sx %s0, (, %s0)
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 acquire, align 2
ret i16 %3
@ -267,10 +267,10 @@ define signext i16 @_Z23atomic_load_acquire_i16RNSt3__16atomicIsEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define zeroext i16 @_Z23atomic_load_acquire_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_u16RNSt3__16atomicItEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 acquire, align 2
ret i16 %3
@ -279,10 +279,10 @@ define zeroext i16 @_Z23atomic_load_acquire_u16RNSt3__16atomicItEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define signext i32 @_Z23atomic_load_acquire_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_i32RNSt3__16atomicIiEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 acquire, align 4
ret i32 %3
@ -291,10 +291,10 @@ define signext i32 @_Z23atomic_load_acquire_i32RNSt3__16atomicIiEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define zeroext i32 @_Z23atomic_load_acquire_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_u32RNSt3__16atomicIjEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldl.zx %s0, (, %s0)
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 acquire, align 4
ret i32 %3
@ -303,10 +303,10 @@ define zeroext i32 @_Z23atomic_load_acquire_u32RNSt3__16atomicIjEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_acquire_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_i64RNSt3__16atomicIlEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 acquire, align 8
ret i64 %3
@ -315,10 +315,10 @@ define i64 @_Z23atomic_load_acquire_i64RNSt3__16atomicIlEE(%"struct.std::__1::at
; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_acquire_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_acquire_u64RNSt3__16atomicImEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: fencem 2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 acquire, align 8
ret i64 %3
@ -332,12 +332,12 @@ define i128 @_Z24atomic_load_acquire_i128RNSt3__16atomicInEE(%"struct.std::__1::
; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9)
; CHECK-NEXT: ld %s0, -16(, %s9)
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8*
@ -357,12 +357,12 @@ define i128 @_Z24atomic_load_acquire_u128RNSt3__16atomicIoEE(%"struct.std::__1::
; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9)
; CHECK-NEXT: ld %s0, -16(, %s9)
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8*
@ -377,11 +377,11 @@ define i128 @_Z24atomic_load_acquire_u128RNSt3__16atomicIoEE(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define zeroext i1 @_Z22atomic_load_seq_cst_i1RNSt3__16atomicIbEE(%"struct.std::__1::atomic"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_seq_cst_i1RNSt3__16atomicIbEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: and %s0, 1, %s0
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 seq_cst, align 1
%4 = and i8 %3, 1
@ -392,10 +392,10 @@ define zeroext i1 @_Z22atomic_load_seq_cst_i1RNSt3__16atomicIbEE(%"struct.std::_
; Function Attrs: nofree norecurse nounwind
define signext i8 @_Z22atomic_load_seq_cst_i8RNSt3__16atomicIcEE(%"struct.std::__1::atomic.0"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_seq_cst_i8RNSt3__16atomicIcEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.sx %s0, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 seq_cst, align 1
ret i8 %3
@ -404,10 +404,10 @@ define signext i8 @_Z22atomic_load_seq_cst_i8RNSt3__16atomicIcEE(%"struct.std::_
; Function Attrs: nofree norecurse nounwind
define zeroext i8 @_Z22atomic_load_seq_cst_u8RNSt3__16atomicIhEE(%"struct.std::__1::atomic.5"* nocapture nonnull readonly align 1 dereferenceable(1) %0) {
; CHECK-LABEL: _Z22atomic_load_seq_cst_u8RNSt3__16atomicIhEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i8, i8* %2 seq_cst, align 1
ret i8 %3
@ -416,10 +416,10 @@ define zeroext i8 @_Z22atomic_load_seq_cst_u8RNSt3__16atomicIhEE(%"struct.std::_
; Function Attrs: nofree norecurse nounwind
define signext i16 @_Z23atomic_load_seq_cst_i16RNSt3__16atomicIsEE(%"struct.std::__1::atomic.10"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_i16RNSt3__16atomicIsEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.sx %s0, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 seq_cst, align 2
ret i16 %3
@ -428,10 +428,10 @@ define signext i16 @_Z23atomic_load_seq_cst_i16RNSt3__16atomicIsEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define zeroext i16 @_Z23atomic_load_seq_cst_u16RNSt3__16atomicItEE(%"struct.std::__1::atomic.15"* nocapture nonnull readonly align 2 dereferenceable(2) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_u16RNSt3__16atomicItEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i16, i16* %2 seq_cst, align 2
ret i16 %3
@ -440,10 +440,10 @@ define zeroext i16 @_Z23atomic_load_seq_cst_u16RNSt3__16atomicItEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define signext i32 @_Z23atomic_load_seq_cst_i32RNSt3__16atomicIiEE(%"struct.std::__1::atomic.20"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_i32RNSt3__16atomicIiEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 seq_cst, align 4
ret i32 %3
@ -452,10 +452,10 @@ define signext i32 @_Z23atomic_load_seq_cst_i32RNSt3__16atomicIiEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define zeroext i32 @_Z23atomic_load_seq_cst_u32RNSt3__16atomicIjEE(%"struct.std::__1::atomic.25"* nocapture nonnull readonly align 4 dereferenceable(4) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_u32RNSt3__16atomicIjEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldl.zx %s0, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i32, i32* %2 seq_cst, align 4
ret i32 %3
@ -464,10 +464,10 @@ define zeroext i32 @_Z23atomic_load_seq_cst_u32RNSt3__16atomicIjEE(%"struct.std:
; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_seq_cst_i64RNSt3__16atomicIlEE(%"struct.std::__1::atomic.30"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_i64RNSt3__16atomicIlEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 seq_cst, align 8
ret i64 %3
@ -476,10 +476,10 @@ define i64 @_Z23atomic_load_seq_cst_i64RNSt3__16atomicIlEE(%"struct.std::__1::at
; Function Attrs: nofree norecurse nounwind
define i64 @_Z23atomic_load_seq_cst_u64RNSt3__16atomicImEE(%"struct.std::__1::atomic.35"* nocapture nonnull readonly align 8 dereferenceable(8) %0) {
; CHECK-LABEL: _Z23atomic_load_seq_cst_u64RNSt3__16atomicImEE:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
%3 = load atomic i64, i64* %2 seq_cst, align 8
ret i64 %3
@ -493,12 +493,12 @@ define i128 @_Z24atomic_load_seq_cst_i128RNSt3__16atomicInEE(%"struct.std::__1::
; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 5, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9)
; CHECK-NEXT: ld %s0, -16(, %s9)
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8*
@ -518,12 +518,12 @@ define i128 @_Z24atomic_load_seq_cst_u128RNSt3__16atomicIoEE(%"struct.std::__1::
; CHECK-NEXT: lea %s0, __atomic_load@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_load@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 5, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s1, -8(, %s9)
; CHECK-NEXT: ld %s0, -16(, %s9)
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
%2 = alloca i128, align 16
%3 = bitcast i128* %2 to i8*

144
llvm/test/CodeGen/VE/Scalar/atomic_store.ll
View File

@ -64,9 +64,9 @@
; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_relaxed_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_relaxed_i1RNSt3__16atomicIbEEb:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i1 %1 to i8
%4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %3, i8* %4 monotonic, align 1
@ -76,9 +76,9 @@ define void @_Z23atomic_store_relaxed_i1RNSt3__16atomicIbEEb(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_relaxed_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) {
; CHECK-LABEL: _Z23atomic_store_relaxed_i8RNSt3__16atomicIcEEc:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 monotonic, align 1
ret void
@ -87,9 +87,9 @@ define void @_Z23atomic_store_relaxed_i8RNSt3__16atomicIcEEc(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_relaxed_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_relaxed_u8RNSt3__16atomicIhEEh:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 monotonic, align 1
ret void
@ -98,9 +98,9 @@ define void @_Z23atomic_store_relaxed_u8RNSt3__16atomicIhEEh(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_i16RNSt3__16atomicIsEEs:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 monotonic, align 2
ret void
@ -109,9 +109,9 @@ define void @_Z24atomic_store_relaxed_i16RNSt3__16atomicIsEEs(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_u16RNSt3__16atomicItEEt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 monotonic, align 2
ret void
@ -120,9 +120,9 @@ define void @_Z24atomic_store_relaxed_u16RNSt3__16atomicItEEt(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_i32RNSt3__16atomicIiEEi:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 monotonic, align 4
ret void
@ -131,9 +131,9 @@ define void @_Z24atomic_store_relaxed_i32RNSt3__16atomicIiEEi(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_u32RNSt3__16atomicIjEEj:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 monotonic, align 4
ret void
@ -142,9 +142,9 @@ define void @_Z24atomic_store_relaxed_u32RNSt3__16atomicIjEEj(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_i64RNSt3__16atomicIlEEl:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 monotonic, align 8
ret void
@ -153,9 +153,9 @@ define void @_Z24atomic_store_relaxed_i64RNSt3__16atomicIlEEl(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_relaxed_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_relaxed_u64RNSt3__16atomicImEEm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 monotonic, align 8
ret void
@ -166,12 +166,12 @@ define void @_Z25atomic_store_relaxed_i128RNSt3__16atomicInEEn(%"struct.std::__1
; CHECK-LABEL: _Z25atomic_store_relaxed_i128RNSt3__16atomicInEEn:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9)
; CHECK-NEXT: st %s1, -16(, %s9)
; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s1, 0, %s4
@ -192,12 +192,12 @@ define void @_Z25atomic_store_relaxed_u128RNSt3__16atomicIoEEo(%"struct.std::__1
; CHECK-LABEL: _Z25atomic_store_relaxed_u128RNSt3__16atomicIoEEo:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9)
; CHECK-NEXT: st %s1, -16(, %s9)
; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s1, 0, %s4
@ -216,10 +216,10 @@ define void @_Z25atomic_store_relaxed_u128RNSt3__16atomicIoEEo(%"struct.std::__1
; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_release_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_release_i1RNSt3__16atomicIbEEb:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i1 %1 to i8
%4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %3, i8* %4 release, align 1
@ -229,10 +229,10 @@ define void @_Z23atomic_store_release_i1RNSt3__16atomicIbEEb(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_release_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) {
; CHECK-LABEL: _Z23atomic_store_release_i8RNSt3__16atomicIcEEc:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 release, align 1
ret void
@ -241,10 +241,10 @@ define void @_Z23atomic_store_release_i8RNSt3__16atomicIcEEc(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_release_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_release_u8RNSt3__16atomicIhEEh:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 release, align 1
ret void
@ -253,10 +253,10 @@ define void @_Z23atomic_store_release_u8RNSt3__16atomicIhEEh(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) {
; CHECK-LABEL: _Z24atomic_store_release_i16RNSt3__16atomicIsEEs:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1
; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 release, align 2
ret void
@ -265,10 +265,10 @@ define void @_Z24atomic_store_release_i16RNSt3__16atomicIsEEs(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_release_u16RNSt3__16atomicItEEt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1
; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 release, align 2
ret void
@ -277,10 +277,10 @@ define void @_Z24atomic_store_release_u16RNSt3__16atomicItEEt(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) {
; CHECK-LABEL: _Z24atomic_store_release_i32RNSt3__16atomicIiEEi:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1
; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 release, align 4
ret void
@ -289,10 +289,10 @@ define void @_Z24atomic_store_release_i32RNSt3__16atomicIiEEi(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_release_u32RNSt3__16atomicIjEEj:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1
; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 release, align 4
ret void
@ -301,10 +301,10 @@ define void @_Z24atomic_store_release_u32RNSt3__16atomicIjEEj(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_release_i64RNSt3__16atomicIlEEl:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1
; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 release, align 8
ret void
@ -313,10 +313,10 @@ define void @_Z24atomic_store_release_i64RNSt3__16atomicIlEEl(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_release_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_release_u64RNSt3__16atomicImEEm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 1
; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 release, align 8
ret void
@ -327,12 +327,12 @@ define void @_Z25atomic_store_release_i128RNSt3__16atomicInEEn(%"struct.std::__1
; CHECK-LABEL: _Z25atomic_store_release_i128RNSt3__16atomicInEEn:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9)
; CHECK-NEXT: st %s1, -16(, %s9)
; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 3, (0)1
; CHECK-NEXT: or %s1, 0, %s4
@ -353,12 +353,12 @@ define void @_Z25atomic_store_release_u128RNSt3__16atomicIoEEo(%"struct.std::__1
; CHECK-LABEL: _Z25atomic_store_release_u128RNSt3__16atomicIoEEo:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9)
; CHECK-NEXT: st %s1, -16(, %s9)
; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 3, (0)1
; CHECK-NEXT: or %s1, 0, %s4
@ -377,11 +377,11 @@ define void @_Z25atomic_store_release_u128RNSt3__16atomicIoEEo(%"struct.std::__1
; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_seq_cst_i1RNSt3__16atomicIbEEb(%"struct.std::__1::atomic"* nocapture nonnull align 1 dereferenceable(1) %0, i1 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_seq_cst_i1RNSt3__16atomicIbEEb:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i1 %1 to i8
%4 = getelementptr inbounds %"struct.std::__1::atomic", %"struct.std::__1::atomic"* %0, i64 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %3, i8* %4 seq_cst, align 1
@ -391,11 +391,11 @@ define void @_Z23atomic_store_seq_cst_i1RNSt3__16atomicIbEEb(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_seq_cst_i8RNSt3__16atomicIcEEc(%"struct.std::__1::atomic.0"* nocapture nonnull align 1 dereferenceable(1) %0, i8 signext %1) {
; CHECK-LABEL: _Z23atomic_store_seq_cst_i8RNSt3__16atomicIcEEc:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.0", %"struct.std::__1::atomic.0"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 seq_cst, align 1
ret void
@ -404,11 +404,11 @@ define void @_Z23atomic_store_seq_cst_i8RNSt3__16atomicIcEEc(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define void @_Z23atomic_store_seq_cst_u8RNSt3__16atomicIhEEh(%"struct.std::__1::atomic.5"* nocapture nonnull align 1 dereferenceable(1) %0, i8 zeroext %1) {
; CHECK-LABEL: _Z23atomic_store_seq_cst_u8RNSt3__16atomicIhEEh:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.5", %"struct.std::__1::atomic.5"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i8 %1, i8* %3 seq_cst, align 1
ret void
@ -417,11 +417,11 @@ define void @_Z23atomic_store_seq_cst_u8RNSt3__16atomicIhEEh(%"struct.std::__1::
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_i16RNSt3__16atomicIsEEs(%"struct.std::__1::atomic.10"* nocapture nonnull align 2 dereferenceable(2) %0, i16 signext %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_i16RNSt3__16atomicIsEEs:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.10", %"struct.std::__1::atomic.10"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 seq_cst, align 2
ret void
@ -430,11 +430,11 @@ define void @_Z24atomic_store_seq_cst_i16RNSt3__16atomicIsEEs(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_u16RNSt3__16atomicItEEt(%"struct.std::__1::atomic.15"* nocapture nonnull align 2 dereferenceable(2) %0, i16 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_u16RNSt3__16atomicItEEt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.15", %"struct.std::__1::atomic.15"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i16 %1, i16* %3 seq_cst, align 2
ret void
@ -443,11 +443,11 @@ define void @_Z24atomic_store_seq_cst_u16RNSt3__16atomicItEEt(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_i32RNSt3__16atomicIiEEi(%"struct.std::__1::atomic.20"* nocapture nonnull align 4 dereferenceable(4) %0, i32 signext %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_i32RNSt3__16atomicIiEEi:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.20", %"struct.std::__1::atomic.20"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 seq_cst, align 4
ret void
@ -456,11 +456,11 @@ define void @_Z24atomic_store_seq_cst_i32RNSt3__16atomicIiEEi(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_u32RNSt3__16atomicIjEEj(%"struct.std::__1::atomic.25"* nocapture nonnull align 4 dereferenceable(4) %0, i32 zeroext %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_u32RNSt3__16atomicIjEEj:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.25", %"struct.std::__1::atomic.25"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i32 %1, i32* %3 seq_cst, align 4
ret void
@ -469,11 +469,11 @@ define void @_Z24atomic_store_seq_cst_u32RNSt3__16atomicIjEEj(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_i64RNSt3__16atomicIlEEl(%"struct.std::__1::atomic.30"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_i64RNSt3__16atomicIlEEl:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.30", %"struct.std::__1::atomic.30"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 seq_cst, align 8
ret void
@ -482,11 +482,11 @@ define void @_Z24atomic_store_seq_cst_i64RNSt3__16atomicIlEEl(%"struct.std::__1:
; Function Attrs: nofree norecurse nounwind
define void @_Z24atomic_store_seq_cst_u64RNSt3__16atomicImEEm(%"struct.std::__1::atomic.35"* nocapture nonnull align 8 dereferenceable(8) %0, i64 %1) {
; CHECK-LABEL: _Z24atomic_store_seq_cst_u64RNSt3__16atomicImEEm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fencem 3
; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: fencem 3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = getelementptr inbounds %"struct.std::__1::atomic.35", %"struct.std::__1::atomic.35"* %0, i64 0, i32 0, i32 0, i32 0, i32 0, i32 0
store atomic i64 %1, i64* %3 seq_cst, align 8
ret void
@ -497,12 +497,12 @@ define void @_Z25atomic_store_seq_cst_i128RNSt3__16atomicInEEn(%"struct.std::__1
; CHECK-LABEL: _Z25atomic_store_seq_cst_i128RNSt3__16atomicInEEn:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9)
; CHECK-NEXT: st %s1, -16(, %s9)
; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 5, (0)1
; CHECK-NEXT: or %s1, 0, %s4
@ -523,12 +523,12 @@ define void @_Z25atomic_store_seq_cst_u128RNSt3__16atomicIoEEo(%"struct.std::__1
; CHECK-LABEL: _Z25atomic_store_seq_cst_u128RNSt3__16atomicIoEEo:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s4, 0, %s0
; CHECK-NEXT: st %s2, -8(, %s9)
; CHECK-NEXT: st %s1, -16(, %s9)
; CHECK-NEXT: st %s2, 248(, %s11)
; CHECK-NEXT: st %s1, 240(, %s11)
; CHECK-NEXT: lea %s0, __atomic_store@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, __atomic_store@hi(, %s0)
; CHECK-NEXT: lea %s2, -16(, %s9)
; CHECK-NEXT: lea %s2, 240(, %s11)
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s3, 5, (0)1
; CHECK-NEXT: or %s1, 0, %s4

16
llvm/test/CodeGen/VE/Scalar/bitcast.ll
View File

@ -3,8 +3,8 @@
; Function Attrs: noinline nounwind optnone
define dso_local i64 @bitcastd2l(double %x) {
; CHECK-LABEL: bitcastd2l:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK: # %bb.0:
; CHECK-NEXT: b.l.t (, %s10)
%r = bitcast double %x to i64
ret i64 %r
}
@ -12,8 +12,8 @@ define dso_local i64 @bitcastd2l(double %x) {
; Function Attrs: noinline nounwind optnone
define dso_local double @bitcastl2d(i64 %x) {
; CHECK-LABEL: bitcastl2d:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK: # %bb.0:
; CHECK-NEXT: b.l.t (, %s10)
%r = bitcast i64 %x to double
ret double %r
}
@ -21,9 +21,9 @@ define dso_local double @bitcastl2d(i64 %x) {
; Function Attrs: noinline nounwind optnone
define dso_local float @bitcastw2f(i32 %x) {
; CHECK-LABEL: bitcastw2f:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = bitcast i32 %x to float
ret float %r
}
@ -31,9 +31,9 @@ define dso_local float @bitcastw2f(i32 %x) {
; Function Attrs: noinline nounwind optnone
define dso_local i32 @bitcastf2w(float %x) {
; CHECK-LABEL: bitcastf2w:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = bitcast float %x to i32
ret i32 %r
}

64
llvm/test/CodeGen/VE/Scalar/bitreverse.ll
View File

@ -8,154 +8,154 @@ declare i8 @llvm.bitreverse.i8(i8)
define i128 @func128(i128 %p) {
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: brv %s2, %s1
; CHECK-NEXT: brv %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.bitreverse.i128(i128 %p)
ret i128 %r
}
define i64 @func64(i64 %p) {
; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.bitreverse.i64(i64 %p)
ret i64 %r
}
define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bitreverse.i32(i32 %p)
ret i32 %r
}
define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: srl %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bitreverse.i32(i32 %p)
ret i32 %r
}
define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bitreverse.i16(i16 %p)
ret i16 %r
}
define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: srl %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bitreverse.i16(i16 %p)
ret i16 %r
}
define signext i8 @func8s(i8 signext %p) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.bitreverse.i8(i8 %p)
ret i8 %r
}
define zeroext i8 @func8z(i8 zeroext %p) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: srl %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.bitreverse.i8(i8 %p)
ret i8 %r
}
define i128 @func128i() {
; CHECK-LABEL: func128i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: lea.sl %s1, -65536
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.bitreverse.i128(i128 65535)
ret i128 %r
}
define i64 @func64i() {
; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -65536
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.bitreverse.i64(i64 65535)
ret i64 %r
}
define signext i32 @func32is() {
; CHECK-LABEL: func32is:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -65536
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bitreverse.i32(i32 65535)
ret i32 %r
}
define zeroext i32 @func32iz() {
; CHECK-LABEL: func32iz:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -65536
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bitreverse.i32(i32 65535)
ret i32 %r
}
define signext i16 @func16is() {
; CHECK-LABEL: func16is:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -256
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bitreverse.i16(i16 255)
ret i16 %r
}
define zeroext i16 @func16iz() {
; CHECK-LABEL: func16iz:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 65280
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bitreverse.i16(i16 255)
ret i16 %r
}
define signext i8 @func8is() {
; CHECK-LABEL: func8is:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 15, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.bitreverse.i8(i8 240)
ret i8 %r
}
define zeroext i8 @func8iz() {
; CHECK-LABEL: func8iz:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 15, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.bitreverse.i8(i8 240)
ret i8 %r
}

4
llvm/test/CodeGen/VE/Scalar/blockaddress.ll
View File

@ -5,7 +5,7 @@
; Function Attrs: nofree norecurse nounwind writeonly
define void @test() {
; CHECK-LABEL: test:
; CHECK: .LBB0_3: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: .Ltmp0: # Block address taken
; CHECK-NEXT: # %bb.1: # %test1
; CHECK-NEXT: lea %s0, addr@lo
@ -15,7 +15,7 @@ define void @test() {
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, .Ltmp0@hi(, %s1)
; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
br label %test1

168
llvm/test/CodeGen/VE/Scalar/br_cc.ll
View File

@ -3,7 +3,7 @@
; Function Attrs: nounwind
define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) {
; CHECK-LABEL: br_cc_i1_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
@ -11,7 +11,7 @@ define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %0, %1
br i1 %3, label %5, label %4
@ -26,14 +26,14 @@ define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) {
; Function Attrs: nounwind
define void @br_cc_i8_var(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: br_cc_i8_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i8 %0, %1
br i1 %3, label %4, label %5
@ -48,14 +48,14 @@ define void @br_cc_i8_var(i8 signext %0, i8 signext %1) {
; Function Attrs: nounwind
define void @br_cc_u8_var(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: br_cc_u8_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i8 %0, %1
br i1 %3, label %4, label %5
@ -70,14 +70,14 @@ define void @br_cc_u8_var(i8 zeroext %0, i8 zeroext %1) {
; Function Attrs: nounwind
define void @br_cc_i16_var(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: br_cc_i16_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i16 %0, %1
br i1 %3, label %4, label %5
@ -92,14 +92,14 @@ define void @br_cc_i16_var(i16 signext %0, i16 signext %1) {
; Function Attrs: nounwind
define void @br_cc_u16_var(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: br_cc_u16_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i16 %0, %1
br i1 %3, label %4, label %5
@ -114,14 +114,14 @@ define void @br_cc_u16_var(i16 zeroext %0, i16 zeroext %1) {
; Function Attrs: nounwind
define void @br_cc_i32_var(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: br_cc_i32_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1
br i1 %3, label %4, label %5
@ -136,14 +136,14 @@ define void @br_cc_i32_var(i32 signext %0, i32 signext %1) {
; Function Attrs: nounwind
define void @br_cc_u32_var(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: br_cc_u32_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1
br i1 %3, label %4, label %5
@ -158,14 +158,14 @@ define void @br_cc_u32_var(i32 zeroext %0, i32 zeroext %1) {
; Function Attrs: nounwind
define void @br_cc_i64_var(i64 %0, i64 %1) {
; CHECK-LABEL: br_cc_i64_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1
br i1 %3, label %4, label %5
@ -180,14 +180,14 @@ define void @br_cc_i64_var(i64 %0, i64 %1) {
; Function Attrs: nounwind
define void @br_cc_u64_var(i64 %0, i64 %1) {
; CHECK-LABEL: br_cc_u64_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1
br i1 %3, label %4, label %5
@ -202,7 +202,7 @@ define void @br_cc_u64_var(i64 %0, i64 %1) {
; Function Attrs: nounwind
define void @br_cc_i128_var(i128 %0, i128 %1) {
; CHECK-LABEL: br_cc_i128_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
@ -212,7 +212,7 @@ define void @br_cc_i128_var(i128 %0, i128 %1) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i128 %0, %1
br i1 %3, label %4, label %5
@ -227,7 +227,7 @@ define void @br_cc_i128_var(i128 %0, i128 %1) {
; Function Attrs: nounwind
define void @br_cc_u128_var(i128 %0, i128 %1) {
; CHECK-LABEL: br_cc_u128_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
@ -237,7 +237,7 @@ define void @br_cc_u128_var(i128 %0, i128 %1) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i128 %0, %1
br i1 %3, label %4, label %5
@ -252,14 +252,14 @@ define void @br_cc_u128_var(i128 %0, i128 %1) {
; Function Attrs: nounwind
define void @br_cc_float_var(float %0, float %1) {
; CHECK-LABEL: br_cc_float_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.s %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq float %0, %1
br i1 %3, label %4, label %5
@ -274,14 +274,14 @@ define void @br_cc_float_var(float %0, float %1) {
; Function Attrs: nounwind
define void @br_cc_double_var(double %0, double %1) {
; CHECK-LABEL: br_cc_double_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.d %s0, %s1, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq double %0, %1
br i1 %3, label %4, label %5
@ -296,7 +296,7 @@ define void @br_cc_double_var(double %0, double %1) {
; Function Attrs: nounwind
define void @br_cc_quad_var(fp128 %0, fp128 %1) {
; CHECK-LABEL: br_cc_quad_var:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s2, %s0
; CHECK-NEXT: brne.d 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
@ -304,7 +304,7 @@ define void @br_cc_quad_var(fp128 %0, fp128 %1) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq fp128 %0, %1
br i1 %3, label %4, label %5
@ -319,14 +319,14 @@ define void @br_cc_quad_var(fp128 %0, fp128 %1) {
; Function Attrs: nounwind
define void @br_cc_i1_imm(i1 zeroext %0) {
; CHECK-LABEL: br_cc_i1_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %3, label %2
2: ; preds = %1
@ -340,14 +340,14 @@ define void @br_cc_i1_imm(i1 zeroext %0) {
; Function Attrs: nounwind
define void @br_cc_i8_imm(i8 signext %0) {
; CHECK-LABEL: br_cc_i8_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brlt.w -10, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i8 %0, -9
br i1 %2, label %3, label %4
@ -362,7 +362,7 @@ define void @br_cc_i8_imm(i8 signext %0) {
; Function Attrs: nounwind
define void @br_cc_u8_imm(i8 zeroext %0) {
; CHECK-LABEL: br_cc_u8_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 8, %s0
; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
@ -370,7 +370,7 @@ define void @br_cc_u8_imm(i8 zeroext %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i8 %0, 9
br i1 %2, label %3, label %4
@ -385,14 +385,14 @@ define void @br_cc_u8_imm(i8 zeroext %0) {
; Function Attrs: nounwind
define void @br_cc_i16_imm(i16 signext %0) {
; CHECK-LABEL: br_cc_i16_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brlt.w 62, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i16 %0, 63
br i1 %2, label %3, label %4
@ -407,7 +407,7 @@ define void @br_cc_i16_imm(i16 signext %0) {
; Function Attrs: nounwind
define void @br_cc_u16_imm(i16 zeroext %0) {
; CHECK-LABEL: br_cc_u16_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 63, %s0
; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
@ -415,7 +415,7 @@ define void @br_cc_u16_imm(i16 zeroext %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i16 %0, 64
br i1 %2, label %3, label %4
@ -430,14 +430,14 @@ define void @br_cc_u16_imm(i16 zeroext %0) {
; Function Attrs: nounwind
define void @br_cc_i32_imm(i32 signext %0) {
; CHECK-LABEL: br_cc_i32_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brlt.w 63, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i32 %0, 64
br i1 %2, label %3, label %4
@ -452,7 +452,7 @@ define void @br_cc_i32_imm(i32 signext %0) {
; Function Attrs: nounwind
define void @br_cc_u32_imm(i32 zeroext %0) {
; CHECK-LABEL: br_cc_u32_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 63, %s0
; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
@ -460,7 +460,7 @@ define void @br_cc_u32_imm(i32 zeroext %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i32 %0, 64
br i1 %2, label %3, label %4
@ -475,14 +475,14 @@ define void @br_cc_u32_imm(i32 zeroext %0) {
; Function Attrs: nounwind
define void @br_cc_i64_imm(i64 %0) {
; CHECK-LABEL: br_cc_i64_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brlt.l 63, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i64 %0, 64
br i1 %2, label %3, label %4
@ -497,7 +497,7 @@ define void @br_cc_i64_imm(i64 %0) {
; Function Attrs: nounwind
define void @br_cc_u64_imm(i64 %0) {
; CHECK-LABEL: br_cc_u64_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, 63, %s0
; CHECK-NEXT: brgt.l 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
@ -505,7 +505,7 @@ define void @br_cc_u64_imm(i64 %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i64 %0, 64
br i1 %2, label %3, label %4
@ -520,7 +520,7 @@ define void @br_cc_u64_imm(i64 %0) {
; Function Attrs: nounwind
define void @br_cc_i128_imm(i128 %0) {
; CHECK-LABEL: br_cc_i128_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
@ -534,7 +534,7 @@ define void @br_cc_i128_imm(i128 %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i128 %0, 64
br i1 %2, label %3, label %4
@ -549,7 +549,7 @@ define void @br_cc_i128_imm(i128 %0) {
; Function Attrs: nounwind
define void @br_cc_u128_imm(i128 %0) {
; CHECK-LABEL: br_cc_u128_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
@ -563,7 +563,7 @@ define void @br_cc_u128_imm(i128 %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i128 %0, 64
br i1 %2, label %3, label %4
@ -578,14 +578,14 @@ define void @br_cc_u128_imm(i128 %0) {
; Function Attrs: nounwind
define void @br_cc_float_imm(float %0) {
; CHECK-LABEL: br_cc_float_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brle.s 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast olt float %0, 0.000000e+00
br i1 %2, label %3, label %4
@ -600,14 +600,14 @@ define void @br_cc_float_imm(float %0) {
; Function Attrs: nounwind
define void @br_cc_double_imm(double %0) {
; CHECK-LABEL: br_cc_double_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brle.d 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast olt double %0, 0.000000e+00
br i1 %2, label %3, label %4
@ -622,7 +622,7 @@ define void @br_cc_double_imm(double %0) {
; Function Attrs: nounwind
define void @br_cc_quad_imm(fp128 %0) {
; CHECK-LABEL: br_cc_quad_imm:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
@ -635,7 +635,7 @@ define void @br_cc_quad_imm(fp128 %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast olt fp128 %0, 0xL00000000000000000000000000000000
br i1 %2, label %3, label %4
@ -650,14 +650,14 @@ define void @br_cc_quad_imm(fp128 %0) {
; Function Attrs: nounwind
define void @br_cc_imm_i1(i1 zeroext %0) {
; CHECK-LABEL: br_cc_imm_i1:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %2, label %3
2: ; preds = %1
@ -671,14 +671,14 @@ define void @br_cc_imm_i1(i1 zeroext %0) {
; Function Attrs: nounwind
define void @br_cc_imm_i8(i8 signext %0) {
; CHECK-LABEL: br_cc_imm_i8:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brgt.w -9, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i8 %0, -10
br i1 %2, label %3, label %4
@ -693,7 +693,7 @@ define void @br_cc_imm_i8(i8 signext %0) {
; Function Attrs: nounwind
define void @br_cc_imm_u8(i8 zeroext %0) {
; CHECK-LABEL: br_cc_imm_u8:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 9, %s0
; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
@ -701,7 +701,7 @@ define void @br_cc_imm_u8(i8 zeroext %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i8 %0, 8
br i1 %2, label %3, label %4
@ -716,14 +716,14 @@ define void @br_cc_imm_u8(i8 zeroext %0) {
; Function Attrs: nounwind
define void @br_cc_imm_i16(i16 signext %0) {
; CHECK-LABEL: br_cc_imm_i16:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brgt.w 63, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i16 %0, 62
br i1 %2, label %3, label %4
@ -738,7 +738,7 @@ define void @br_cc_imm_i16(i16 signext %0) {
; Function Attrs: nounwind
define void @br_cc_imm_u16(i16 zeroext %0) {
; CHECK-LABEL: br_cc_imm_u16:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 64
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
@ -747,7 +747,7 @@ define void @br_cc_imm_u16(i16 zeroext %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i16 %0, 63
br i1 %2, label %3, label %4
@ -762,14 +762,14 @@ define void @br_cc_imm_u16(i16 zeroext %0) {
; Function Attrs: nounwind
define void @br_cc_imm_i32(i32 signext %0) {
; CHECK-LABEL: br_cc_imm_i32:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brgt.w -64, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i32 %0, -65
br i1 %2, label %3, label %4
@ -784,7 +784,7 @@ define void @br_cc_imm_i32(i32 signext %0) {
; Function Attrs: nounwind
define void @br_cc_imm_u32(i32 zeroext %0) {
; CHECK-LABEL: br_cc_imm_u32:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, -64, %s0
; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
@ -792,7 +792,7 @@ define void @br_cc_imm_u32(i32 zeroext %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i32 %0, -65
br i1 %2, label %3, label %4
@ -807,14 +807,14 @@ define void @br_cc_imm_u32(i32 zeroext %0) {
; Function Attrs: nounwind
define void @br_cc_imm_i64(i64 %0) {
; CHECK-LABEL: br_cc_imm_i64:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brgt.l -64, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i64 %0, -65
br i1 %2, label %3, label %4
@ -829,7 +829,7 @@ define void @br_cc_imm_i64(i64 %0) {
; Function Attrs: nounwind
define void @br_cc_imm_u64(i64 %0) {
; CHECK-LABEL: br_cc_imm_u64:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, -64, %s0
; CHECK-NEXT: brlt.l 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
@ -837,7 +837,7 @@ define void @br_cc_imm_u64(i64 %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i64 %0, -65
br i1 %2, label %3, label %4
@ -852,7 +852,7 @@ define void @br_cc_imm_u64(i64 %0) {
; Function Attrs: nounwind
define void @br_cc_imm_i128(i128 %0) {
; CHECK-LABEL: br_cc_imm_i128:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, (0)0
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
@ -866,7 +866,7 @@ define void @br_cc_imm_i128(i128 %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i128 %0, -65
br i1 %2, label %3, label %4
@ -881,7 +881,7 @@ define void @br_cc_imm_i128(i128 %0) {
; Function Attrs: nounwind
define void @br_cc_imm_u128(i128 %0) {
; CHECK-LABEL: br_cc_imm_u128:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, (0)0
; CHECK-NEXT: or %s2, 0, (0)1
; CHECK-NEXT: or %s3, 0, (0)1
@ -895,7 +895,7 @@ define void @br_cc_imm_u128(i128 %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i128 %0, -65
br i1 %2, label %3, label %4
@ -910,14 +910,14 @@ define void @br_cc_imm_u128(i128 %0) {
; Function Attrs: nounwind
define void @br_cc_imm_float(float %0) {
; CHECK-LABEL: br_cc_imm_float:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brgt.s 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast ult float %0, 0.000000e+00
br i1 %2, label %4, label %3
@ -932,14 +932,14 @@ define void @br_cc_imm_float(float %0) {
; Function Attrs: nounwind
define void @br_cc_imm_double(double %0) {
; CHECK-LABEL: br_cc_imm_double:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brgt.d 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast ult double %0, 0.000000e+00
br i1 %2, label %4, label %3
@ -954,7 +954,7 @@ define void @br_cc_imm_double(double %0) {
; Function Attrs: nounwind
define void @br_cc_imm_quad(fp128 %0) {
; CHECK-LABEL: br_cc_imm_quad:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
@ -967,7 +967,7 @@ define void @br_cc_imm_quad(fp128 %0) {
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast ult fp128 %0, 0xL00000000000000000000000000000000
br i1 %2, label %4, label %3

45
llvm/test/CodeGen/VE/Scalar/br_jt.ll
View File

@ -3,31 +3,34 @@
; Function Attrs: norecurse nounwind readnone
define signext i32 @br_jt(i32 signext %0) {
; CHECK-LABEL: br_jt:
; CHECK: .LBB{{[0-9]+}}_11:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: brlt.w 2, %s0, .LBB{{[0-9]+}}_3
; CHECK-NEXT: brlt.w 2, %s0, .LBB{{[0-9]+}}_4
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: breq.w 1, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.8:
; CHECK-NEXT: brne.w 2, %s0, .LBB{{[0-9]+}}_9
; CHECK-NEXT: # %bb.6:
; CHECK-NEXT: breq.w 1, %s0, .LBB{{[0-9]+}}_8
; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: brne.w 2, %s0, .LBB{{[0-9]+}}_7
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_9
; CHECK-NEXT: .LBB{{[0-9]+}}_3:
; CHECK-NEXT: breq.w 3, %s0, .LBB{{[0-9]+}}_7
; CHECK-NEXT: # %bb.4:
; CHECK-NEXT: brne.w 4, %s0, .LBB{{[0-9]+}}_9
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: or %s0, 7, (0)1
; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_9
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_9
; CHECK-NEXT: .LBB{{[0-9]+}}_7:
; CHECK-NEXT: or %s0, 4, (0)1
; CHECK-NEXT: .LBB{{[0-9]+}}_9:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .LBB{{[0-9]+}}_4:
; CHECK-NEXT: breq.w 3, %s0, .LBB{{[0-9]+}}_9
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: brne.w 4, %s0, .LBB{{[0-9]+}}_7
; CHECK-NEXT: # %bb.6:
; CHECK-NEXT: or %s0, 7, (0)1
; CHECK-NEXT: .LBB{{[0-9]+}}_7:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .LBB{{[0-9]+}}_8:
; CHECK-NEXT: or %s0, 3, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .LBB{{[0-9]+}}_9:
; CHECK-NEXT: or %s0, 4, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
switch i32 %0, label %5 [
i32 1, label %6
i32 2, label %2

8
llvm/test/CodeGen/VE/Scalar/brcond.ll
View File

@ -3,14 +3,14 @@
; Function Attrs: nounwind
define void @brcond_then(i1 zeroext %0) {
; CHECK-LABEL: brcond_then:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %2, label %3
2: ; preds = %1
@ -24,14 +24,14 @@ define void @brcond_then(i1 zeroext %0) {
; Function Attrs: nounwind
define void @brcond_else(i1 zeroext %0) {
; CHECK-LABEL: brcond_else:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK: # %bb.0:
; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %3, label %2
2: ; preds = %1

11
llvm/test/CodeGen/VE/Scalar/brind.ll
View File

@ -3,7 +3,7 @@
; Function Attrs: norecurse nounwind readnone
define signext i32 @brind(i32 signext %0) {
; CHECK-LABEL: brind:
; CHECK: .LBB{{[0-9]+}}_6:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 1, (0)1
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: lea %s2, .Ltmp0@lo
@ -23,17 +23,18 @@ define signext i32 @brind(i32 signext %0) {
; CHECK-NEXT: .Ltmp0: # Block address taken
; CHECK-NEXT: .LBB{{[0-9]+}}_3:
; CHECK-NEXT: or %s0, -1, (0)1
; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_4
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .Ltmp2: # Block address taken
; CHECK-NEXT: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_4
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: .Ltmp1: # Block address taken
; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: .LBB{{[0-9]+}}_4: # %.split
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp eq i32 %0, 1
%3 = select i1 %2, i8* blockaddress(@brind, %6), i8* blockaddress(@brind, %8)
%4 = icmp eq i32 %0, 0

48
llvm/test/CodeGen/VE/Scalar/bswap.ll
View File

@ -7,121 +7,121 @@ declare i16 @llvm.bswap.i16(i16)
define i128 @func128(i128 %p) {
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s2, %s1, 0
; CHECK-NEXT: bswp %s1, %s0, 0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.bswap.i128(i128 %p)
ret i128 %r
}
define i64 @func64(i64 %p) {
; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s0, %s0, 0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.bswap.i64(i64 %p)
ret i64 %r
}
define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bswap.i32(i32 %p)
ret i32 %r
}
define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bswap.i32(i32 %p)
ret i32 %r
}
define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 16
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bswap.i16(i16 %p)
ret i16 %r
}
define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 16
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bswap.i16(i16 %p)
ret i16 %r
}
define i128 @func128i() {
; CHECK-LABEL: func128i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: lea.sl %s1, -16777216
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.bswap.i128(i128 255)
ret i128 %r
}
define i64 @func64i() {
; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -16777216
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.bswap.i64(i64 255)
ret i64 %r
}
define signext i32 @func32si() {
; CHECK-LABEL: func32si:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -16777216
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bswap.i32(i32 255)
ret i32 %r
}
define zeroext i32 @func32zi() {
; CHECK-LABEL: func32zi:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -16777216
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.bswap.i32(i32 255)
ret i32 %r
}
define signext i16 @func16si() {
; CHECK-LABEL: func16si:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -256
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bswap.i16(i16 255)
ret i16 %r
}
define zeroext i16 @func16zi() {
; CHECK-LABEL: func16zi:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 65280
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.bswap.i16(i16 255)
ret i16 %r
}

8
llvm/test/CodeGen/VE/Scalar/callstruct.ll
View File

@ -7,10 +7,10 @@
; Function Attrs: norecurse nounwind
define void @fun(%struct.a* noalias nocapture sret %a, i32 %p1, i32 %p2) {
; CHECK-LABEL: fun:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: stl %s2, 4(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%a.zero = getelementptr inbounds %struct.a, %struct.a* %a, i64 0, i32 0
store i32 %p1, i32* %a.zero, align 4
%a.one = getelementptr inbounds %struct.a, %struct.a* %a, i64 0, i32 1
@ -25,11 +25,11 @@ define void @caller() {
; CHECK-NEXT: lea %s0, callee@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, callee@hi(, %s0)
; CHECK-NEXT: lea %s0, -8(, %s9)
; CHECK-NEXT: lea %s0, 248(, %s11)
; CHECK-NEXT: or %s1, 3, (0)1
; CHECK-NEXT: or %s2, 4, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: ld %s0, -8(, %s9)
; CHECK-NEXT: ld %s0, 248(, %s11)
; CHECK-NEXT: lea %s1, A@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, A@hi(, %s1)

644
llvm/test/CodeGen/VE/Scalar/cast.ll
View File

File diff suppressed because it is too large Load Diff

168
llvm/test/CodeGen/VE/Scalar/constants.ll
View File

@ -2,351 +2,351 @@
define i8 @p0i8() {
; CHECK-LABEL: p0i8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i8 0
}
define signext i8 @p0si8() {
; CHECK-LABEL: p0si8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i8 0
}
define zeroext i8 @p0zi8() {
; CHECK-LABEL: p0zi8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i8 0
}
define i8 @p128i8() {
; CHECK-LABEL: p128i8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i8 128
}
define signext i8 @p128si8() {
; CHECK-LABEL: p128si8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -128
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i8 128
}
define zeroext i8 @p128zi8() {
; CHECK-LABEL: p128zi8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i8 128
}
define i8 @p256i8() {
; CHECK-LABEL: p256i8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i8 256
}
define signext i8 @p256si8() {
; CHECK-LABEL: p256si8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i8 256
}
define zeroext i8 @p256zi8() {
; CHECK-LABEL: p256zi8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i8 256
}
define i16 @p0i16() {
; CHECK-LABEL: p0i16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i16 0
}
define signext i16 @p0si16() {
; CHECK-LABEL: p0si16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i16 0
}
define zeroext i16 @p0zi16() {
; CHECK-LABEL: p0zi16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i16 0
}
define i32 @p0i32() {
; CHECK-LABEL: p0i32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i32 0
}
define signext i32 @p0si32() {
; CHECK-LABEL: p0si32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i32 0
}
define zeroext i32 @p0zi32() {
; CHECK-LABEL: p0zi32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i32 0
}
define i32 @p128i32() {
; CHECK-LABEL: p128i32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i32 128
}
define signext i32 @p128si32() {
; CHECK-LABEL: p128si32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i32 128
}
define zeroext i32 @p128zi32() {
; CHECK-LABEL: p128zi32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i32 128
}
define i64 @p0i64() {
; CHECK-LABEL: p0i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 0
}
define signext i64 @p0si64() {
; CHECK-LABEL: p0si64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 0
}
define zeroext i64 @p0zi64() {
; CHECK-LABEL: p0zi64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 0
}
define i64 @p128i64() {
; CHECK-LABEL: p128i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 128
}
define signext i64 @p128si64() {
; CHECK-LABEL: p128si64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 128
}
define zeroext i64 @p128zi64() {
; CHECK-LABEL: p128zi64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 128
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 128
}
define i64 @p2264924160i64() {
; CHECK-LABEL: p2264924160i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2030043136
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 2264924160
}
define signext i64 @p2264924160si64() {
; CHECK-LABEL: p2264924160si64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2030043136
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 2264924160
}
define zeroext i64 @p2264924160zi64() {
; CHECK-LABEL: p2264924160zi64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2030043136
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 2264924160
}
define i64 @p2147483647i64() {
; CHECK-LABEL: p2147483647i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 2147483647
}
define signext i64 @p2147483647si64() {
; CHECK-LABEL: p2147483647si64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 2147483647
}
define zeroext i64 @p2147483647zi64() {
; CHECK-LABEL: p2147483647zi64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 2147483647
}
define i64 @p15032385535i64() {
; CHECK-LABEL: p15032385535i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385535
}
define signext i64 @p15032385535si64() {
; CHECK-LABEL: p15032385535si64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385535
}
define zeroext i64 @p15032385535zi64() {
; CHECK-LABEL: p15032385535zi64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 2147483647
; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385535
}
define i64 @p15032385536i64() {
; CHECK-LABEL: p15032385536i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385536
}
define signext i64 @p15032385536si64() {
; CHECK-LABEL: p15032385536si64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385536
}
define zeroext i64 @p15032385536zi64() {
; CHECK-LABEL: p15032385536zi64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, 3(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret i64 15032385536
}
define float @m5f32() {
; CHECK-LABEL: m5f32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -1063256064
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float -5.000000e+00
}
define double @m5f64() {
; CHECK-LABEL: m5f64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -1072431104
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double -5.000000e+00
}
define float @p2p3f32() {
; CHECK-LABEL: p2p3f32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1075000115
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float 0x4002666660000000 ; 2.3
}
define double @p2p3f64() {
; CHECK-LABEL: p2p3f64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 1717986918
; CHECK-NEXT: lea.sl %s0, 1073899110(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double 2.3
}
define float @p128p3f32() {
; CHECK-LABEL: p128p3f32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1124093133
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float 0x40600999A0000000 ; 128.3
}
define double @p128p3f64() {
; CHECK-LABEL: p128p3f64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -1717986918
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, 1080035737(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double 128.3
}

96
llvm/test/CodeGen/VE/Scalar/ctlz.ll
View File

@ -8,265 +8,265 @@ declare i8 @llvm.ctlz.i8(i8, i1)
define i128 @func128(i128 %p){
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s2, %s1, (0)1
; CHECK-NEXT: ldz %s1, %s1
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, 64(, %s0)
; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 true)
ret i128 %r
}
define i64 @func64(i64 %p) {
; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.ctlz.i64(i64 %p, i1 true)
ret i64 %r
}
define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 true)
ret i32 %r
}
define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 true)
ret i32 %r
}
define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -16, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 true)
ret i16 %r
}
define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -16, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 true)
ret i16 %r
}
define signext i8 @func8s(i8 signext %p) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -24, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 true)
ret i8 %r
}
define zeroext i8 @func8z(i8 zeroext %p) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -24, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 true)
ret i8 %r
}
define i128 @func128i(){
; CHECK-LABEL: func128i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 112
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctlz.i128(i128 65535, i1 true)
ret i128 %r
}
define i64 @func64i() {
; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 48, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.ctlz.i64(i64 65535, i1 true)
ret i64 %r
}
define signext i32 @func32is() {
; CHECK-LABEL: func32is:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 65535, i1 true)
ret i32 %r
}
define zeroext i32 @func32iz() {
; CHECK-LABEL: func32iz:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 65535, i1 true)
ret i32 %r
}
define signext i16 @func16is() {
; CHECK-LABEL: func16is:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 255, i1 true)
ret i16 %r
}
define zeroext i16 @func16iz() {
; CHECK-LABEL: func16iz:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 255, i1 true)
ret i16 %r
}
define signext i8 @func8is() {
; CHECK-LABEL: func8is:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 255, i1 true)
ret i8 %r
}
define zeroext i8 @func8iz() {
; CHECK-LABEL: func8iz:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 255, i1 true)
ret i8 %r
}
define i128 @func128x(i128 %p){
; CHECK-LABEL: func128x:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s2, %s1, (0)1
; CHECK-NEXT: ldz %s1, %s1
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, 64(, %s0)
; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 false)
ret i128 %r
}
define i64 @func64x(i64 %p) {
; CHECK-LABEL: func64x:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.ctlz.i64(i64 %p, i1 false)
ret i64 %r
}
define signext i32 @func32sx(i32 signext %p) {
; CHECK-LABEL: func32sx:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 false)
ret i32 %r
}
define zeroext i32 @func32zx(i32 zeroext %p) {
; CHECK-LABEL: func32zx:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 false)
ret i32 %r
}
define signext i16 @func16sx(i16 signext %p) {
; CHECK-LABEL: func16sx:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -16, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 false)
ret i16 %r
}
define zeroext i16 @func16zx(i16 zeroext %p) {
; CHECK-LABEL: func16zx:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -16, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 false)
ret i16 %r
}
define signext i8 @func8sx(i8 signext %p) {
; CHECK-LABEL: func8sx:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -24, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 false)
ret i8 %r
}
define zeroext i8 @func8zx(i8 zeroext %p) {
; CHECK-LABEL: func8zx:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, -32(, %s0)
; CHECK-NEXT: adds.w.sx %s0, -24, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 false)
ret i8 %r
}

64
llvm/test/CodeGen/VE/Scalar/ctpop.ll
View File

@ -8,151 +8,151 @@ declare i8 @llvm.ctpop.i8(i8)
define i128 @func128(i128 %p) {
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: pcnt %s1, %s1
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: adds.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctpop.i128(i128 %p)
ret i128 %r
}
define i64 @func64(i64 %p) {
; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.ctpop.i64(i64 %p)
ret i64 %r
}
define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctpop.i32(i32 %p)
ret i32 %r
}
define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctpop.i32(i32 %p)
ret i32 %r
}
define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctpop.i16(i16 %p)
ret i16 %r
}
define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctpop.i16(i16 %p)
ret i16 %r
}
define signext i8 @func8s(i8 signext %p) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctpop.i8(i8 %p)
ret i8 %r
}
define zeroext i8 @func8z(i8 zeroext %p) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctpop.i8(i8 %p)
ret i8 %r
}
define i128 @func128i() {
; CHECK-LABEL: func128i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctpop.i128(i128 65535)
ret i128 %r
}
define i64 @func64i() {
; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.ctpop.i64(i64 65535)
ret i64 %r
}
define signext i32 @func32is() {
; CHECK-LABEL: func32is:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctpop.i32(i32 65535)
ret i32 %r
}
define zeroext i32 @func32iz() {
; CHECK-LABEL: func32iz:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.ctpop.i32(i32 65535)
ret i32 %r
}
define signext i16 @func16si() {
; CHECK-LABEL: func16si:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctpop.i16(i16 65535)
ret i16 %r
}
define zeroext i16 @func16zi() {
; CHECK-LABEL: func16zi:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 16, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.ctpop.i16(i16 65535)
ret i16 %r
}
define signext i8 @func8si() {
; CHECK-LABEL: func8si:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctpop.i8(i8 255)
ret i8 %r
}
define zeroext i8 @func8zi() {
; CHECK-LABEL: func8zi:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.ctpop.i8(i8 255)
ret i8 %r
}

64
llvm/test/CodeGen/VE/Scalar/cttz.ll
View File

@ -8,7 +8,7 @@ declare i8 @llvm.cttz.i8(i8, i1)
define i128 @func128(i128 %p) {
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s2, %s0, (0)1
; CHECK-NEXT: lea %s3, -1(, %s0)
; CHECK-NEXT: nnd %s0, %s0, %s3
@ -19,163 +19,163 @@ define i128 @func128(i128 %p) {
; CHECK-NEXT: lea %s0, 64(, %s0)
; CHECK-NEXT: cmov.l.ne %s0, %s3, %s2
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.cttz.i128(i128 %p, i1 true)
ret i128 %r
}
define i64 @func64(i64 %p) {
; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -1(, %s0)
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.cttz.i64(i64 %p, i1 true)
ret i64 %r
}
define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
ret i32 %r
}
define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
ret i32 %r
}
define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
ret i16 %r
}
define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
ret i16 %r
}
define signext i8 @func8s(i8 signext %p) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
ret i8 %r
}
define zeroext i8 @func8z(i8 zeroext %p) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
ret i8 %r
}
define i128 @func128i() {
; CHECK-LABEL: func128i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.cttz.i128(i128 65280, i1 true)
ret i128 %r
}
define i64 @func64i() {
; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i64 @llvm.cttz.i64(i64 65280, i1 true)
ret i64 %r
}
define signext i32 @func32is() {
; CHECK-LABEL: func32is:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.cttz.i32(i32 65280, i1 true)
ret i32 %r
}
define zeroext i32 @func32iz() {
; CHECK-LABEL: func32iz:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i32 @llvm.cttz.i32(i32 65280, i1 true)
ret i32 %r
}
define signext i16 @func16is() {
; CHECK-LABEL: func16is:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.cttz.i16(i16 65280, i1 true)
ret i16 %r
}
define zeroext i16 @func16iz() {
; CHECK-LABEL: func16iz:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i16 @llvm.cttz.i16(i16 65280, i1 true)
ret i16 %r
}
define signext i8 @func8is() {
; CHECK-LABEL: func8is:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 4, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.cttz.i8(i8 240, i1 true)
ret i8 %r
}
define zeroext i8 @func8iz() {
; CHECK-LABEL: func8iz:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 4, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i8 @llvm.cttz.i8(i8 240, i1 true)
ret i8 %r
}

64
llvm/test/CodeGen/VE/Scalar/div.ll
View File

@ -16,9 +16,9 @@ define i128 @divi128(i128, i128) {
; Function Attrs: norecurse nounwind readnone
define i64 @divi64(i64 %a, i64 %b) {
; CHECK-LABEL: divi64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i64 %a, %b
ret i64 %r
}
@ -26,10 +26,10 @@ define i64 @divi64(i64 %a, i64 %b) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @divi32(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: divi32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i32 %a, %b
ret i32 %r
}
@ -50,9 +50,9 @@ define i128 @divu128(i128, i128) {
; Function Attrs: norecurse nounwind readnone
define i64 @divu64(i64 %a, i64 %b) {
; CHECK-LABEL: divu64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i64 %a, %b
ret i64 %r
}
@ -60,10 +60,10 @@ define i64 @divu64(i64 %a, i64 %b) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @divu32(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: divu32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i32 %a, %b
ret i32 %r
}
@ -71,11 +71,11 @@ define zeroext i32 @divu32(i32 zeroext %a, i32 zeroext %b) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @divi16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: divi16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%a32 = sext i16 %a to i32
%b32 = sext i16 %b to i32
%r32 = sdiv i32 %a32, %b32
@ -86,10 +86,10 @@ define signext i16 @divi16(i16 signext %a, i16 signext %b) {
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: divu16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i16 %a, %b
ret i16 %r
}
@ -97,11 +97,11 @@ define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) {
; Function Attrs: norecurse nounwind readnone
define signext i8 @divi8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: divi8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%a32 = sext i8 %a to i32
%b32 = sext i8 %b to i32
%r32 = sdiv i32 %a32, %b32
@ -112,10 +112,10 @@ define signext i8 @divi8(i8 signext %a, i8 signext %b) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @divu8(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: divu8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i8 %a, %b
ret i8 %r
}
@ -138,9 +138,9 @@ define i128 @divi128ri(i128) {
; Function Attrs: norecurse nounwind readnone
define i64 @divi64ri(i64 %a, i64 %b) {
; CHECK-LABEL: divi64ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s0, %s0, (62)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i64 %a, 3
ret i64 %r
}
@ -148,10 +148,10 @@ define i64 @divi64ri(i64 %a, i64 %b) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @divi32ri(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: divi32ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, %s0, (62)0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i32 %a, 3
ret i32 %r
}
@ -174,9 +174,9 @@ define i128 @divu128ri(i128) {
; Function Attrs: norecurse nounwind readnone
define i64 @divu64ri(i64 %a, i64 %b) {
; CHECK-LABEL: divu64ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s0, %s0, (62)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i64 %a, 3
ret i64 %r
}
@ -184,10 +184,10 @@ define i64 @divu64ri(i64 %a, i64 %b) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @divu32ri(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: divu32ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, %s0, (62)0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i32 %a, 3
ret i32 %r
}
@ -212,9 +212,9 @@ define i128 @divi128li(i128) {
; Function Attrs: norecurse nounwind readnone
define i64 @divi64li(i64 %a, i64 %b) {
; CHECK-LABEL: divi64li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s0, 3, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i64 3, %b
ret i64 %r
}
@ -222,10 +222,10 @@ define i64 @divi64li(i64 %a, i64 %b) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @divi32li(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: divi32li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, 3, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i32 3, %b
ret i32 %r
}
@ -250,9 +250,9 @@ define i128 @divu128li(i128) {
; Function Attrs: norecurse nounwind readnone
define i64 @divu64li(i64 %a, i64 %b) {
; CHECK-LABEL: divu64li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s0, 3, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i64 3, %b
ret i64 %r
}
@ -260,10 +260,10 @@ define i64 @divu64li(i64 %a, i64 %b) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @divu32li(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: divu32li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, 3, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = udiv i32 3, %b
ret i32 %r
}

32
llvm/test/CodeGen/VE/Scalar/fabs.ll
View File

@ -30,11 +30,11 @@
; Function Attrs: nounwind readnone
define float @fabs_float_var(float %0) {
; CHECK-LABEL: fabs_float_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: and %s0, %s0, (33)0
; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast float @llvm.fabs.f32(float %0)
ret float %2
}
@ -45,9 +45,9 @@ declare float @llvm.fabs.f32(float)
; Function Attrs: nounwind readnone
define double @fabs_double_var(double %0) {
; CHECK-LABEL: fabs_double_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (1)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast double @llvm.fabs.f64(double %0)
ret double %2
}
@ -77,62 +77,62 @@ declare fp128 @llvm.fabs.f128(fp128)
; Function Attrs: norecurse nounwind readnone
define float @fabs_float_zero() {
; CHECK-LABEL: fabs_float_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float 0.000000e+00
}
; Function Attrs: norecurse nounwind readnone
define double @fabs_double_zero() {
; CHECK-LABEL: fabs_double_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double 0.000000e+00
}
; Function Attrs: norecurse nounwind readnone
define fp128 @fabs_quad_zero() {
; CHECK-LABEL: fabs_quad_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0)
; CHECK-NEXT: ld %s0, 8(, %s2)
; CHECK-NEXT: ld %s1, (, %s2)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret fp128 0xL00000000000000000000000000000000
}
; Function Attrs: norecurse nounwind readnone
define float @fabs_float_const() {
; CHECK-LABEL: fabs_float_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1073741824
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float 2.000000e+00
}
; Function Attrs: norecurse nounwind readnone
define double @fabs_double_const() {
; CHECK-LABEL: fabs_double_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1073741824
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double 2.000000e+00
}
; Function Attrs: nounwind readnone
define fp128 @fabs_quad_const() {
; CHECK-LABEL: fabs_quad_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s0)
; CHECK-NEXT: ld %s0, 8(, %s2)
; CHECK-NEXT: ld %s1, (, %s2)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = tail call fast fp128 @llvm.fabs.f128(fp128 0xL0000000000000000C000000000000000)
ret fp128 %1
}

24
llvm/test/CodeGen/VE/Scalar/fcopysign.ll
View File

@ -31,7 +31,7 @@
; Function Attrs: nounwind readnone
define float @copysign_float_var(float %0, float %1) {
; CHECK-LABEL: copysign_float_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s1, %s1, 32
; CHECK-NEXT: lea %s2, -2147483648
; CHECK-NEXT: and %s2, %s2, (32)0
@ -40,7 +40,7 @@ define float @copysign_float_var(float %0, float %1) {
; CHECK-NEXT: and %s0, %s0, (33)0
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast float @llvm.copysign.f32(float %0, float %1)
ret float %3
}
@ -51,11 +51,11 @@ declare float @llvm.copysign.f32(float, float)
; Function Attrs: nounwind readnone
define double @copysign_double_var(double %0, double %1) {
; CHECK-LABEL: copysign_double_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (1)1
; CHECK-NEXT: and %s0, %s0, (1)0
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast double @llvm.copysign.f64(double %0, double %1)
ret double %3
}
@ -91,13 +91,13 @@ declare fp128 @llvm.copysign.f128(fp128, fp128)
; Function Attrs: nounwind readnone
define float @copysign_float_zero(float %0) {
; CHECK-LABEL: copysign_float_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast float @llvm.copysign.f32(float 0.000000e+00, float %0)
ret float %2
}
@ -105,9 +105,9 @@ define float @copysign_float_zero(float %0) {
; Function Attrs: nounwind readnone
define double @copysign_double_zero(double %0) {
; CHECK-LABEL: copysign_double_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (1)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast double @llvm.copysign.f64(double 0.000000e+00, double %0)
ret double %2
}
@ -142,7 +142,7 @@ define fp128 @copysign_quad_zero(fp128 %0) {
; Function Attrs: nounwind readnone
define float @copysign_float_const(float %0) {
; CHECK-LABEL: copysign_float_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0
@ -150,7 +150,7 @@ define float @copysign_float_const(float %0) {
; CHECK-NEXT: lea %s1, 1073741824
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast float @llvm.copysign.f32(float -2.000000e+00, float %0)
ret float %2
}
@ -158,11 +158,11 @@ define float @copysign_float_const(float %0) {
; Function Attrs: nounwind readnone
define double @copysign_double_const(double %0) {
; CHECK-LABEL: copysign_double_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (1)1
; CHECK-NEXT: lea.sl %s1, 1073741824
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call fast double @llvm.copysign.f64(double -2.000000e+00, double %0)
ret double %2
}

16
llvm/test/CodeGen/VE/Scalar/fcos.ll
View File

@ -80,18 +80,18 @@ declare fp128 @llvm.cos.f128(fp128)
; Function Attrs: norecurse nounwind readnone
define float @fcos_float_zero() {
; CHECK-LABEL: fcos_float_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1065353216
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float 1.000000e+00
}
; Function Attrs: norecurse nounwind readnone
define double @fcos_double_zero() {
; CHECK-LABEL: fcos_double_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 1072693248
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double 1.000000e+00
}
@ -116,19 +116,19 @@ define fp128 @fcos_quad_zero() {
; Function Attrs: norecurse nounwind readnone
define float @fcos_float_const() {
; CHECK-LABEL: fcos_float_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -1093332685
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float 0xBFDAA22660000000
}
; Function Attrs: norecurse nounwind readnone
define double @fcos_double_const() {
; CHECK-LABEL: fcos_double_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 1465086469
; CHECK-NEXT: lea.sl %s0, -1076190682(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double 0xBFDAA22657537205
}

48
llvm/test/CodeGen/VE/Scalar/fp_add.ll
View File

@ -2,129 +2,129 @@
define float @func1(float %a, float %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, %b
ret float %r
}
define double @func2(double %a, double %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, %b
ret double %r
}
define fp128 @func3(fp128 %a, fp128 %b) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fadd.q %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, %b
ret fp128 %r
}
define float @func4(float %a) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1084227584
; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, 5.000000e+00
ret float %r
}
define double @func5(double %a) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1075052544
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, 5.000000e+00
ret double %r
}
define fp128 @func6(fp128 %a) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fadd.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, 0xL00000000000000004001400000000000
ret fp128 %r
}
define float @func7(float %a) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 2139095039
; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, 0x47EFFFFFE0000000
ret float %r
}
define double @func8(double %a) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1)
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, 0x7FEFFFFFFFFFFFFF
ret double %r
}
define fp128 @func9(fp128 %a) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fadd.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF
ret fp128 %r
}
define float @fadds_imm(float %a) {
; CHECK-LABEL: fadds_imm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fadd.s %s0, %s0, (2)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, -2.e+00
ret float %r
}
define double @faddd_imm(double %a) {
; CHECK-LABEL: faddd_imm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fadd.d %s0, %s0, (2)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, -2.e+00
ret double %r
}
define fp128 @faddq_imm(fp128 %a) {
; CHECK-LABEL: faddq_imm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fadd.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, 0xLA0000000000000000000000000000000
ret fp128 %r
}

24
llvm/test/CodeGen/VE/Scalar/fp_div.ll
View File

@ -2,18 +2,18 @@
define float @func1(float %a, float %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fdiv.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv float %a, %b
ret float %r
}
define double @func2(double %a, double %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fdiv.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv double %a, %b
ret double %r
}
@ -32,20 +32,20 @@ define fp128 @func3(fp128 %a, fp128 %b) {
define float @func4(float %a) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1084227584
; CHECK-NEXT: fdiv.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv float %a, 5.000000e+00
ret float %r
}
define double @func5(double %a) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1075052544
; CHECK-NEXT: fdiv.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv double %a, 5.000000e+00
ret double %r
}
@ -69,22 +69,22 @@ define fp128 @func6(fp128 %a) {
define float @func7(float %a) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 2139095039
; CHECK-NEXT: fdiv.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv float %a, 0x47EFFFFFE0000000
ret float %r
}
define double @func8(double %a) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1)
; CHECK-NEXT: fdiv.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fdiv double %a, 0x7FEFFFFFFFFFFFFF
ret double %r
}

28
llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll
View File

@ -67,7 +67,7 @@ define double @func_fp16fp64(half* %a) {
define void @func_fp32i16(i16* %fl.ptr, float %val) {
; CHECK-LABEL: func_fp32i16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill
; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __gnu_f2h_ieee@lo
; CHECK-NEXT: and %s0, %s0, (32)0
@ -75,7 +75,7 @@ define void @func_fp32i16(i16* %fl.ptr, float %val) {
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: st2b %s0, (, %s18)
; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload
; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9
%val.asf = call i16 @llvm.convert.to.fp16.f32(float %val)
store i16 %val.asf, i16* %fl.ptr
@ -85,8 +85,8 @@ define void @func_fp32i16(i16* %fl.ptr, float %val) {
define half @func_fp32fp16(half* %fl.ptr, float %a) {
; CHECK-LABEL: func_fp32fp16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill
; CHECK-NEXT: st %s19, 56(, %s9) # 8-byte Folded Spill
; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: st %s19, 296(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __gnu_f2h_ieee@lo
; CHECK-NEXT: and %s0, %s0, (32)0
@ -100,8 +100,8 @@ define half @func_fp32fp16(half* %fl.ptr, float %a) {
; CHECK-NEXT: or %s0, 0, %s19
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: st2b %s19, (, %s18)
; CHECK-NEXT: ld %s19, 56(, %s9) # 8-byte Folded Reload
; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload
; CHECK-NEXT: ld %s19, 296(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9
%a.asd = fptrunc float %a to half
store half %a.asd, half* %fl.ptr
@ -110,10 +110,10 @@ define half @func_fp32fp16(half* %fl.ptr, float %a) {
define double @func_fp32fp64(float* %a) {
; CHECK-LABEL: func_fp32fp64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%a.val = load float, float* %a, align 4
%a.asd = fpext float %a.val to double
ret double %a.asd
@ -122,7 +122,7 @@ define double @func_fp32fp64(float* %a) {
define void @func_fp64i16(i16* %fl.ptr, double %val) {
; CHECK-LABEL: func_fp64i16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill
; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __truncdfhf2@lo
; CHECK-NEXT: and %s0, %s0, (32)0
@ -130,7 +130,7 @@ define void @func_fp64i16(i16* %fl.ptr, double %val) {
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: st2b %s0, (, %s18)
; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload
; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9
%val.asf = call i16 @llvm.convert.to.fp16.f64(double %val)
store i16 %val.asf, i16* %fl.ptr
@ -140,7 +140,7 @@ define void @func_fp64i16(i16* %fl.ptr, double %val) {
define void @func_fp64fp16(half* %fl.ptr, double %val) {
; CHECK-LABEL: func_fp64fp16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill
; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __truncdfhf2@lo
; CHECK-NEXT: and %s0, %s0, (32)0
@ -148,7 +148,7 @@ define void @func_fp64fp16(half* %fl.ptr, double %val) {
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: st2b %s0, (, %s18)
; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload
; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9
%val.asf = fptrunc double %val to half
store half %val.asf, half* %fl.ptr
@ -157,10 +157,10 @@ define void @func_fp64fp16(half* %fl.ptr, double %val) {
define void @func_fp64fp32(float* %fl.ptr, double %val) {
; CHECK-LABEL: func_fp64fp32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cvt.s.d %s1, %s1
; CHECK-NEXT: stu %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%val.asf = fptrunc double %val to float
store float %val.asf, float* %fl.ptr
ret void

8
llvm/test/CodeGen/VE/Scalar/fp_fneg.ll
View File

@ -28,13 +28,13 @@
; Function Attrs: norecurse nounwind readnone
define float @fneg_float(float %0) {
; CHECK-LABEL: fneg_float:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 32
; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = fneg float %0
ret float %2
}
@ -42,9 +42,9 @@ define float @fneg_float(float %0) {
; Function Attrs: norecurse nounwind readnone
define double @fneg_double(double %0) {
; CHECK-LABEL: fneg_double:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, (1)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = fneg double %0
ret double %2
}

52
llvm/test/CodeGen/VE/Scalar/fp_mul.ll
View File

@ -2,133 +2,133 @@
define float @func1(float %a, float %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmul.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, %b
ret float %r
}
define double @func2(double %a, double %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmul.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul double %a, %b
ret double %r
}
define fp128 @func3(fp128 %a, fp128 %b) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmul.q %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul fp128 %a, %b
ret fp128 %r
}
define float @func4(float %a) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1084227584
; CHECK-NEXT: fmul.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, 5.000000e+00
ret float %r
}
define double @func5(double %a) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 1075052544
; CHECK-NEXT: fmul.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul double %a, 5.000000e+00
ret double %r
}
define fp128 @func6(fp128 %a) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fmul.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul fp128 %a, 0xL00000000000000004001400000000000
ret fp128 %r
}
define float @func7(float %a) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 2139095039
; CHECK-NEXT: fmul.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, 0x47EFFFFFE0000000
ret float %r
}
define double @func8(double %a) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, 2146435071(, %s1)
; CHECK-NEXT: fmul.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul double %a, 0x7FEFFFFFFFFFFFFF
ret double %r
}
define fp128 @func9(fp128 %a) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fmul.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul fp128 %a, 0xLFFFFFFFFFFFFFFFF7FFEFFFFFFFFFFFF
ret fp128 %r
}
define float @fmuls_ir(float %a) {
; CHECK-LABEL: fmuls_ir:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmul.s %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float 0.e+00, %a
ret float %r
}
define float @fmuls_ri(float %a) {
; CHECK-LABEL: fmuls_ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmul.s %s0, %s0, (2)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, -2.
ret float %r
}
define float @fmuls_ri2(float %a) {
; CHECK-LABEL: fmuls_ri2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmul.s %s0, %s0, (3)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, -36893488147419103232.
ret float %r
}
define float @fmuls_ri3(float %a) {
; CHECK-LABEL: fmuls_ri3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmul.s %s0, %s0, (9)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fmul float %a, 1.175494210692441075487029444849287348827052428745893333857174530571588870475618904265502351336181163787841796875E-38
ret float %r
}

44
llvm/test/CodeGen/VE/Scalar/fp_sub.ll
View File

@ -2,115 +2,115 @@
define float @func1(float %a, float %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fsub.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fsub float %a, %b
ret float %r
}
define double @func2(double %a, double %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fsub.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fsub double %a, %b
ret double %r
}
define fp128 @func3(fp128 %a, fp128 %b) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fsub.q %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fsub fp128 %a, %b
ret fp128 %r
}
define float @func4(float %a) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, -1063256064
; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, -5.000000e+00
ret float %r
}
define double @func5(double %a) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, -1072431104
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, -5.000000e+00
ret double %r
}
define fp128 @func6(fp128 %a) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fadd.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, 0xL0000000000000000C001400000000000
ret fp128 %r
}
define float @func7(float %a) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, -8388609
; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd float %a, 0xC7EFFFFFE0000000
ret float %r
}
define double @func8(double %a) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, -1048577(, %s1)
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd double %a, 0xFFEFFFFFFFFFFFFF
ret double %r
}
define fp128 @func9(fp128 %a) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0@hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fadd.q %s0, %s0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fadd fp128 %a, 0xLFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFF
ret fp128 %r
}
define float @fsubs_ir(float %a) {
; CHECK-LABEL: fsubs_ir:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fsub.s %s0, 0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fsub float 0.e+00, %a
ret float %r
}
define float @fsubs_ri(float %a) {
; CHECK-LABEL: fsubs_ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fadd.s %s0, %s0, (2)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = fsub float %a, 2.0e+00
ret float %r
}

64
llvm/test/CodeGen/VE/Scalar/fp_to_int.ll
View File

@ -3,10 +3,10 @@
; Function Attrs: norecurse nounwind readnone
define signext i8 @f2c(float %a) {
; CHECK-LABEL: f2c:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptosi float %a to i8
ret i8 %conv
@ -15,10 +15,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i16 @f2s(float %a) {
; CHECK-LABEL: f2s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptosi float %a to i16
ret i16 %conv
@ -27,9 +27,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i32 @f2i(float %a) {
; CHECK-LABEL: f2i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptosi float %a to i32
ret i32 %conv
@ -38,10 +38,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @f2l(float %a) {
; CHECK-LABEL: f2l:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptosi float %a to i64
ret i64 %conv
@ -50,10 +50,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @f2uc(float %a) {
; CHECK-LABEL: f2uc:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptoui float %a to i8
ret i8 %conv
@ -62,10 +62,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @f2us(float %a) {
; CHECK-LABEL: f2us:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptoui float %a to i16
ret i16 %conv
@ -74,10 +74,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i32 @f2ui(float %a) {
; CHECK-LABEL: f2ui:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptoui float %a to i32
ret i32 %conv
@ -86,7 +86,7 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @f2ul(float %a) {
; CHECK-LABEL: f2ul:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea.sl %s1, 1593835520
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: fsub.s %s1, %s0, %s1
@ -97,7 +97,7 @@ define i64 @f2ul(float %a) {
; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: cmov.s.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptoui float %a to i64
ret i64 %conv
@ -106,10 +106,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i8 @d2c(double %a) {
; CHECK-LABEL: d2c:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptosi double %a to i8
ret i8 %conv
@ -118,10 +118,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i16 @d2s(double %a) {
; CHECK-LABEL: d2s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptosi double %a to i16
ret i16 %conv
@ -130,9 +130,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i32 @d2i(double %a) {
; CHECK-LABEL: d2i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptosi double %a to i32
ret i32 %conv
@ -141,9 +141,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @d2l(double %a) {
; CHECK-LABEL: d2l:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptosi double %a to i64
ret i64 %conv
@ -152,10 +152,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @d2uc(double %a) {
; CHECK-LABEL: d2uc:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptoui double %a to i8
ret i8 %conv
@ -164,10 +164,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @d2us(double %a) {
; CHECK-LABEL: d2us:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptoui double %a to i16
ret i16 %conv
@ -176,9 +176,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i32 @d2ui(double %a) {
; CHECK-LABEL: d2ui:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptoui double %a to i32
ret i32 %conv
@ -187,7 +187,7 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @d2ul(double %a) {
; CHECK-LABEL: d2ul:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea.sl %s1, 1138753536
; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: fsub.d %s1, %s0, %s1
@ -196,7 +196,7 @@ define i64 @d2ul(double %a) {
; CHECK-NEXT: cvt.l.d.rz %s0, %s0
; CHECK-NEXT: cmov.d.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = fptoui double %a to i64
ret i64 %conv

16
llvm/test/CodeGen/VE/Scalar/fsin.ll
View File

@ -80,18 +80,18 @@ declare fp128 @llvm.sin.f128(fp128)
; Function Attrs: norecurse nounwind readnone
define float @fsin_float_zero() {
; CHECK-LABEL: fsin_float_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float 0.000000e+00
}
; Function Attrs: norecurse nounwind readnone
define double @fsin_double_zero() {
; CHECK-LABEL: fsin_double_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double 0.000000e+00
}
@ -116,20 +116,20 @@ define fp128 @fsin_quad_zero() {
; Function Attrs: norecurse nounwind readnone
define float @fsin_float_const() {
; CHECK-LABEL: fsin_float_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -1083652169
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float 0xBFED18F6E0000000
}
; Function Attrs: norecurse nounwind readnone
define double @fsin_double_const() {
; CHECK-LABEL: fsin_double_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -355355578
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, -1074980618(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double 0xBFED18F6EAD1B446
}

16
llvm/test/CodeGen/VE/Scalar/fsqrt.ll
View File

@ -81,18 +81,18 @@ declare fp128 @llvm.sqrt.f128(fp128)
; Function Attrs: norecurse nounwind readnone
define float @fsqrt_float_zero() {
; CHECK-LABEL: fsqrt_float_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float 0.000000e+00
}
; Function Attrs: norecurse nounwind readnone
define double @fsqrt_double_zero() {
; CHECK-LABEL: fsqrt_double_zero:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, 0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double 0.000000e+00
}
@ -117,18 +117,18 @@ define fp128 @fsqrt_quad_zero() {
; Function Attrs: norecurse nounwind readnone
define float @fsqrt_float_const() {
; CHECK-LABEL: fsqrt_float_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -4194304
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret float 0xFFF8000000000000
}
; Function Attrs: norecurse nounwind readnone
define double @fsqrt_double_const() {
; CHECK-LABEL: fsqrt_double_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s0, -524288
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret double 0xFFF8000000000000
}

132
llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll Normal file
View File

@ -0,0 +1,132 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve | FileCheck %s
; RUN: llc < %s -mtriple=ve -relocation-model=pic \
; RUN: | FileCheck -check-prefix=PIC %s
define void @func() {
; CHECK-LABEL: func:
; CHECK: # %bb.0:
; CHECK-NEXT: b.l.t (, %s10)
;
; PIC-LABEL: func:
; PIC: # %bb.0:
; PIC-NEXT: b.l.t (, %s10)
ret void
}
@vi8 = common dso_local local_unnamed_addr global i8 0, align 1
define i8 @func_gv() {
; CHECK-LABEL: func_gv:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: b.l.t (, %s10)
;
; PIC-LABEL: func_gv:
; PIC: # %bb.0:
; PIC-NEXT: st %s9, (, %s11)
; PIC-NEXT: st %s10, 8(, %s11)
; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: or %s9, 0, %s11
; PIC-NEXT: lea %s13, -176
; PIC-NEXT: and %s13, %s13, (32)0
; PIC-NEXT: lea.sl %s11, -1(%s13, %s11)
; PIC-NEXT: brge.l.t %s11, %s8, .LBB1_2
; PIC-NEXT: # %bb.1:
; PIC-NEXT: ld %s61, 24(, %s14)
; PIC-NEXT: or %s62, 0, %s0
; PIC-NEXT: lea %s63, 315
; PIC-NEXT: shm.l %s63, (%s61)
; PIC-NEXT: shm.l %s8, 8(%s61)
; PIC-NEXT: shm.l %s11, 16(%s61)
; PIC-NEXT: monc
; PIC-NEXT: or %s0, 0, %s62
; PIC-NEXT: .LBB1_2:
; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; PIC-NEXT: and %s15, %s15, (32)0
; PIC-NEXT: sic %s16
; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
; PIC-NEXT: lea %s0, vi8@got_lo
; PIC-NEXT: and %s0, %s0, (32)0
; PIC-NEXT: lea.sl %s0, vi8@got_hi(, %s0)
; PIC-NEXT: ld %s0, (%s0, %s15)
; PIC-NEXT: ld1b.zx %s0, (, %s0)
; PIC-NEXT: or %s11, 0, %s9
; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: ld %s10, 8(, %s11)
; PIC-NEXT: ld %s9, (, %s11)
; PIC-NEXT: b.l.t (, %s10)
%v = load i8, i8* @vi8, align 1
ret i8 %v
}
define i32 @func_alloca(i32 signext %0) {
; CHECK-LABEL: func_alloca:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: st %s15, 24(, %s11)
; CHECK-NEXT: st %s16, 32(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s13, -192
; CHECK-NEXT: and %s13, %s13, (32)0
; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: stl %s0, 188(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s16, 32(, %s11)
; CHECK-NEXT: ld %s15, 24(, %s11)
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
;
; PIC-LABEL: func_alloca:
; PIC: # %bb.0:
; PIC-NEXT: st %s9, (, %s11)
; PIC-NEXT: st %s10, 8(, %s11)
; PIC-NEXT: st %s15, 24(, %s11)
; PIC-NEXT: st %s16, 32(, %s11)
; PIC-NEXT: or %s9, 0, %s11
; PIC-NEXT: lea %s13, -192
; PIC-NEXT: and %s13, %s13, (32)0
; PIC-NEXT: lea.sl %s11, -1(%s13, %s11)
; PIC-NEXT: brge.l.t %s11, %s8, .LBB2_2
; PIC-NEXT: # %bb.1:
; PIC-NEXT: ld %s61, 24(, %s14)
; PIC-NEXT: or %s62, 0, %s0
; PIC-NEXT: lea %s63, 315
; PIC-NEXT: shm.l %s63, (%s61)
; PIC-NEXT: shm.l %s8, 8(%s61)
; PIC-NEXT: shm.l %s11, 16(%s61)
; PIC-NEXT: monc
; PIC-NEXT: or %s0, 0, %s62
; PIC-NEXT: .LBB2_2:
; PIC-NEXT: stl %s0, 188(, %s11)
; PIC-NEXT: or %s11, 0, %s9
; PIC-NEXT: ld %s16, 32(, %s11)
; PIC-NEXT: ld %s15, 24(, %s11)
; PIC-NEXT: ld %s10, 8(, %s11)
; PIC-NEXT: ld %s9, (, %s11)
; PIC-NEXT: b.l.t (, %s10)
%2 = alloca i32, align 4
store i32 %0, i32* %2, align 4
%3 = load i32, i32* %2, align 4
ret i32 %3
}

20
llvm/test/CodeGen/VE/Scalar/inlineasm-lea.ll
View File

@ -2,55 +2,55 @@
define i64 @lea1a(i64 %x) nounwind {
; CHECK-LABEL: lea1a:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s0, (%s0)
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%asmtmp = tail call i64 asm "lea $0, ($1)", "=r,r"(i64 %x) nounwind
ret i64 %asmtmp
}
define i64 @lea1b(i64 %x) nounwind {
; CHECK-LABEL: lea1b:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s0, (, %s0)
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%asmtmp = tail call i64 asm "lea $0, (, $1)", "=r,r"(i64 %x) nounwind
ret i64 %asmtmp
}
define i64 @lea2(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: lea2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s0, (%s0, %s1)
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%asmtmp = tail call i64 asm "lea $0, ($1, $2)", "=r,r,r"(i64 %x, i64 %y) nounwind
ret i64 %asmtmp
}
define i64 @lea3(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: lea3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s0, 2048(%s0, %s1)
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%asmtmp = tail call i64 asm "lea $0, 2048($1, $2)", "=r,r,r"(i64 %x, i64 %y) nounwind
ret i64 %asmtmp
}
define i64 @leasl3(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: leasl3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea.sl %s0, 2048(%s1, %s0)
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%asmtmp = tail call i64 asm "lea.sl $0, 2048($1, $2)", "=r,r,r"(i64 %y, i64 %x) nounwind
ret i64 %asmtmp
}

12
llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst.ll
View File

@ -2,7 +2,7 @@
define void @vld(i8* %p, i64 %i) nounwind {
; CHECK-LABEL: vld:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: #NO_APP
@ -12,7 +12,7 @@ define void @vld(i8* %p, i64 %i) nounwind {
; CHECK-NEXT: #APP
; CHECK-NEXT: vld %v0, %s1, %s0
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
@ -21,7 +21,7 @@ define void @vld(i8* %p, i64 %i) nounwind {
define void @vldvst(i8* %p, i64 %i) nounwind {
; CHECK-LABEL: vldvst:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: #NO_APP
@ -34,7 +34,7 @@ define void @vldvst(i8* %p, i64 %i) nounwind {
; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v0, %s1, %s0
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
%1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
@ -44,7 +44,7 @@ define void @vldvst(i8* %p, i64 %i) nounwind {
define void @vld2vst2(i8* %p, i64 %i) nounwind {
; CHECK-LABEL: vld2vst2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: #APP
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: #NO_APP
@ -63,7 +63,7 @@ define void @vld2vst2(i8* %p, i64 %i) nounwind {
; CHECK-NEXT: #APP
; CHECK-NEXT: vst %v1, %s1, %s0
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
%1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind

64
llvm/test/CodeGen/VE/Scalar/int_to_fp.ll
View File

@ -3,9 +3,9 @@
; Function Attrs: norecurse nounwind readnone
define float @c2f(i8 signext %a) {
; CHECK-LABEL: c2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = sitofp i8 %a to float
ret float %conv
@ -14,9 +14,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define float @s2f(i16 signext %a) {
; CHECK-LABEL: s2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = sitofp i16 %a to float
ret float %conv
@ -25,9 +25,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define float @i2f(i32 %a) {
; CHECK-LABEL: i2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = sitofp i32 %a to float
ret float %conv
@ -36,10 +36,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define float @l2f(i64 %a) {
; CHECK-LABEL: l2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = sitofp i64 %a to float
ret float %conv
@ -48,9 +48,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define float @uc2f(i8 zeroext %a) {
; CHECK-LABEL: uc2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = uitofp i8 %a to float
ret float %conv
@ -59,9 +59,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define float @us2f(i16 zeroext %a) {
; CHECK-LABEL: us2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = uitofp i16 %a to float
ret float %conv
@ -70,11 +70,11 @@ entry:
; Function Attrs: norecurse nounwind readnone
define float @ui2f(i32 %a) {
; CHECK-LABEL: ui2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = uitofp i32 %a to float
ret float %conv
@ -83,7 +83,7 @@ entry:
; Function Attrs: norecurse nounwind readnone
define float @ul2f(i64 %a) {
; CHECK-LABEL: ul2f:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmps.l %s2, %s0, (0)1
; CHECK-NEXT: cvt.d.l %s1, %s0
; CHECK-NEXT: cvt.s.d %s1, %s1
@ -95,7 +95,7 @@ define float @ul2f(i64 %a) {
; CHECK-NEXT: fadd.s %s0, %s0, %s0
; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = uitofp i64 %a to float
ret float %conv
@ -104,9 +104,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define double @c2d(i8 signext %a) {
; CHECK-LABEL: c2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = sitofp i8 %a to double
ret double %conv
@ -115,9 +115,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define double @s2d(i16 signext %a) {
; CHECK-LABEL: s2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = sitofp i16 %a to double
ret double %conv
@ -126,9 +126,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define double @i2d(i32 %a) {
; CHECK-LABEL: i2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = sitofp i32 %a to double
ret double %conv
@ -137,9 +137,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define double @l2d(i64 %a) {
; CHECK-LABEL: l2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = sitofp i64 %a to double
ret double %conv
@ -148,9 +148,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define double @uc2d(i8 zeroext %a) {
; CHECK-LABEL: uc2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = uitofp i8 %a to double
ret double %conv
@ -159,9 +159,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define double @us2d(i16 zeroext %a) {
; CHECK-LABEL: us2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = uitofp i16 %a to double
ret double %conv
@ -170,10 +170,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define double @ui2d(i32 %a) {
; CHECK-LABEL: ui2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = uitofp i32 %a to double
ret double %conv
@ -182,7 +182,7 @@ entry:
; Function Attrs: norecurse nounwind readnone
define double @ul2d(i64 %a) {
; CHECK-LABEL: ul2d:
; CHECK: .LBB{{[0-9]+}}_2: # %entry
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: srl %s1, %s0, 32
; CHECK-NEXT: lea.sl %s2, 1160773632
; CHECK-NEXT: or %s1, %s1, %s2
@ -193,7 +193,7 @@ define double @ul2d(i64 %a) {
; CHECK-NEXT: lea.sl %s2, 1127219200
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%conv = uitofp i64 %a to double
ret double %conv

64
llvm/test/CodeGen/VE/Scalar/left_shift.ll
View File

@ -2,11 +2,11 @@
define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i8 %0 to i32
%4 = sext i8 %1 to i32
%5 = shl i32 %3, %4
@ -16,11 +16,11 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i16 %0 to i32
%4 = sext i16 %1 to i32
%5 = shl i32 %3, %4
@ -30,28 +30,28 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i32 %0, %1
ret i32 %3
}
define i64 @func4(i64 %0, i64 %1) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i64 %0, %1
ret i64 %3
}
define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i8 %0 to i32
%4 = zext i8 %1 to i32
%5 = shl i32 %3, %4
@ -61,10 +61,10 @@ define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i16 %0 to i32
%4 = zext i16 %1 to i32
%5 = shl i32 %3, %4
@ -74,98 +74,98 @@ define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
define i32 @func8(i32 %0, i32 %1) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i32 %0, %1
ret i32 %3
}
define i64 @func9(i64 %0, i64 %1) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i64 %0, %1
ret i64 %3
}
define signext i8 @func11(i8 signext %0) {
; CHECK-LABEL: func11:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i8 %0, 5
ret i8 %2
}
define signext i16 @func12(i16 signext %0) {
; CHECK-LABEL: func12:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i16 %0, 5
ret i16 %2
}
define i32 @func13(i32 %0) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 %0, 5
ret i32 %2
}
define i64 @func14(i64 %0) {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 %0, 5
ret i64 %2
}
define zeroext i8 @func16(i8 zeroext %0) {
; CHECK-LABEL: func16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: lea %s1, 224
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i8 %0, 5
ret i8 %2
}
define zeroext i16 @func17(i16 zeroext %0) {
; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: lea %s1, 65504
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i16 %0, 5
ret i16 %2
}
define i32 @func18(i32 %0) {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 %0, 5
ret i32 %2
}
define i64 @func19(i64 %0) {
; CHECK-LABEL: func19:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 %0, 5
ret i64 %2
}

24
llvm/test/CodeGen/VE/Scalar/load-align1.ll
View File

@ -76,12 +76,12 @@ define i8 @loadi8stk() {
; Function Attrs: norecurse nounwind readonly
define double @loadf64com() {
; CHECK-LABEL: loadf64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load double, double* @vf64, align 1
ret double %1
}
@ -89,12 +89,12 @@ define double @loadf64com() {
; Function Attrs: norecurse nounwind readonly
define float @loadf32com() {
; CHECK-LABEL: loadf32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0)
; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load float, float* @vf32, align 1
ret float %1
}
@ -102,12 +102,12 @@ define float @loadf32com() {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi64com() {
; CHECK-LABEL: loadi64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i64, i64* @vi64, align 1
ret i64 %1
}
@ -115,12 +115,12 @@ define i64 @loadi64com() {
; Function Attrs: norecurse nounwind readonly
define i32 @loadi32com() {
; CHECK-LABEL: loadi32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i32, i32* @vi32, align 1
ret i32 %1
}
@ -128,12 +128,12 @@ define i32 @loadi32com() {
; Function Attrs: norecurse nounwind readonly
define i16 @loadi16com() {
; CHECK-LABEL: loadi16com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i16, i16* @vi16, align 1
ret i16 %1
}
@ -141,12 +141,12 @@ define i16 @loadi16com() {
; Function Attrs: norecurse nounwind readonly
define i8 @loadi8com() {
; CHECK-LABEL: loadi8com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i8, i8* @vi8, align 1
ret i8 %1
}

24
llvm/test/CodeGen/VE/Scalar/load-align2.ll
View File

@ -76,12 +76,12 @@ define i8 @loadi8stk() {
; Function Attrs: norecurse nounwind readonly
define double @loadf64com() {
; CHECK-LABEL: loadf64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load double, double* @vf64, align 2
ret double %1
}
@ -89,12 +89,12 @@ define double @loadf64com() {
; Function Attrs: norecurse nounwind readonly
define float @loadf32com() {
; CHECK-LABEL: loadf32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0)
; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load float, float* @vf32, align 2
ret float %1
}
@ -102,12 +102,12 @@ define float @loadf32com() {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi64com() {
; CHECK-LABEL: loadi64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i64, i64* @vi64, align 2
ret i64 %1
}
@ -115,12 +115,12 @@ define i64 @loadi64com() {
; Function Attrs: norecurse nounwind readonly
define i32 @loadi32com() {
; CHECK-LABEL: loadi32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i32, i32* @vi32, align 2
ret i32 %1
}
@ -128,12 +128,12 @@ define i32 @loadi32com() {
; Function Attrs: norecurse nounwind readonly
define i16 @loadi16com() {
; CHECK-LABEL: loadi16com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i16, i16* @vi16, align 2
ret i16 %1
}
@ -141,12 +141,12 @@ define i16 @loadi16com() {
; Function Attrs: norecurse nounwind readonly
define i8 @loadi8com() {
; CHECK-LABEL: loadi8com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i8, i8* @vi8, align 2
ret i8 %1
}

24
llvm/test/CodeGen/VE/Scalar/load-align4.ll
View File

@ -76,12 +76,12 @@ define i8 @loadi8stk() {
; Function Attrs: norecurse nounwind readonly
define double @loadf64com() {
; CHECK-LABEL: loadf64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load double, double* @vf64, align 4
ret double %1
}
@ -89,12 +89,12 @@ define double @loadf64com() {
; Function Attrs: norecurse nounwind readonly
define float @loadf32com() {
; CHECK-LABEL: loadf32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0)
; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load float, float* @vf32, align 4
ret float %1
}
@ -102,12 +102,12 @@ define float @loadf32com() {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi64com() {
; CHECK-LABEL: loadi64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i64, i64* @vi64, align 4
ret i64 %1
}
@ -115,12 +115,12 @@ define i64 @loadi64com() {
; Function Attrs: norecurse nounwind readonly
define i32 @loadi32com() {
; CHECK-LABEL: loadi32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i32, i32* @vi32, align 4
ret i32 %1
}
@ -128,12 +128,12 @@ define i32 @loadi32com() {
; Function Attrs: norecurse nounwind readonly
define i16 @loadi16com() {
; CHECK-LABEL: loadi16com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i16, i16* @vi16, align 4
ret i16 %1
}
@ -141,12 +141,12 @@ define i16 @loadi16com() {
; Function Attrs: norecurse nounwind readonly
define i8 @loadi8com() {
; CHECK-LABEL: loadi8com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i8, i8* @vi8, align 4
ret i8 %1
}

24
llvm/test/CodeGen/VE/Scalar/load-align8.ll
View File

@ -76,12 +76,12 @@ define i8 @loadi8stk() {
; Function Attrs: norecurse nounwind readonly
define double @loadf64com() {
; CHECK-LABEL: loadf64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load double, double* @vf64, align 8
ret double %1
}
@ -89,12 +89,12 @@ define double @loadf64com() {
; Function Attrs: norecurse nounwind readonly
define float @loadf32com() {
; CHECK-LABEL: loadf32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0)
; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load float, float* @vf32, align 8
ret float %1
}
@ -102,12 +102,12 @@ define float @loadf32com() {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi64com() {
; CHECK-LABEL: loadi64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i64, i64* @vi64, align 8
ret i64 %1
}
@ -115,12 +115,12 @@ define i64 @loadi64com() {
; Function Attrs: norecurse nounwind readonly
define i32 @loadi32com() {
; CHECK-LABEL: loadi32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i32, i32* @vi32, align 8
ret i32 %1
}
@ -128,12 +128,12 @@ define i32 @loadi32com() {
; Function Attrs: norecurse nounwind readonly
define i16 @loadi16com() {
; CHECK-LABEL: loadi16com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i16, i16* @vi16, align 8
ret i16 %1
}
@ -141,12 +141,12 @@ define i16 @loadi16com() {
; Function Attrs: norecurse nounwind readonly
define i8 @loadi8com() {
; CHECK-LABEL: loadi8com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i8, i8* @vi8, align 8
ret i8 %1
}

56
llvm/test/CodeGen/VE/Scalar/load.ll
View File

@ -3,12 +3,12 @@
; Function Attrs: norecurse nounwind readonly
define fp128 @loadf128(fp128* nocapture readonly %0) {
; CHECK-LABEL: loadf128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld %s2, 8(, %s0)
; CHECK-NEXT: ld %s3, (, %s0)
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load fp128, fp128* %0, align 16
ret fp128 %2
}
@ -16,9 +16,9 @@ define fp128 @loadf128(fp128* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define double @loadf64(double* nocapture readonly %0) {
; CHECK-LABEL: loadf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load double, double* %0, align 16
ret double %2
}
@ -26,9 +26,9 @@ define double @loadf64(double* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define float @loadf32(float* nocapture readonly %0) {
; CHECK-LABEL: loadf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load float, float* %0, align 16
ret float %2
}
@ -36,11 +36,11 @@ define float @loadf32(float* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i128 @loadi128(i128* nocapture readonly %0) {
; CHECK-LABEL: loadi128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld %s2, (, %s0)
; CHECK-NEXT: ld %s1, 8(, %s0)
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i128, i128* %0, align 16
ret i128 %2
}
@ -48,9 +48,9 @@ define i128 @loadi128(i128* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi64(i64* nocapture readonly %0) {
; CHECK-LABEL: loadi64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i64, i64* %0, align 16
ret i64 %2
}
@ -58,9 +58,9 @@ define i64 @loadi64(i64* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i32 @loadi32(i32* nocapture readonly %0) {
; CHECK-LABEL: loadi32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i32, i32* %0, align 16
ret i32 %2
}
@ -68,9 +68,9 @@ define i32 @loadi32(i32* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi32sext(i32* nocapture readonly %0) {
; CHECK-LABEL: loadi32sext:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i32, i32* %0, align 16
%3 = sext i32 %2 to i64
ret i64 %3
@ -79,9 +79,9 @@ define i64 @loadi32sext(i32* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi32zext(i32* nocapture readonly %0) {
; CHECK-LABEL: loadi32zext:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ldl.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i32, i32* %0, align 16
%3 = zext i32 %2 to i64
ret i64 %3
@ -90,9 +90,9 @@ define i64 @loadi32zext(i32* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i16 @loadi16(i16* nocapture readonly %0) {
; CHECK-LABEL: loadi16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i16, i16* %0, align 16
ret i16 %2
}
@ -100,9 +100,9 @@ define i16 @loadi16(i16* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi16sext(i16* nocapture readonly %0) {
; CHECK-LABEL: loadi16sext:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i16, i16* %0, align 16
%3 = sext i16 %2 to i64
ret i64 %3
@ -111,9 +111,9 @@ define i64 @loadi16sext(i16* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi16zext(i16* nocapture readonly %0) {
; CHECK-LABEL: loadi16zext:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i16, i16* %0, align 16
%3 = zext i16 %2 to i64
ret i64 %3
@ -122,9 +122,9 @@ define i64 @loadi16zext(i16* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i8 @loadi8(i8* nocapture readonly %0) {
; CHECK-LABEL: loadi8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i8, i8* %0, align 16
ret i8 %2
}
@ -132,9 +132,9 @@ define i8 @loadi8(i8* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi8sext(i8* nocapture readonly %0) {
; CHECK-LABEL: loadi8sext:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i8, i8* %0, align 16
%3 = sext i8 %2 to i64
ret i64 %3
@ -143,9 +143,9 @@ define i64 @loadi8sext(i8* nocapture readonly %0) {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi8zext(i8* nocapture readonly %0) {
; CHECK-LABEL: loadi8zext:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = load i8, i8* %0, align 16
%3 = zext i8 %2 to i64
ret i64 %3

32
llvm/test/CodeGen/VE/Scalar/load_gv.ll
View File

@ -12,13 +12,13 @@
; Function Attrs: norecurse nounwind readonly
define fp128 @loadf128com() {
; CHECK-LABEL: loadf128com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf128@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, vf128@hi(, %s0)
; CHECK-NEXT: ld %s0, 8(, %s2)
; CHECK-NEXT: ld %s1, (, %s2)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load fp128, fp128* @vf128, align 16
ret fp128 %1
}
@ -26,12 +26,12 @@ define fp128 @loadf128com() {
; Function Attrs: norecurse nounwind readonly
define double @loadf64com() {
; CHECK-LABEL: loadf64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load double, double* @vf64, align 8
ret double %1
}
@ -39,12 +39,12 @@ define double @loadf64com() {
; Function Attrs: norecurse nounwind readonly
define float @loadf32com() {
; CHECK-LABEL: loadf32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vf32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vf32@hi(, %s0)
; CHECK-NEXT: ldu %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load float, float* @vf32, align 4
ret float %1
}
@ -52,13 +52,13 @@ define float @loadf32com() {
; Function Attrs: norecurse nounwind readonly
define i128 @loadi128com() {
; CHECK-LABEL: loadi128com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi128@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s1, vi128@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s1)
; CHECK-NEXT: ld %s1, 8(, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i128, i128* @vi128, align 16
ret i128 %1
}
@ -66,12 +66,12 @@ define i128 @loadi128com() {
; Function Attrs: norecurse nounwind readonly
define i64 @loadi64com() {
; CHECK-LABEL: loadi64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi64@hi(, %s0)
; CHECK-NEXT: ld %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i64, i64* @vi64, align 8
ret i64 %1
}
@ -79,12 +79,12 @@ define i64 @loadi64com() {
; Function Attrs: norecurse nounwind readonly
define i32 @loadi32com() {
; CHECK-LABEL: loadi32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i32, i32* @vi32, align 4
ret i32 %1
}
@ -92,12 +92,12 @@ define i32 @loadi32com() {
; Function Attrs: norecurse nounwind readonly
define i16 @loadi16com() {
; CHECK-LABEL: loadi16com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i16, i16* @vi16, align 2
ret i16 %1
}
@ -105,12 +105,12 @@ define i16 @loadi16com() {
; Function Attrs: norecurse nounwind readonly
define i8 @loadi8com() {
; CHECK-LABEL: loadi8com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, vi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, vi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%1 = load i8, i8* @vi8, align 1
ret i8 %1
}

52
llvm/test/CodeGen/VE/Scalar/load_off.ll
View File

@ -12,12 +12,12 @@
; Function Attrs: noinline nounwind optnone
define signext i8 @loadi8s() {
; CHECK-LABEL: loadi8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi8@hi(, %s0)
; CHECK-NEXT: ld1b.sx %s0, 2(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load i8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @bufi8, i64 0, i64 2), align 1
ret i8 %0
@ -26,12 +26,12 @@ entry:
; Function Attrs: noinline nounwind optnone
define signext i16 @loadi16s() {
; CHECK-LABEL: loadi16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi16@hi(, %s0)
; CHECK-NEXT: ld2b.sx %s0, 4(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load i16, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @bufi16, i64 0, i64 2), align 2
ret i16 %0
@ -40,12 +40,12 @@ entry:
; Function Attrs: noinline nounwind optnone
define signext i32 @loadi32s() {
; CHECK-LABEL: loadi32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi32@hi(, %s0)
; CHECK-NEXT: ldl.sx %s0, 8(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @bufi32, i64 0, i64 2), align 4
ret i32 %0
@ -54,12 +54,12 @@ entry:
; Function Attrs: noinline nounwind optnone
define i64 @loadi64s() {
; CHECK-LABEL: loadi64s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi64@hi(, %s0)
; CHECK-NEXT: ld %s0, 16(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load i64, i64* getelementptr inbounds ([3 x i64], [3 x i64]* @bufi64, i64 0, i64 2), align 8
ret i64 %0
@ -68,13 +68,13 @@ entry:
; Function Attrs: noinline nounwind optnone
define i128 @loadi128s() {
; CHECK-LABEL: loadi128s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi128@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s1, bufi128@hi(, %s0)
; CHECK-NEXT: ld %s0, 32(, %s1)
; CHECK-NEXT: ld %s1, 40(, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load i128, i128* getelementptr inbounds ([3 x i128], [3 x i128]* @bufi128, i64 0, i64 2), align 16
ret i128 %0
@ -83,12 +83,12 @@ entry:
; Function Attrs: noinline nounwind optnone
define zeroext i8 @loadi8z() {
; CHECK-LABEL: loadi8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi8@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi8@hi(, %s0)
; CHECK-NEXT: ld1b.zx %s0, 2(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load i8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @bufi8, i64 0, i64 2), align 1
ret i8 %0
@ -97,12 +97,12 @@ entry:
; Function Attrs: noinline nounwind optnone
define zeroext i16 @loadi16z() {
; CHECK-LABEL: loadi16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi16@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi16@hi(, %s0)
; CHECK-NEXT: ld2b.zx %s0, 4(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load i16, i16* getelementptr inbounds ([3 x i16], [3 x i16]* @bufi16, i64 0, i64 2), align 2
ret i16 %0
@ -111,12 +111,12 @@ entry:
; Function Attrs: noinline nounwind optnone
define zeroext i32 @loadi32z() {
; CHECK-LABEL: loadi32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi32@hi(, %s0)
; CHECK-NEXT: ldl.zx %s0, 8(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @bufi32, i64 0, i64 2), align 4
ret i32 %0
@ -125,12 +125,12 @@ entry:
; Function Attrs: noinline nounwind optnone
define i64 @loadi64z() {
; CHECK-LABEL: loadi64z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi64@hi(, %s0)
; CHECK-NEXT: ld %s0, 16(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load i64, i64* getelementptr inbounds ([3 x i64], [3 x i64]* @bufi64, i64 0, i64 2), align 8
ret i64 %0
@ -139,13 +139,13 @@ entry:
; Function Attrs: noinline nounwind optnone
define i128 @loadi128z() {
; CHECK-LABEL: loadi128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, bufi128@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s1, bufi128@hi(, %s0)
; CHECK-NEXT: ld %s0, 32(, %s1)
; CHECK-NEXT: ld %s1, 40(, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load i128, i128* getelementptr inbounds ([3 x i128], [3 x i128]* @bufi128, i64 0, i64 2), align 16
ret i128 %0
@ -154,12 +154,12 @@ entry:
; Function Attrs: noinline nounwind optnone
define float @loadf32() {
; CHECK-LABEL: loadf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, buff32@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, buff32@hi(, %s0)
; CHECK-NEXT: ldu %s0, 8(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load float, float* getelementptr inbounds ([3 x float], [3 x float]* @buff32, i64 0, i64 2), align 4
ret float %0
@ -168,12 +168,12 @@ entry:
; Function Attrs: noinline nounwind optnone
define double @loadf64() {
; CHECK-LABEL: loadf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, buff64@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, buff64@hi(, %s0)
; CHECK-NEXT: ld %s0, 16(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load double, double* getelementptr inbounds ([3 x double], [3 x double]* @buff64, i64 0, i64 2), align 8
ret double %0
@ -182,13 +182,13 @@ entry:
; Function Attrs: noinline nounwind optnone
define fp128 @loadf128() {
; CHECK-LABEL: loadf128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lea %s0, buff128@lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s2, buff128@hi(, %s0)
; CHECK-NEXT: ld %s0, 40(, %s2)
; CHECK-NEXT: ld %s1, 32(, %s2)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
entry:
%0 = load fp128, fp128* getelementptr inbounds ([3 x fp128], [3 x fp128]* @buff128, i64 0, i64 2), align 16
ret fp128 %0

4
llvm/test/CodeGen/VE/Scalar/loadrri.ll
View File

@ -12,10 +12,10 @@
; Function Attrs: norecurse nounwind readonly
define signext i8 @func_rr(%struct.data* nocapture readonly %0, i32 signext %1) {
; CHECK-LABEL: func_rr:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 2
; CHECK-NEXT: ld1b.sx %s0, (%s1, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i32 %1 to i64
%4 = getelementptr inbounds %struct.data, %struct.data* %0, i64 %3, i32 0, i64 0
%5 = load i8, i8* %4, align 1

68
llvm/test/CodeGen/VE/Scalar/max.ll
View File

@ -2,9 +2,9 @@
define double @maxf64(double, double) {
; CHECK-LABEL: maxf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmax.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
@ -12,9 +12,9 @@ define double @maxf64(double, double) {
define double @max2f64(double, double) {
; CHECK-LABEL: max2f64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmax.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
@ -23,11 +23,11 @@ define double @max2f64(double, double) {
; VE has no max for unordered comparison
define double @maxuf64(double, double) {
; CHECK-LABEL: maxuf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: cmov.d.gtnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
@ -36,11 +36,11 @@ define double @maxuf64(double, double) {
; VE has no max for unordered comparison
define double @max2uf64(double, double) {
; CHECK-LABEL: max2uf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: cmov.d.genan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
@ -48,9 +48,9 @@ define double @max2uf64(double, double) {
define float @maxf32(float, float) {
; CHECK-LABEL: maxf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmax.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
@ -58,9 +58,9 @@ define float @maxf32(float, float) {
define float @max2f32(float, float) {
; CHECK-LABEL: max2f32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmax.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
@ -68,11 +68,11 @@ define float @max2f32(float, float) {
define float @maxuf32(float, float) {
; CHECK-LABEL: maxuf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.gtnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
@ -80,11 +80,11 @@ define float @maxuf32(float, float) {
define float @max2uf32(float, float) {
; CHECK-LABEL: max2uf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.genan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
@ -92,9 +92,9 @@ define float @max2uf32(float, float) {
define i64 @maxi64(i64, i64) {
; CHECK-LABEL: maxi64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@ -102,9 +102,9 @@ define i64 @maxi64(i64, i64) {
define i64 @max2i64(i64, i64) {
; CHECK-LABEL: max2i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@ -112,11 +112,11 @@ define i64 @max2i64(i64, i64) {
define i64 @maxu64(i64, i64) {
; CHECK-LABEL: maxu64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s2, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@ -124,11 +124,11 @@ define i64 @maxu64(i64, i64) {
define i64 @max2u64(i64, i64) {
; CHECK-LABEL: max2u64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s2, %s0, %s1
; CHECK-NEXT: cmov.l.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@ -136,9 +136,9 @@ define i64 @max2u64(i64, i64) {
define i32 @maxi32(i32, i32) {
; CHECK-LABEL: maxi32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@ -146,9 +146,9 @@ define i32 @maxi32(i32, i32) {
define i32 @max2i32(i32, i32) {
; CHECK-LABEL: max2i32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@ -156,11 +156,11 @@ define i32 @max2i32(i32, i32) {
define i32 @maxu32(i32, i32) {
; CHECK-LABEL: maxu32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s2, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@ -168,11 +168,11 @@ define i32 @maxu32(i32, i32) {
define i32 @max2u32(i32, i32) {
; CHECK-LABEL: max2u32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s2, %s0, %s1
; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@ -180,10 +180,10 @@ define i32 @max2u32(i32, i32) {
define zeroext i1 @maxi1(i1 zeroext, i1 zeroext) {
; CHECK-LABEL: maxi1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %1, true
%4 = and i1 %3, %0
%5 = select i1 %4, i1 %0, i1 %1

68
llvm/test/CodeGen/VE/Scalar/min.ll
View File

@ -2,9 +2,9 @@
define double @minf64(double, double) {
; CHECK-LABEL: minf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmin.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
@ -12,9 +12,9 @@ define double @minf64(double, double) {
define double @min2f64(double, double) {
; CHECK-LABEL: min2f64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmin.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
@ -22,11 +22,11 @@ define double @min2f64(double, double) {
define double @minuf64(double, double) {
; CHECK-LABEL: minuf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: cmov.d.ltnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
@ -34,11 +34,11 @@ define double @minuf64(double, double) {
define double @min2uf64(double, double) {
; CHECK-LABEL: min2uf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s2, %s0, %s1
; CHECK-NEXT: cmov.d.lenan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule double %0, %1
%4 = select i1 %3, double %0, double %1
ret double %4
@ -46,9 +46,9 @@ define double @min2uf64(double, double) {
define float @minf32(float, float) {
; CHECK-LABEL: minf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmin.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
@ -56,9 +56,9 @@ define float @minf32(float, float) {
define float @min2f32(float, float) {
; CHECK-LABEL: min2f32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmin.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
@ -66,11 +66,11 @@ define float @min2f32(float, float) {
define float @minuf32(float, float) {
; CHECK-LABEL: minuf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.ltnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
@ -78,11 +78,11 @@ define float @minuf32(float, float) {
define float @min2uf32(float, float) {
; CHECK-LABEL: min2uf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.lenan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule float %0, %1
%4 = select i1 %3, float %0, float %1
ret float %4
@ -90,9 +90,9 @@ define float @min2uf32(float, float) {
define i64 @mini64(i64, i64) {
; CHECK-LABEL: mini64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: mins.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@ -100,9 +100,9 @@ define i64 @mini64(i64, i64) {
define i64 @min2i64(i64, i64) {
; CHECK-LABEL: min2i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: mins.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@ -110,11 +110,11 @@ define i64 @min2i64(i64, i64) {
define i64 @minu64(i64, i64) {
; CHECK-LABEL: minu64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s2, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@ -122,11 +122,11 @@ define i64 @minu64(i64, i64) {
define i64 @min2u64(i64, i64) {
; CHECK-LABEL: min2u64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s2, %s0, %s1
; CHECK-NEXT: cmov.l.le %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i64 %0, %1
%4 = select i1 %3, i64 %0, i64 %1
ret i64 %4
@ -134,9 +134,9 @@ define i64 @min2u64(i64, i64) {
define i32 @mini32(i32, i32) {
; CHECK-LABEL: mini32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: mins.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@ -144,9 +144,9 @@ define i32 @mini32(i32, i32) {
define i32 @min2i32(i32, i32) {
; CHECK-LABEL: min2i32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: mins.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@ -154,11 +154,11 @@ define i32 @min2i32(i32, i32) {
define i32 @minu32(i32, i32) {
; CHECK-LABEL: minu32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s2, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@ -166,11 +166,11 @@ define i32 @minu32(i32, i32) {
define i32 @min2u32(i32, i32) {
; CHECK-LABEL: min2u32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s2, %s0, %s1
; CHECK-NEXT: cmov.w.le %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
ret i32 %4
@ -178,11 +178,11 @@ define i32 @min2u32(i32, i32) {
define zeroext i1 @mini1(i1 zeroext, i1 zeroext) {
; CHECK-LABEL: mini1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s2, %s1, %s0
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %0, true
%4 = and i1 %3, %1
%5 = select i1 %4, i1 %0, i1 %1

76
llvm/test/CodeGen/VE/Scalar/multiply.ll
View File

@ -2,41 +2,41 @@
define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i8 %b, %a
ret i8 %r
}
define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i16 %b, %a
ret i16 %r
}
define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul nsw i32 %b, %a
ret i32 %r
}
define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul nsw i64 %b, %a
ret i64 %r
}
@ -61,39 +61,39 @@ define i128 @func128(i128 %a, i128 %b) {
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i8 %b, %a
ret i8 %r
}
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i16 %b, %a
ret i16 %r
}
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i32 %b, %a
ret i32 %r
}
define i64 @func64z(i64 %a, i64 %b) {
; CHECK-LABEL: func64z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.l %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i64 %b, %a
ret i64 %r
}
@ -118,41 +118,41 @@ define i128 @func128z(i128 %a, i128 %b) {
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i8 %a, 5
ret i8 %r
}
define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i16 %a, 5
ret i16 %r
}
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul nsw i32 %a, 5
ret i32 %r
}
define i64 @funci64(i64 %a) {
; CHECK-LABEL: funci64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.l %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul nsw i64 %a, 5
ret i64 %r
}
@ -173,39 +173,39 @@ define i128 @funci128(i128 %a) {
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i8 %a, 5
ret i8 %r
}
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i16 %a, 5
ret i16 %r
}
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i32 %a, 5
ret i32 %r
}
define i64 @funci64z(i64 %a) {
; CHECK-LABEL: funci64z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: muls.l %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = mul i64 %a, 5
ret i64 %r
}
@ -226,31 +226,31 @@ define i128 @funci128z(i128 %a) {
define zeroext i32 @funci32z_2(i32 zeroext %a) {
; CHECK-LABEL: funci32z_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 31
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = shl i32 %a, 31
ret i32 %r
}
define i64 @funci64_2(i64 %a) {
; CHECK-LABEL: funci64_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = shl nsw i64 %a, 31
ret i64 %r
}
define i128 @funci128_2(i128 %a) {
; CHECK-LABEL: funci128_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: srl %s2, %s0, 33
; CHECK-NEXT: sll %s1, %s1, 31
; CHECK-NEXT: or %s1, %s1, %s2
; CHECK-NEXT: sll %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = shl nsw i128 %a, 31
ret i128 %r
}

80
llvm/test/CodeGen/VE/Scalar/nnd.ll
View File

@ -2,9 +2,9 @@
define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i8 %a, -1
%res = and i8 %not, %b
ret i8 %res
@ -12,9 +12,9 @@ define signext i8 @func8s(i8 signext %a, i8 signext %b) {
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i8 %a, -1
%res = and i8 %b, %not
ret i8 %res
@ -22,10 +22,10 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 5, (0)1
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i8 %a, -1
%res = and i8 %not, 5
ret i8 %res
@ -33,10 +33,10 @@ define signext i8 @funci8s(i8 signext %a) {
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i8 %a, -1
%res = and i8 -5, %not
ret i8 %res
@ -44,9 +44,9 @@ define zeroext i8 @funci8z(i8 zeroext %a) {
define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i16 %a, -1
%res = and i16 %not, %b
ret i16 %res
@ -54,9 +54,9 @@ define signext i16 @func16s(i16 signext %a, i16 signext %b) {
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i16 %a, -1
%res = and i16 %b, %not
ret i16 %res
@ -64,9 +64,9 @@ define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i16 %a, -1
%res = and i16 %not, 65535
ret i16 %res
@ -74,9 +74,9 @@ define signext i16 @funci16s(i16 signext %a) {
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, (52)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i16 %a, -1
%res = and i16 4095, %not
ret i16 %res
@ -84,9 +84,9 @@ define zeroext i16 @funci16z(i16 zeroext %a) {
define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i32 %a, -1
%res = and i32 %not, %b
ret i32 %res
@ -94,9 +94,9 @@ define signext i32 @func32s(i32 signext %a, i32 signext %b) {
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i32 %a, -1
%res = and i32 %not, %b
ret i32 %res
@ -104,9 +104,9 @@ define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i32 %a, -1
%res = and i32 %not, 268435455
ret i32 %res
@ -114,9 +114,9 @@ define signext i32 @funci32s(i32 signext %a) {
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i32 %a, -1
%res = and i32 %not, 268435455
ret i32 %res
@ -124,9 +124,9 @@ define zeroext i32 @funci32z(i32 zeroext %a) {
define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i64 %a, -1
%res = and i64 %not, %b
ret i64 %res
@ -134,9 +134,9 @@ define i64 @func64(i64 %a, i64 %b) {
define i64 @func64_2(i64 %a, i64 %b) {
; CHECK-LABEL: func64_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i64 %b, -1
%res = and i64 %not, %a
ret i64 %res
@ -144,9 +144,9 @@ define i64 @func64_2(i64 %a, i64 %b) {
define i64 @func64i(i64 %a) {
; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, (24)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i64 %a, -1
%res = and i64 %not, 1099511627775
ret i64 %res
@ -154,10 +154,10 @@ define i64 @func64i(i64 %a) {
define i128 @func128(i128 %a, i128 %b) {
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s2
; CHECK-NEXT: nnd %s1, %s1, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i128 %a, -1
%res = and i128 %b, %not
ret i128 %res
@ -165,11 +165,11 @@ define i128 @func128(i128 %a, i128 %b) {
define i128 @funci128(i128 %a) {
; CHECK-LABEL: funci128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 5, (0)1
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%not = xor i128 %a, -1
%res = and i128 %not, 5
ret i128 %res
@ -177,11 +177,11 @@ define i128 @funci128(i128 %a) {
define i64 @func64_nnd_fold(i64 %x, i64 %y, i64 %m) {
; CHECK-LABEL: func64_nnd_fold:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s1, %s2, %s1
; CHECK-NEXT: and %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%D = xor i64 %x, %y
%A = and i64 %D, %m
%res = xor i64 %A, %y
@ -190,11 +190,11 @@ define i64 @func64_nnd_fold(i64 %x, i64 %y, i64 %m) {
define i64 @func64iy_nnd_fold(i64 %x, i64 %m) {
; CHECK-LABEL: func64iy_nnd_fold:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s1, -64, %s1
; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%D = xor i64 %x, -64
%A = and i64 %D, %m
%res = xor i64 %A, -64
@ -203,11 +203,11 @@ define i64 @func64iy_nnd_fold(i64 %x, i64 %m) {
define i64 @func64im_nnd_fold(i64 %x, i64 %y) {
; CHECK-LABEL: func64im_nnd_fold:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: and %s0, 30, %s0
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%D = xor i64 %x, %y
%A = and i64 %D, 30
%res = xor i64 %A, %y

64
llvm/test/CodeGen/VE/Scalar/or.ll
View File

@ -2,146 +2,146 @@
define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i8 %a, %b
ret i8 %res
}
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i8 %b, %a
ret i8 %res
}
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i8 %a, 5
ret i8 %res
}
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i8 -5, %a
ret i8 %res
}
define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i16 %a, %b
ret i16 %res
}
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i16 %b, %a
ret i16 %res
}
define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, -1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i16 %a, 65535
ret i16 %res
}
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, (52)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i16 4095, %a
ret i16 %res
}
define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i32 %a, %b
ret i32 %res
}
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i32 %a, %b
ret i32 %res
}
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i32 %a, 268435455
ret i32 %res
}
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i32 %a, 268435455
ret i32 %res
}
define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i64 %a, %b
ret i64 %res
}
define i64 @func64i(i64 %a) {
; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, (24)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i64 %a, 1099511627775
ret i64 %res
}
define i128 @func128(i128 %a, i128 %b) {
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s2, %s0
; CHECK-NEXT: or %s1, %s3, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i128 %b, %a
ret i128 %res
}
define i128 @funci128(i128 %a) {
; CHECK-LABEL: funci128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = or i128 %a, 5
ret i128 %res
}

64
llvm/test/CodeGen/VE/Scalar/rem.ll
View File

@ -16,11 +16,11 @@ define i128 @remi128(i128 %a, i128 %b) {
; Function Attrs: norecurse nounwind readnone
define i64 @remi64(i64 %a, i64 %b) {
; CHECK-LABEL: remi64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s2, %s0, %s1
; CHECK-NEXT: muls.l %s1, %s2, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = srem i64 %a, %b
ret i64 %r
}
@ -28,12 +28,12 @@ define i64 @remi64(i64 %a, i64 %b) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @remi32(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: remi32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = srem i32 %a, %b
ret i32 %r
}
@ -54,11 +54,11 @@ define i128 @remu128(i128 %a, i128 %b) {
; Function Attrs: norecurse nounwind readnone
define i64 @remu64(i64 %a, i64 %b) {
; CHECK-LABEL: remu64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s2, %s0, %s1
; CHECK-NEXT: muls.l %s1, %s2, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = urem i64 %a, %b
ret i64 %r
}
@ -66,12 +66,12 @@ define i64 @remu64(i64 %a, i64 %b) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @remu32(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: remu32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = urem i32 %a, %b
ret i32 %r
}
@ -79,13 +79,13 @@ define zeroext i32 @remu32(i32 zeroext %a, i32 zeroext %b) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @remi16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: remi16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%a32 = sext i16 %a to i32
%b32 = sext i16 %b to i32
%r32 = srem i32 %a32, %b32
@ -96,12 +96,12 @@ define signext i16 @remi16(i16 signext %a, i16 signext %b) {
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: remu16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = urem i16 %a, %b
ret i16 %r
}
@ -109,13 +109,13 @@ define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) {
; Function Attrs: norecurse nounwind readnone
define signext i8 @remi8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: remi8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%a32 = sext i8 %a to i32
%b32 = sext i8 %b to i32
%r32 = srem i32 %a32, %b32
@ -126,12 +126,12 @@ define signext i8 @remi8(i8 signext %a, i8 signext %b) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @remu8(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: remu8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = urem i8 %a, %b
ret i8 %r
}
@ -154,11 +154,11 @@ define i128 @remi128ri(i128 %a) {
; Function Attrs: norecurse nounwind readnone
define i64 @remi64ri(i64 %a) {
; CHECK-LABEL: remi64ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s1, %s0, (62)0
; CHECK-NEXT: muls.l %s1, 3, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = srem i64 %a, 3
ret i64 %r
}
@ -166,12 +166,12 @@ define i64 @remi64ri(i64 %a) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @remi32ri(i32 signext %a) {
; CHECK-LABEL: remi32ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s1, %s0, (62)0
; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = srem i32 %a, 3
ret i32 %r
}
@ -194,11 +194,11 @@ define i128 @remu128ri(i128 %a) {
; Function Attrs: norecurse nounwind readnone
define i64 @remu64ri(i64 %a) {
; CHECK-LABEL: remu64ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s1, %s0, (62)0
; CHECK-NEXT: muls.l %s1, 3, %s1
; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = urem i64 %a, 3
ret i64 %r
}
@ -206,12 +206,12 @@ define i64 @remu64ri(i64 %a) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @remu32ri(i32 zeroext %a) {
; CHECK-LABEL: remu32ri:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s1, %s0, (62)0
; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = urem i32 %a, 3
ret i32 %r
}
@ -236,11 +236,11 @@ define i128 @remi128li(i128 %a) {
; Function Attrs: norecurse nounwind readnone
define i64 @remi64li(i64 %a, i64 %b) {
; CHECK-LABEL: remi64li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.l %s0, 3, %s1
; CHECK-NEXT: muls.l %s0, %s0, %s1
; CHECK-NEXT: subs.l %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = srem i64 3, %b
ret i64 %r
}
@ -248,12 +248,12 @@ define i64 @remi64li(i64 %a, i64 %b) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @remi32li(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: remi32li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divs.w.sx %s0, 3, %s1
; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
; CHECK-NEXT: subs.w.sx %s0, 3, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = srem i32 3, %b
ret i32 %r
}
@ -278,11 +278,11 @@ define i128 @remu128li(i128) {
; Function Attrs: norecurse nounwind readnone
define i64 @remu64li(i64 %a, i64 %b) {
; CHECK-LABEL: remu64li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.l %s0, 3, %s1
; CHECK-NEXT: muls.l %s0, %s0, %s1
; CHECK-NEXT: subs.l %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = urem i64 3, %b
ret i64 %r
}
@ -290,12 +290,12 @@ define i64 @remu64li(i64 %a, i64 %b) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @remu32li(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: remu32li:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: divu.w %s0, 3, %s1
; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
; CHECK-NEXT: subs.w.sx %s0, 3, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%r = urem i32 3, %b
ret i32 %r
}

64
llvm/test/CodeGen/VE/Scalar/right_shift.ll
View File

@ -2,10 +2,10 @@
define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i8 %0 to i32
%4 = sext i8 %1 to i32
%5 = ashr i32 %3, %4
@ -15,10 +15,10 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i16 %0 to i32
%4 = sext i16 %1 to i32
%5 = ashr i32 %3, %4
@ -28,29 +28,29 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = ashr i32 %0, %1
ret i32 %3
}
define i64 @func4(i64 %0, i64 %1) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = ashr i64 %0, %1
ret i64 %3
}
define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i8 %0 to i32
%4 = zext i8 %1 to i32
%5 = lshr i32 %3, %4
@ -60,11 +60,11 @@ define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i16 %0 to i32
%4 = zext i16 %1 to i32
%5 = lshr i32 %3, %4
@ -74,98 +74,98 @@ define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) {
define i32 @func9(i32 %0, i32 %1) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = lshr i32 %0, %1
ret i32 %3
}
define i64 @func10(i64 %0, i64 %1) {
; CHECK-LABEL: func10:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = lshr i64 %0, %1
ret i64 %3
}
define signext i8 @func12(i8 signext %0) {
; CHECK-LABEL: func12:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 5
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i8 %0, 5
ret i8 %2
}
define signext i16 @func13(i16 signext %0) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 5
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i16 %0, 5
ret i16 %2
}
define i32 @func14(i32 %0) {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i32 %0, 5
ret i32 %2
}
define i64 @func15(i64 %0) {
; CHECK-LABEL: func15:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i64 %0, 5
ret i64 %2
}
define zeroext i8 @func17(i8 zeroext %0) {
; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i8 %0, 5
ret i8 %2
}
define zeroext i16 @func18(i16 zeroext %0) {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i16 %0, 5
ret i16 %2
}
define i32 @func19(i32 %0) {
; CHECK-LABEL: func19:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i32 %0, 5
ret i32 %2
}
define i64 @func20(i64 %0) {
; CHECK-LABEL: func20:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i64 %0, 5
ret i64 %2
}

8
llvm/test/CodeGen/VE/Scalar/rotl.ll
View File

@ -2,13 +2,13 @@
define i64 @func1(i64 %a, i32 %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s2, %s0, %s1
; CHECK-NEXT: lea %s3, 64
; CHECK-NEXT: subs.w.sx %s1, %s3, %s1
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%b64 = zext i32 %b to i64
%a.sl = shl i64 %a, %b64
%b.inv = sub nsw i32 64, %b
@ -20,13 +20,13 @@ define i64 @func1(i64 %a, i32 %b) {
define i32 @func2(i32 %a, i32 %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s2, %s0, %s1
; CHECK-NEXT: subs.w.sx %s1, 32, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%a.sl = shl i32 %a, %b
%b.inv = sub nsw i32 32, %b
%a.sr = lshr i32 %a, %b.inv

8
llvm/test/CodeGen/VE/Scalar/rotr.ll
View File

@ -2,13 +2,13 @@
define i64 @func1(i64 %a, i32 %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: srl %s2, %s0, %s1
; CHECK-NEXT: lea %s3, 64
; CHECK-NEXT: subs.w.sx %s1, %s3, %s1
; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%b64 = zext i32 %b to i64
%a.lr = lshr i64 %a, %b64
%b.inv = sub nsw i32 64, %b
@ -20,13 +20,13 @@ define i64 @func1(i64 %a, i32 %b) {
define i32 @func2(i32 %a, i32 %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s2, %s0, (32)0
; CHECK-NEXT: srl %s2, %s2, %s1
; CHECK-NEXT: subs.w.sx %s1, 32, %s1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%a.lr = lshr i32 %a, %b
%b.inv = sub nsw i32 32, %b
%a.sl = shl i32 %a, %b.inv

168
llvm/test/CodeGen/VE/Scalar/select.ll
View File

@ -41,10 +41,10 @@
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_i1_var(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2) {
; CHECK-LABEL: select_i1_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i1 %1, i1 %2
ret i1 %4
}
@ -52,10 +52,10 @@ define zeroext i1 @select_i1_var(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2) {
; Function Attrs: norecurse nounwind readnone
define signext i8 @select_i8_var(i1 zeroext %0, i8 signext %1, i8 signext %2) {
; CHECK-LABEL: select_i8_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i8 %1, i8 %2
ret i8 %4
}
@ -63,10 +63,10 @@ define signext i8 @select_i8_var(i1 zeroext %0, i8 signext %1, i8 signext %2) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_u8_var(i1 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
; CHECK-LABEL: select_u8_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i8 %1, i8 %2
ret i8 %4
}
@ -74,10 +74,10 @@ define zeroext i8 @select_u8_var(i1 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @select_i16_var(i1 zeroext %0, i16 signext %1, i16 signext %2) {
; CHECK-LABEL: select_i16_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i16 %1, i16 %2
ret i16 %4
}
@ -85,10 +85,10 @@ define signext i16 @select_i16_var(i1 zeroext %0, i16 signext %1, i16 signext %2
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_u16_var(i1 zeroext %0, i16 zeroext %1, i16 zeroext %2) {
; CHECK-LABEL: select_u16_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i16 %1, i16 %2
ret i16 %4
}
@ -96,10 +96,10 @@ define zeroext i16 @select_u16_var(i1 zeroext %0, i16 zeroext %1, i16 zeroext %2
; Function Attrs: norecurse nounwind readnone
define signext i32 @select_i32_var(i1 zeroext %0, i32 signext %1, i32 signext %2) {
; CHECK-LABEL: select_i32_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i32 %1, i32 %2
ret i32 %4
}
@ -107,10 +107,10 @@ define signext i32 @select_i32_var(i1 zeroext %0, i32 signext %1, i32 signext %2
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_u32_var(i1 zeroext %0, i32 zeroext %1, i32 zeroext %2) {
; CHECK-LABEL: select_u32_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i32 %1, i32 %2
ret i32 %4
}
@ -118,11 +118,11 @@ define zeroext i32 @select_u32_var(i1 zeroext %0, i32 zeroext %1, i32 zeroext %2
; Function Attrs: norecurse nounwind readnone
define i64 @select_i64_var(i1 zeroext %0, i64 %1, i64 %2) {
; CHECK-LABEL: select_i64_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i64 %1, i64 %2
ret i64 %4
}
@ -130,11 +130,11 @@ define i64 @select_i64_var(i1 zeroext %0, i64 %1, i64 %2) {
; Function Attrs: norecurse nounwind readnone
define i64 @select_u64_var(i1 zeroext %0, i64 %1, i64 %2) {
; CHECK-LABEL: select_u64_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i64 %1, i64 %2
ret i64 %4
}
@ -142,13 +142,13 @@ define i64 @select_u64_var(i1 zeroext %0, i64 %1, i64 %2) {
; Function Attrs: norecurse nounwind readnone
define i128 @select_i128_var(i1 zeroext %0, i128 %1, i128 %2) {
; CHECK-LABEL: select_i128_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s1, 0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i128 %1, i128 %2
ret i128 %4
}
@ -156,13 +156,13 @@ define i128 @select_i128_var(i1 zeroext %0, i128 %1, i128 %2) {
; Function Attrs: norecurse nounwind readnone
define i128 @select_u128_var(i1 zeroext %0, i128 %1, i128 %2) {
; CHECK-LABEL: select_u128_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s1, 0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select i1 %0, i128 %1, i128 %2
ret i128 %4
}
@ -170,11 +170,11 @@ define i128 @select_u128_var(i1 zeroext %0, i128 %1, i128 %2) {
; Function Attrs: norecurse nounwind readnone
define float @select_float_var(i1 zeroext %0, float %1, float %2) {
; CHECK-LABEL: select_float_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select fast i1 %0, float %1, float %2
ret float %4
}
@ -182,11 +182,11 @@ define float @select_float_var(i1 zeroext %0, float %1, float %2) {
; Function Attrs: norecurse nounwind readnone
define double @select_double_var(i1 zeroext %0, double %1, double %2) {
; CHECK-LABEL: select_double_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select fast i1 %0, double %1, double %2
ret double %4
}
@ -194,13 +194,13 @@ define double @select_double_var(i1 zeroext %0, double %1, double %2) {
; Function Attrs: norecurse nounwind readnone
define fp128 @select_quad_var(i1 zeroext %0, fp128 %1, fp128 %2) {
; CHECK-LABEL: select_quad_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = select fast i1 %0, fp128 %1, fp128 %2
ret fp128 %4
}
@ -208,9 +208,9 @@ define fp128 @select_quad_var(i1 zeroext %0, fp128 %1, fp128 %2) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_i1_mimm(i1 zeroext %0, i1 zeroext %1) {
; CHECK-LABEL: select_i1_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = or i1 %0, %1
ret i1 %3
}
@ -218,10 +218,10 @@ define zeroext i1 @select_i1_mimm(i1 zeroext %0, i1 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define signext i8 @select_i8_mimm(i1 zeroext %0, i8 signext %1) {
; CHECK-LABEL: select_i8_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (57)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i8 -128, i8 %1
ret i8 %3
}
@ -229,10 +229,10 @@ define signext i8 @select_i8_mimm(i1 zeroext %0, i8 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_u8_mimm(i1 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: select_u8_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (57)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i8 127, i8 %1
ret i8 %3
}
@ -240,10 +240,10 @@ define zeroext i8 @select_u8_mimm(i1 zeroext %0, i8 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @select_i16_mimm(i1 zeroext %0, i16 signext %1) {
; CHECK-LABEL: select_i16_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (49)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i16 -32768, i16 %1
ret i16 %3
}
@ -251,10 +251,10 @@ define signext i16 @select_i16_mimm(i1 zeroext %0, i16 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_u16_mimm(i1 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: select_u16_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (49)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i16 32767, i16 %1
ret i16 %3
}
@ -262,10 +262,10 @@ define zeroext i16 @select_u16_mimm(i1 zeroext %0, i16 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @select_i32_mimm(i1 zeroext %0, i32 signext %1) {
; CHECK-LABEL: select_i32_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i32 65535, i32 %1
ret i32 %3
}
@ -273,10 +273,10 @@ define signext i32 @select_i32_mimm(i1 zeroext %0, i32 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_u32_mimm(i1 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: select_u32_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i32 65535, i32 %1
ret i32 %3
}
@ -284,11 +284,11 @@ define zeroext i32 @select_u32_mimm(i1 zeroext %0, i32 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define i64 @select_i64_mimm(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_i64_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i64 65535, i64 %1
ret i64 %3
}
@ -296,11 +296,11 @@ define i64 @select_i64_mimm(i1 zeroext %0, i64 %1) {
; Function Attrs: norecurse nounwind readnone
define i64 @select_u64_mimm(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_u64_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i64 65535, i64 %1
ret i64 %3
}
@ -308,13 +308,13 @@ define i64 @select_u64_mimm(i1 zeroext %0, i64 %1) {
; Function Attrs: norecurse nounwind readnone
define i128 @select_i128_mimm(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_i128_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i128 65535, i128 %1
ret i128 %3
}
@ -322,13 +322,13 @@ define i128 @select_i128_mimm(i1 zeroext %0, i128 %1) {
; Function Attrs: norecurse nounwind readnone
define i128 @select_u128_mimm(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_u128_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i128 65535, i128 %1
ret i128 %3
}
@ -336,11 +336,11 @@ define i128 @select_u128_mimm(i1 zeroext %0, i128 %1) {
; Function Attrs: norecurse nounwind readnone
define float @select_float_mimm(i1 zeroext %0, float %1) {
; CHECK-LABEL: select_float_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, float -2.000000e+00, float %1
ret float %3
}
@ -348,11 +348,11 @@ define float @select_float_mimm(i1 zeroext %0, float %1) {
; Function Attrs: norecurse nounwind readnone
define double @select_double_mimm(i1 zeroext %0, double %1) {
; CHECK-LABEL: select_double_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select fast i1 %0, double -2.000000e+00, double %1
ret double %3
}
@ -360,7 +360,7 @@ define double @select_double_mimm(i1 zeroext %0, double %1) {
; Function Attrs: norecurse nounwind readnone
define fp128 @select_quad_mimm(i1 zeroext %0, fp128 %1) {
; CHECK-LABEL: select_quad_mimm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1)
@ -371,7 +371,7 @@ define fp128 @select_quad_mimm(i1 zeroext %0, fp128 %1) {
; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s1, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select fast i1 %0, fp128 0xL0000000000000000C000000000000000, fp128 %1
ret fp128 %3
}
@ -379,10 +379,10 @@ define fp128 @select_quad_mimm(i1 zeroext %0, fp128 %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @select_mimm_i1(i1 zeroext %0, i1 zeroext %1) {
; CHECK-LABEL: select_mimm_i1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, 1, %s0
; CHECK-NEXT: or %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %0, true
%4 = or i1 %3, %1
ret i1 %4
@ -391,10 +391,10 @@ define zeroext i1 @select_mimm_i1(i1 zeroext %0, i1 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define signext i8 @select_mimm_i8(i1 zeroext %0, i8 signext %1) {
; CHECK-LABEL: select_mimm_i8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (57)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i8 %1, i8 -128
ret i8 %3
}
@ -402,10 +402,10 @@ define signext i8 @select_mimm_i8(i1 zeroext %0, i8 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @select_mimm_u8(i1 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: select_mimm_u8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (57)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i8 %1, i8 127
ret i8 %3
}
@ -413,10 +413,10 @@ define zeroext i8 @select_mimm_u8(i1 zeroext %0, i8 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @select_mimm_i16(i1 zeroext %0, i16 signext %1) {
; CHECK-LABEL: select_mimm_i16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (49)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i16 %1, i16 -32768
ret i16 %3
}
@ -424,10 +424,10 @@ define signext i16 @select_mimm_i16(i1 zeroext %0, i16 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @select_mimm_u16(i1 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: select_mimm_u16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (49)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i16 %1, i16 32767
ret i16 %3
}
@ -435,10 +435,10 @@ define zeroext i16 @select_mimm_u16(i1 zeroext %0, i16 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @select_mimm_i32(i1 zeroext %0, i32 signext %1) {
; CHECK-LABEL: select_mimm_i32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i32 %1, i32 65535
ret i32 %3
}
@ -446,10 +446,10 @@ define signext i32 @select_mimm_i32(i1 zeroext %0, i32 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @select_mimm_u32(i1 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: select_mimm_u32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i32 %1, i32 65535
ret i32 %3
}
@ -457,11 +457,11 @@ define zeroext i32 @select_mimm_u32(i1 zeroext %0, i32 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define i64 @select_mimm_i64(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_mimm_i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i64 %1, i64 65535
ret i64 %3
}
@ -469,11 +469,11 @@ define i64 @select_mimm_i64(i1 zeroext %0, i64 %1) {
; Function Attrs: norecurse nounwind readnone
define i64 @select_mimm_u64(i1 zeroext %0, i64 %1) {
; CHECK-LABEL: select_mimm_u64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i64 %1, i64 65535
ret i64 %3
}
@ -481,13 +481,13 @@ define i64 @select_mimm_u64(i1 zeroext %0, i64 %1) {
; Function Attrs: norecurse nounwind readnone
define i128 @select_mimm_i128(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_mimm_i128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i128 %1, i128 65535
ret i128 %3
}
@ -495,13 +495,13 @@ define i128 @select_mimm_i128(i1 zeroext %0, i128 %1) {
; Function Attrs: norecurse nounwind readnone
define i128 @select_mimm_u128(i1 zeroext %0, i128 %1) {
; CHECK-LABEL: select_mimm_u128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s1, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, i128 %1, i128 65535
ret i128 %3
}
@ -509,11 +509,11 @@ define i128 @select_mimm_u128(i1 zeroext %0, i128 %1) {
; Function Attrs: norecurse nounwind readnone
define float @select_mimm_float(i1 zeroext %0, float %1) {
; CHECK-LABEL: select_mimm_float:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select i1 %0, float %1, float -2.000000e+00
ret float %3
}
@ -521,11 +521,11 @@ define float @select_mimm_float(i1 zeroext %0, float %1) {
; Function Attrs: norecurse nounwind readnone
define double @select_mimm_double(i1 zeroext %0, double %1) {
; CHECK-LABEL: select_mimm_double:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select fast i1 %0, double %1, double -2.000000e+00
ret double %3
}
@ -533,7 +533,7 @@ define double @select_mimm_double(i1 zeroext %0, double %1) {
; Function Attrs: norecurse nounwind readnone
define fp128 @select_mimm_quad(i1 zeroext %0, fp128 %1) {
; CHECK-LABEL: select_mimm_quad:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1)
@ -544,7 +544,7 @@ define fp128 @select_mimm_quad(i1 zeroext %0, fp128 %1) {
; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = select fast i1 %0, fp128 %1, fp128 0xL0000000000000000C000000000000000
ret fp128 %3
}

784
llvm/test/CodeGen/VE/Scalar/select_cc.ll
View File

File diff suppressed because it is too large Load Diff

64
llvm/test/CodeGen/VE/Scalar/selectccf32.ll
View File

@ -2,9 +2,9 @@
define float @selectccaf(float, float, float, float) {
; CHECK-LABEL: selectccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp false float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -12,9 +12,9 @@ define float @selectccaf(float, float, float, float) {
define float @selectccat(float, float, float, float) {
; CHECK-LABEL: selectccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp true float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -22,11 +22,11 @@ define float @selectccat(float, float, float, float) {
define float @selectccoeq(float, float, float, float) {
; CHECK-LABEL: selectccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oeq float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -34,11 +34,11 @@ define float @selectccoeq(float, float, float, float) {
define float @selectccone(float, float, float, float) {
; CHECK-LABEL: selectccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp one float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -46,11 +46,11 @@ define float @selectccone(float, float, float, float) {
define float @selectccogt(float, float, float, float) {
; CHECK-LABEL: selectccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -58,11 +58,11 @@ define float @selectccogt(float, float, float, float) {
define float @selectccoge(float, float, float, float) {
; CHECK-LABEL: selectccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oge float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -70,11 +70,11 @@ define float @selectccoge(float, float, float, float) {
define float @selectccolt(float, float, float, float) {
; CHECK-LABEL: selectccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp olt float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -82,11 +82,11 @@ define float @selectccolt(float, float, float, float) {
define float @selectccole(float, float, float, float) {
; CHECK-LABEL: selectccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ole float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -94,11 +94,11 @@ define float @selectccole(float, float, float, float) {
define float @selectccord(float, float, float, float) {
; CHECK-LABEL: selectccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.num %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ord float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -106,11 +106,11 @@ define float @selectccord(float, float, float, float) {
define float @selectccuno(float, float, float, float) {
; CHECK-LABEL: selectccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uno float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -118,11 +118,11 @@ define float @selectccuno(float, float, float, float) {
define float @selectccueq(float, float, float, float) {
; CHECK-LABEL: selectccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ueq float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -130,11 +130,11 @@ define float @selectccueq(float, float, float, float) {
define float @selectccune(float, float, float, float) {
; CHECK-LABEL: selectccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp une float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -142,11 +142,11 @@ define float @selectccune(float, float, float, float) {
define float @selectccugt(float, float, float, float) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ugt float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -154,11 +154,11 @@ define float @selectccugt(float, float, float, float) {
define float @selectccuge(float, float, float, float) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uge float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -166,11 +166,11 @@ define float @selectccuge(float, float, float, float) {
define float @selectccult(float, float, float, float) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ult float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -178,11 +178,11 @@ define float @selectccult(float, float, float, float) {
define float @selectccule(float, float, float, float) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ule float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6

28
llvm/test/CodeGen/VE/Scalar/selectccf32c.ll
View File

@ -2,7 +2,7 @@
define float @selectccsgti8(i8, i8, float, float) {
; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 56
; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56
@ -10,7 +10,7 @@ define float @selectccsgti8(i8, i8, float, float) {
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i8 %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -18,7 +18,7 @@ define float @selectccsgti8(i8, i8, float, float) {
define float @selectccsgti16(i16, i16, float, float) {
; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 48
; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48
@ -26,7 +26,7 @@ define float @selectccsgti16(i16, i16, float, float) {
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i16 %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -34,11 +34,11 @@ define float @selectccsgti16(i16, i16, float, float) {
define float @selectccsgti32(i32, i32, float, float) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -46,11 +46,11 @@ define float @selectccsgti32(i32, i32, float, float) {
define float @selectccsgti64(i64, i64, float, float) {
; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -58,7 +58,7 @@ define float @selectccsgti64(i64, i64, float, float) {
define float @selectccsgti128(i128, i128, float, float) {
; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1
@ -70,7 +70,7 @@ define float @selectccsgti128(i128, i128, float, float) {
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -78,11 +78,11 @@ define float @selectccsgti128(i128, i128, float, float) {
define float @selectccogtf32(float, float, float, float) {
; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6
@ -90,11 +90,11 @@ define float @selectccogtf32(float, float, float, float) {
define float @selectccogtf64(double, double, float, float) {
; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, %1
%6 = select i1 %5, float %2, float %3
ret float %6

64
llvm/test/CodeGen/VE/Scalar/selectccf32i.ll
View File

@ -2,9 +2,9 @@
define float @selectccaf(float, float, float, float) {
; CHECK-LABEL: selectccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp false float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -12,9 +12,9 @@ define float @selectccaf(float, float, float, float) {
define float @selectccat(float, float, float, float) {
; CHECK-LABEL: selectccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp true float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -22,12 +22,12 @@ define float @selectccat(float, float, float, float) {
define float @selectccoeq(float, float, float, float) {
; CHECK-LABEL: selectccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oeq float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -35,12 +35,12 @@ define float @selectccoeq(float, float, float, float) {
define float @selectccone(float, float, float, float) {
; CHECK-LABEL: selectccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp one float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -48,12 +48,12 @@ define float @selectccone(float, float, float, float) {
define float @selectccogt(float, float, float, float) {
; CHECK-LABEL: selectccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -61,12 +61,12 @@ define float @selectccogt(float, float, float, float) {
define float @selectccoge(float, float, float, float) {
; CHECK-LABEL: selectccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oge float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -74,12 +74,12 @@ define float @selectccoge(float, float, float, float) {
define float @selectccolt(float, float, float, float) {
; CHECK-LABEL: selectccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp olt float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -87,12 +87,12 @@ define float @selectccolt(float, float, float, float) {
define float @selectccole(float, float, float, float) {
; CHECK-LABEL: selectccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ole float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -100,11 +100,11 @@ define float @selectccole(float, float, float, float) {
define float @selectccord(float, float, float, float) {
; CHECK-LABEL: selectccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s0
; CHECK-NEXT: cmov.s.num %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ord float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -112,11 +112,11 @@ define float @selectccord(float, float, float, float) {
define float @selectccuno(float, float, float, float) {
; CHECK-LABEL: selectccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s0
; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uno float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -124,12 +124,12 @@ define float @selectccuno(float, float, float, float) {
define float @selectccueq(float, float, float, float) {
; CHECK-LABEL: selectccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ueq float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -137,12 +137,12 @@ define float @selectccueq(float, float, float, float) {
define float @selectccune(float, float, float, float) {
; CHECK-LABEL: selectccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp une float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -150,12 +150,12 @@ define float @selectccune(float, float, float, float) {
define float @selectccugt(float, float, float, float) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ugt float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -163,12 +163,12 @@ define float @selectccugt(float, float, float, float) {
define float @selectccuge(float, float, float, float) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uge float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -176,12 +176,12 @@ define float @selectccuge(float, float, float, float) {
define float @selectccult(float, float, float, float) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ult float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6
@ -189,12 +189,12 @@ define float @selectccult(float, float, float, float) {
define float @selectccule(float, float, float, float) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ule float %0, 0.0
%6 = select i1 %5, float %2, float %3
ret float %6

64
llvm/test/CodeGen/VE/Scalar/selectccf64.ll
View File

@ -2,9 +2,9 @@
define double @selectccaf(double, double, double, double) {
; CHECK-LABEL: selectccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp false double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -12,9 +12,9 @@ define double @selectccaf(double, double, double, double) {
define double @selectccat(double, double, double, double) {
; CHECK-LABEL: selectccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp true double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -22,11 +22,11 @@ define double @selectccat(double, double, double, double) {
define double @selectccoeq(double, double, double, double) {
; CHECK-LABEL: selectccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oeq double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -34,11 +34,11 @@ define double @selectccoeq(double, double, double, double) {
define double @selectccone(double, double, double, double) {
; CHECK-LABEL: selectccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp one double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -46,11 +46,11 @@ define double @selectccone(double, double, double, double) {
define double @selectccogt(double, double, double, double) {
; CHECK-LABEL: selectccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -58,11 +58,11 @@ define double @selectccogt(double, double, double, double) {
define double @selectccoge(double, double, double, double) {
; CHECK-LABEL: selectccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oge double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -70,11 +70,11 @@ define double @selectccoge(double, double, double, double) {
define double @selectccolt(double, double, double, double) {
; CHECK-LABEL: selectccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp olt double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -82,11 +82,11 @@ define double @selectccolt(double, double, double, double) {
define double @selectccole(double, double, double, double) {
; CHECK-LABEL: selectccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ole double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -94,11 +94,11 @@ define double @selectccole(double, double, double, double) {
define double @selectccord(double, double, double, double) {
; CHECK-LABEL: selectccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.num %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ord double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -106,11 +106,11 @@ define double @selectccord(double, double, double, double) {
define double @selectccuno(double, double, double, double) {
; CHECK-LABEL: selectccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.nan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uno double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -118,11 +118,11 @@ define double @selectccuno(double, double, double, double) {
define double @selectccueq(double, double, double, double) {
; CHECK-LABEL: selectccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ueq double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -130,11 +130,11 @@ define double @selectccueq(double, double, double, double) {
define double @selectccune(double, double, double, double) {
; CHECK-LABEL: selectccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp une double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -142,11 +142,11 @@ define double @selectccune(double, double, double, double) {
define double @selectccugt(double, double, double, double) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ugt double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -154,11 +154,11 @@ define double @selectccugt(double, double, double, double) {
define double @selectccuge(double, double, double, double) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uge double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -166,11 +166,11 @@ define double @selectccuge(double, double, double, double) {
define double @selectccult(double, double, double, double) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ult double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -178,11 +178,11 @@ define double @selectccult(double, double, double, double) {
define double @selectccule(double, double, double, double) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ule double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6

28
llvm/test/CodeGen/VE/Scalar/selectccf64c.ll
View File

@ -2,7 +2,7 @@
define double @selectccsgti8(i8, i8, double, double) {
; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 56
; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56
@ -10,7 +10,7 @@ define double @selectccsgti8(i8, i8, double, double) {
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i8 %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -18,7 +18,7 @@ define double @selectccsgti8(i8, i8, double, double) {
define double @selectccsgti16(i16, i16, double, double) {
; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 48
; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48
@ -26,7 +26,7 @@ define double @selectccsgti16(i16, i16, double, double) {
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i16 %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -34,11 +34,11 @@ define double @selectccsgti16(i16, i16, double, double) {
define double @selectccsgti32(i32, i32, double, double) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -46,11 +46,11 @@ define double @selectccsgti32(i32, i32, double, double) {
define double @selectccsgti64(i64, i64, double, double) {
; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -58,7 +58,7 @@ define double @selectccsgti64(i64, i64, double, double) {
define double @selectccsgti128(i128, i128, double, double) {
; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1
@ -70,7 +70,7 @@ define double @selectccsgti128(i128, i128, double, double) {
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -78,11 +78,11 @@ define double @selectccsgti128(i128, i128, double, double) {
define double @selectccogtf32(float, float, double, double) {
; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6
@ -90,11 +90,11 @@ define double @selectccogtf32(float, float, double, double) {
define double @selectccogtf64(double, double, double, double) {
; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, %1
%6 = select i1 %5, double %2, double %3
ret double %6

64
llvm/test/CodeGen/VE/Scalar/selectccf64i.ll
View File

@ -2,9 +2,9 @@
define double @selectccaf(double, double, double, double) {
; CHECK-LABEL: selectccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp false double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -12,9 +12,9 @@ define double @selectccaf(double, double, double, double) {
define double @selectccat(double, double, double, double) {
; CHECK-LABEL: selectccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp true double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -22,12 +22,12 @@ define double @selectccat(double, double, double, double) {
define double @selectccoeq(double, double, double, double) {
; CHECK-LABEL: selectccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oeq double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -35,12 +35,12 @@ define double @selectccoeq(double, double, double, double) {
define double @selectccone(double, double, double, double) {
; CHECK-LABEL: selectccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp one double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -48,12 +48,12 @@ define double @selectccone(double, double, double, double) {
define double @selectccogt(double, double, double, double) {
; CHECK-LABEL: selectccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -61,12 +61,12 @@ define double @selectccogt(double, double, double, double) {
define double @selectccoge(double, double, double, double) {
; CHECK-LABEL: selectccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp oge double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -74,12 +74,12 @@ define double @selectccoge(double, double, double, double) {
define double @selectccolt(double, double, double, double) {
; CHECK-LABEL: selectccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp olt double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -87,12 +87,12 @@ define double @selectccolt(double, double, double, double) {
define double @selectccole(double, double, double, double) {
; CHECK-LABEL: selectccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ole double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -100,11 +100,11 @@ define double @selectccole(double, double, double, double) {
define double @selectccord(double, double, double, double) {
; CHECK-LABEL: selectccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s0
; CHECK-NEXT: cmov.d.num %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ord double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -112,11 +112,11 @@ define double @selectccord(double, double, double, double) {
define double @selectccuno(double, double, double, double) {
; CHECK-LABEL: selectccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s0
; CHECK-NEXT: cmov.d.nan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uno double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -124,12 +124,12 @@ define double @selectccuno(double, double, double, double) {
define double @selectccueq(double, double, double, double) {
; CHECK-LABEL: selectccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ueq double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -137,12 +137,12 @@ define double @selectccueq(double, double, double, double) {
define double @selectccune(double, double, double, double) {
; CHECK-LABEL: selectccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp une double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -150,12 +150,12 @@ define double @selectccune(double, double, double, double) {
define double @selectccugt(double, double, double, double) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ugt double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -163,12 +163,12 @@ define double @selectccugt(double, double, double, double) {
define double @selectccuge(double, double, double, double) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp uge double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -176,12 +176,12 @@ define double @selectccuge(double, double, double, double) {
define double @selectccult(double, double, double, double) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ult double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6
@ -189,12 +189,12 @@ define double @selectccult(double, double, double, double) {
define double @selectccule(double, double, double, double) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ule double %0, 0.0
%6 = select i1 %5, double %2, double %3
ret double %6

56
llvm/test/CodeGen/VE/Scalar/selectcci32.ll
View File

@ -2,11 +2,11 @@
define i32 @selectcceq(i32, i32, i32, i32) {
; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -14,11 +14,11 @@ define i32 @selectcceq(i32, i32, i32, i32) {
define i32 @selectccne(i32, i32, i32, i32) {
; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ne i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -26,11 +26,11 @@ define i32 @selectccne(i32, i32, i32, i32) {
define i32 @selectccsgt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -38,11 +38,11 @@ define i32 @selectccsgt(i32, i32, i32, i32) {
define i32 @selectccsge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -50,11 +50,11 @@ define i32 @selectccsge(i32, i32, i32, i32) {
define i32 @selectccslt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp slt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -62,11 +62,11 @@ define i32 @selectccslt(i32, i32, i32, i32) {
define i32 @selectccsle(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sle i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -74,11 +74,11 @@ define i32 @selectccsle(i32, i32, i32, i32) {
define i32 @selectccugt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -86,11 +86,11 @@ define i32 @selectccugt(i32, i32, i32, i32) {
define i32 @selectccuge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -98,11 +98,11 @@ define i32 @selectccuge(i32, i32, i32, i32) {
define i32 @selectccult(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -110,11 +110,11 @@ define i32 @selectccult(i32, i32, i32, i32) {
define i32 @selectccule(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -122,11 +122,11 @@ define i32 @selectccule(i32, i32, i32, i32) {
define i32 @selectccugt2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -134,11 +134,11 @@ define i32 @selectccugt2(i32, i32, i32, i32) {
define i32 @selectccuge2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -146,11 +146,11 @@ define i32 @selectccuge2(i32, i32, i32, i32) {
define i32 @selectccult2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -158,11 +158,11 @@ define i32 @selectccult2(i32, i32, i32, i32) {
define i32 @selectccule2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6

28
llvm/test/CodeGen/VE/Scalar/selectcci32c.ll
View File

@ -2,7 +2,7 @@
define i32 @selectccsgti8(i8, i8, i32, i32) {
; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 56
; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56
@ -10,7 +10,7 @@ define i32 @selectccsgti8(i8, i8, i32, i32) {
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i8 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -18,7 +18,7 @@ define i32 @selectccsgti8(i8, i8, i32, i32) {
define i32 @selectccsgti16(i16, i16, i32, i32) {
; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 48
; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48
@ -26,7 +26,7 @@ define i32 @selectccsgti16(i16, i16, i32, i32) {
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i16 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -34,11 +34,11 @@ define i32 @selectccsgti16(i16, i16, i32, i32) {
define i32 @selectccsgti32(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -46,11 +46,11 @@ define i32 @selectccsgti32(i32, i32, i32, i32) {
define i32 @selectccsgti64(i64, i64, i32, i32) {
; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -58,7 +58,7 @@ define i32 @selectccsgti64(i64, i64, i32, i32) {
define i32 @selectccsgti128(i128, i128, i32, i32) {
; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1
@ -70,7 +70,7 @@ define i32 @selectccsgti128(i128, i128, i32, i32) {
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -78,11 +78,11 @@ define i32 @selectccsgti128(i128, i128, i32, i32) {
define i32 @selectccogtf32(float, float, i32, i32) {
; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -90,11 +90,11 @@ define i32 @selectccogtf32(float, float, i32, i32) {
define i32 @selectccogtf64(double, double, i32, i32) {
; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, %1
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6

56
llvm/test/CodeGen/VE/Scalar/selectcci32i.ll
View File

@ -2,12 +2,12 @@
define i32 @selectcceq(i32, i32, i32, i32) {
; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -15,12 +15,12 @@ define i32 @selectcceq(i32, i32, i32, i32) {
define i32 @selectccne(i32, i32, i32, i32) {
; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ne i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -28,12 +28,12 @@ define i32 @selectccne(i32, i32, i32, i32) {
define i32 @selectccsgt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -41,12 +41,12 @@ define i32 @selectccsgt(i32, i32, i32, i32) {
define i32 @selectccsge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -54,12 +54,12 @@ define i32 @selectccsge(i32, i32, i32, i32) {
define i32 @selectccslt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp slt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -67,12 +67,12 @@ define i32 @selectccslt(i32, i32, i32, i32) {
define i32 @selectccsle(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sle i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -80,12 +80,12 @@ define i32 @selectccsle(i32, i32, i32, i32) {
define i32 @selectccugt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -93,12 +93,12 @@ define i32 @selectccugt(i32, i32, i32, i32) {
define i32 @selectccuge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -106,12 +106,12 @@ define i32 @selectccuge(i32, i32, i32, i32) {
define i32 @selectccult(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -119,12 +119,12 @@ define i32 @selectccult(i32, i32, i32, i32) {
define i32 @selectccule(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -132,12 +132,12 @@ define i32 @selectccule(i32, i32, i32, i32) {
define i32 @selectccugt2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -145,12 +145,12 @@ define i32 @selectccugt2(i32, i32, i32, i32) {
define i32 @selectccuge2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -158,12 +158,12 @@ define i32 @selectccuge2(i32, i32, i32, i32) {
define i32 @selectccult2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6
@ -171,12 +171,12 @@ define i32 @selectccult2(i32, i32, i32, i32) {
define i32 @selectccule2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
ret i32 %6

56
llvm/test/CodeGen/VE/Scalar/selectcci64.ll
View File

@ -2,11 +2,11 @@
define i64 @selectcceq(i64, i64, i64, i64) {
; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -14,11 +14,11 @@ define i64 @selectcceq(i64, i64, i64, i64) {
define i64 @selectccne(i64, i64, i64, i64) {
; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ne i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -26,11 +26,11 @@ define i64 @selectccne(i64, i64, i64, i64) {
define i64 @selectccsgt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -38,11 +38,11 @@ define i64 @selectccsgt(i64, i64, i64, i64) {
define i64 @selectccsge(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sge i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -50,11 +50,11 @@ define i64 @selectccsge(i64, i64, i64, i64) {
define i64 @selectccslt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp slt i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -62,11 +62,11 @@ define i64 @selectccslt(i64, i64, i64, i64) {
define i64 @selectccsle(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sle i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -74,11 +74,11 @@ define i64 @selectccsle(i64, i64, i64, i64) {
define i64 @selectccugt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -86,11 +86,11 @@ define i64 @selectccugt(i64, i64, i64, i64) {
define i64 @selectccuge(i64, i64, i64, i64) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -98,11 +98,11 @@ define i64 @selectccuge(i64, i64, i64, i64) {
define i64 @selectccult(i64, i64, i64, i64) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -110,11 +110,11 @@ define i64 @selectccult(i64, i64, i64, i64) {
define i64 @selectccule(i64, i64, i64, i64) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -122,11 +122,11 @@ define i64 @selectccule(i64, i64, i64, i64) {
define i64 @selectccugt2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -134,11 +134,11 @@ define i64 @selectccugt2(i64, i64, i64, i64) {
define i64 @selectccuge2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -146,11 +146,11 @@ define i64 @selectccuge2(i64, i64, i64, i64) {
define i64 @selectccult2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -158,11 +158,11 @@ define i64 @selectccult2(i64, i64, i64, i64) {
define i64 @selectccule2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6

28
llvm/test/CodeGen/VE/Scalar/selectcci64c.ll
View File

@ -2,7 +2,7 @@
define i64 @selectccsgti8(i8, i8, i64, i64) {
; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 56
; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56
@ -10,7 +10,7 @@ define i64 @selectccsgti8(i8, i8, i64, i64) {
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i8 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -18,7 +18,7 @@ define i64 @selectccsgti8(i8, i8, i64, i64) {
define i64 @selectccsgti16(i16, i16, i64, i64) {
; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s1, 48
; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48
@ -26,7 +26,7 @@ define i64 @selectccsgti16(i16, i16, i64, i64) {
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i16 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -34,11 +34,11 @@ define i64 @selectccsgti16(i16, i16, i64, i64) {
define i64 @selectccsgti32(i32, i32, i64, i64) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -46,11 +46,11 @@ define i64 @selectccsgti32(i32, i32, i64, i64) {
define i64 @selectccsgti64(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -58,7 +58,7 @@ define i64 @selectccsgti64(i64, i64, i64, i64) {
define i64 @selectccsgti128(i128, i128, i64, i64) {
; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1
; CHECK-NEXT: or %s6, 0, (0)1
@ -70,7 +70,7 @@ define i64 @selectccsgti128(i128, i128, i64, i64) {
; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -78,11 +78,11 @@ define i64 @selectccsgti128(i128, i128, i64, i64) {
define i64 @selectccogtf32(float, float, i64, i64) {
; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt float %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -90,11 +90,11 @@ define i64 @selectccogtf32(float, float, i64, i64) {
define i64 @selectccogtf64(double, double, i64, i64) {
; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = fcmp ogt double %0, %1
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6

56
llvm/test/CodeGen/VE/Scalar/selectcci64i.ll
View File

@ -2,12 +2,12 @@
define i64 @selectcceq(i64, i64, i64, i64) {
; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp eq i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -15,12 +15,12 @@ define i64 @selectcceq(i64, i64, i64, i64) {
define i64 @selectccne(i64, i64, i64, i64) {
; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ne i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -28,12 +28,12 @@ define i64 @selectccne(i64, i64, i64, i64) {
define i64 @selectccsgt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -41,12 +41,12 @@ define i64 @selectccsgt(i64, i64, i64, i64) {
define i64 @selectccsge(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sge i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -54,12 +54,12 @@ define i64 @selectccsge(i64, i64, i64, i64) {
define i64 @selectccslt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp slt i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -67,12 +67,12 @@ define i64 @selectccslt(i64, i64, i64, i64) {
define i64 @selectccsle(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sle i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -80,12 +80,12 @@ define i64 @selectccsle(i64, i64, i64, i64) {
define i64 @selectccugt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -93,12 +93,12 @@ define i64 @selectccugt(i64, i64, i64, i64) {
define i64 @selectccuge(i64, i64, i64, i64) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -106,12 +106,12 @@ define i64 @selectccuge(i64, i64, i64, i64) {
define i64 @selectccult(i64, i64, i64, i64) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -119,12 +119,12 @@ define i64 @selectccult(i64, i64, i64, i64) {
define i64 @selectccule(i64, i64, i64, i64) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -132,12 +132,12 @@ define i64 @selectccule(i64, i64, i64, i64) {
define i64 @selectccugt2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -145,12 +145,12 @@ define i64 @selectccugt2(i64, i64, i64, i64) {
define i64 @selectccuge2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -158,12 +158,12 @@ define i64 @selectccuge2(i64, i64, i64, i64) {
define i64 @selectccult2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6
@ -171,12 +171,12 @@ define i64 @selectccult2(i64, i64, i64, i64) {
define i64 @selectccule2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i64 %0, 12
%6 = select i1 %5, i64 %2, i64 %3
ret i64 %6

56
llvm/test/CodeGen/VE/Scalar/setcc.ll
View File

@ -8,10 +8,10 @@
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i1(i1 zeroext %0, i1 zeroext %1) {
; CHECK-LABEL: setcc_i1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: xor %s0, 1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %0, %1
%4 = xor i1 %3, true
ret i1 %4
@ -20,12 +20,12 @@ define zeroext i1 @setcc_i1(i1 zeroext %0, i1 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i8(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: setcc_i8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i8 %0, %1
ret i1 %3
}
@ -33,12 +33,12 @@ define zeroext i1 @setcc_i8(i8 signext %0, i8 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u8(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: setcc_u8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i8 %0, %1
ret i1 %3
}
@ -46,12 +46,12 @@ define zeroext i1 @setcc_u8(i8 zeroext %0, i8 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i16(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: setcc_i16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i16 %0, %1
ret i1 %3
}
@ -59,12 +59,12 @@ define zeroext i1 @setcc_i16(i16 signext %0, i16 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u16(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: setcc_u16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i16 %0, %1
ret i1 %3
}
@ -72,12 +72,12 @@ define zeroext i1 @setcc_u16(i16 zeroext %0, i16 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i32(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: setcc_i32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1
ret i1 %3
}
@ -85,12 +85,12 @@ define zeroext i1 @setcc_i32(i32 signext %0, i32 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u32(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: setcc_u32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1
ret i1 %3
}
@ -98,12 +98,12 @@ define zeroext i1 @setcc_u32(i32 zeroext %0, i32 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i64(i64 %0, i64 %1) {
; CHECK-LABEL: setcc_i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1
ret i1 %3
}
@ -111,12 +111,12 @@ define zeroext i1 @setcc_i64(i64 %0, i64 %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u64(i64 %0, i64 %1) {
; CHECK-LABEL: setcc_u64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1
ret i1 %3
}
@ -124,7 +124,7 @@ define zeroext i1 @setcc_u64(i64 %0, i64 %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_i128(i128 %0, i128 %1) {
; CHECK-LABEL: setcc_i128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
@ -132,7 +132,7 @@ define zeroext i1 @setcc_i128(i128 %0, i128 %1) {
; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i128 %0, %1
ret i1 %3
}
@ -140,7 +140,7 @@ define zeroext i1 @setcc_i128(i128 %0, i128 %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_u128(i128 %0, i128 %1) {
; CHECK-LABEL: setcc_u128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
@ -148,7 +148,7 @@ define zeroext i1 @setcc_u128(i128 %0, i128 %1) {
; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i128 %0, %1
ret i1 %3
}
@ -156,12 +156,12 @@ define zeroext i1 @setcc_u128(i128 %0, i128 %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_float(float %0, float %1) {
; CHECK-LABEL: setcc_float:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq float %0, %1
ret i1 %3
}
@ -169,12 +169,12 @@ define zeroext i1 @setcc_float(float %0, float %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_double(double %0, double %1) {
; CHECK-LABEL: setcc_double:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq double %0, %1
ret i1 %3
}
@ -182,12 +182,12 @@ define zeroext i1 @setcc_double(double %0, double %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i1 @setcc_quad(fp128 %0, fp128 %1) {
; CHECK-LABEL: setcc_quad:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s0, %s2
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq fp128 %0, %1
ret i1 %3
}

64
llvm/test/CodeGen/VE/Scalar/setccf32.ll
View File

@ -2,186 +2,186 @@
define zeroext i1 @setccaf(float, float) {
; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp false float %0, %1
ret i1 %3
}
define zeroext i1 @setccat(float, float) {
; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp true float %0, %1
ret i1 %3
}
define zeroext i1 @setccoeq(float, float) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oeq float %0, %1
ret i1 %3
}
define zeroext i1 @setccone(float, float) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp one float %0, %1
ret i1 %3
}
define zeroext i1 @setccogt(float, float) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt float %0, %1
ret i1 %3
}
define zeroext i1 @setccoge(float, float) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge float %0, %1
ret i1 %3
}
define zeroext i1 @setccolt(float, float) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt float %0, %1
ret i1 %3
}
define zeroext i1 @setccole(float, float) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole float %0, %1
ret i1 %3
}
define zeroext i1 @setccord(float, float) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ord float %0, %1
ret i1 %3
}
define zeroext i1 @setccuno(float, float) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uno float %0, %1
ret i1 %3
}
define zeroext i1 @setccueq(float, float) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ueq float %0, %1
ret i1 %3
}
define zeroext i1 @setccune(float, float) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp une float %0, %1
ret i1 %3
}
define zeroext i1 @setccugt(float, float) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt float %0, %1
ret i1 %3
}
define zeroext i1 @setccuge(float, float) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge float %0, %1
ret i1 %3
}
define zeroext i1 @setccult(float, float) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult float %0, %1
ret i1 %3
}
define zeroext i1 @setccule(float, float) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule float %0, %1
ret i1 %3
}

64
llvm/test/CodeGen/VE/Scalar/setccf32i.ll
View File

@ -2,198 +2,198 @@
define zeroext i1 @setccaf(float, float) {
; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp false float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccat(float, float) {
; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp true float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccoeq(float, float) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oeq float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccone(float, float) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp one float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccogt(float, float) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccoge(float, float) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccolt(float, float) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccole(float, float) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccord(float, float) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s0
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ord float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccuno(float, float) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.s %s0, %s0, %s0
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uno float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccueq(float, float) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ueq float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccune(float, float) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp une float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccugt(float, float) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccuge(float, float) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccult(float, float) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccule(float, float) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule float %0, 0.0
ret i1 %3
}

64
llvm/test/CodeGen/VE/Scalar/setccf64.ll
View File

@ -2,186 +2,186 @@
define zeroext i1 @setccaf(double, double) {
; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp false double %0, %1
ret i1 %3
}
define zeroext i1 @setccat(double, double) {
; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp true double %0, %1
ret i1 %3
}
define zeroext i1 @setccoeq(double, double) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oeq double %0, %1
ret i1 %3
}
define zeroext i1 @setccone(double, double) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp one double %0, %1
ret i1 %3
}
define zeroext i1 @setccogt(double, double) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt double %0, %1
ret i1 %3
}
define zeroext i1 @setccoge(double, double) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge double %0, %1
ret i1 %3
}
define zeroext i1 @setccolt(double, double) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt double %0, %1
ret i1 %3
}
define zeroext i1 @setccole(double, double) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole double %0, %1
ret i1 %3
}
define zeroext i1 @setccord(double, double) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.num %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ord double %0, %1
ret i1 %3
}
define zeroext i1 @setccuno(double, double) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.nan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uno double %0, %1
ret i1 %3
}
define zeroext i1 @setccueq(double, double) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eqnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ueq double %0, %1
ret i1 %3
}
define zeroext i1 @setccune(double, double) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.nenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp une double %0, %1
ret i1 %3
}
define zeroext i1 @setccugt(double, double) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.gtnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt double %0, %1
ret i1 %3
}
define zeroext i1 @setccuge(double, double) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.genan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge double %0, %1
ret i1 %3
}
define zeroext i1 @setccult(double, double) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ltnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult double %0, %1
ret i1 %3
}
define zeroext i1 @setccule(double, double) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.lenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule double %0, %1
ret i1 %3
}

64
llvm/test/CodeGen/VE/Scalar/setccf64i.ll
View File

@ -2,198 +2,198 @@
define zeroext i1 @setccaf(double, double) {
; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp false double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccat(double, double) {
; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp true double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccoeq(double, double) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oeq double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccone(double, double) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp one double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccogt(double, double) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ogt double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccoge(double, double) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp oge double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccolt(double, double) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp olt double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccole(double, double) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ole double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccord(double, double) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s0
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.num %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ord double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccuno(double, double) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.d %s0, %s0, %s0
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.nan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uno double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccueq(double, double) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.eqnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ueq double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccune(double, double) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.nenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp une double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccugt(double, double) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.gtnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ugt double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccuge(double, double) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.genan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp uge double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccult(double, double) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.ltnan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ult double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccule(double, double) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.d.lenan %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp ule double %0, 0.0
ret i1 %3
}

40
llvm/test/CodeGen/VE/Scalar/setcci32.ll
View File

@ -2,120 +2,120 @@
define zeroext i1 @setcceq(i32, i32) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccne(i32, i32) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ne i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccugt(i32, i32) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccuge(i32, i32) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccult(i32, i32) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccule(i32, i32) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccsgt(i32, i32) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccsge(i32, i32) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccslt(i32, i32) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccsle(i32, i32) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i32 %0, %1
ret i1 %3
}

40
llvm/test/CodeGen/VE/Scalar/setcci32i.ll
View File

@ -2,130 +2,130 @@
define zeroext i1 @setcceq(i32, i32) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccne(i32, i32) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ne i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccugt(i32, i32) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccuge(i32, i32) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccult(i32, i32) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccule(i32, i32) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccsgt(i32, i32) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccsge(i32, i32) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccslt(i32, i32) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccsle(i32, i32) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i32 %0, 12
ret i1 %3
}

40
llvm/test/CodeGen/VE/Scalar/setcci64.ll
View File

@ -2,120 +2,120 @@
define zeroext i1 @setcceq(i64, i64) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccne(i64, i64) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ne i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccugt(i64, i64) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccuge(i64, i64) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccult(i64, i64) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccule(i64, i64) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccsgt(i64, i64) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccsge(i64, i64) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.ge %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccslt(i64, i64) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccsle(i64, i64) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.le %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i64 %0, %1
ret i1 %3
}

40
llvm/test/CodeGen/VE/Scalar/setcci64i.ll
View File

@ -2,130 +2,130 @@
define zeroext i1 @setcceq(i64, i64) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccne(i64, i64) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ne i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccugt(i64, i64) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ugt i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccuge(i64, i64) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccult(i64, i64) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ult i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccule(i64, i64) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccsgt(i64, i64) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sgt i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccsge(i64, i64) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sge i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccslt(i64, i64) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp slt i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccsle(i64, i64) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp sle i64 %0, 12
ret i1 %3
}

104
llvm/test/CodeGen/VE/Scalar/shl.ll
View File

@ -42,12 +42,12 @@
; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: shl_i8_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (56)0
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i8 %0 to i32
%4 = zext i8 %1 to i32
%5 = shl i32 %3, %4
@ -58,10 +58,10 @@ define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: shl_u8_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i8 %0 to i32
%4 = zext i8 %1 to i32
%5 = shl i32 %3, %4
@ -72,12 +72,12 @@ define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: shl_i16_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (48)0
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i16 %0 to i32
%4 = zext i16 %1 to i32
%5 = shl i32 %3, %4
@ -88,10 +88,10 @@ define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: shl_u16_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i16 %0 to i32
%4 = zext i16 %1 to i32
%5 = shl i32 %3, %4
@ -102,10 +102,10 @@ define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: shl_i32_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i32 %0, %1
ret i32 %3
}
@ -113,10 +113,10 @@ define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: shl_u32_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i32 %0, %1
ret i32 %3
}
@ -124,9 +124,9 @@ define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_i64_var(i64 %0, i64 %1) {
; CHECK-LABEL: shl_i64_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i64 %0, %1
ret i64 %3
}
@ -134,9 +134,9 @@ define i64 @shl_i64_var(i64 %0, i64 %1) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_u64_var(i64 %0, i64 %1) {
; CHECK-LABEL: shl_u64_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = shl i64 %0, %1
ret i64 %3
}
@ -172,12 +172,12 @@ define i128 @shl_u128_var(i128 %0, i128 %1) {
; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_const_i8(i8 signext %0) {
; CHECK-LABEL: shl_const_i8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i32
%3 = shl i32 -4, %2
%4 = trunc i32 %3 to i8
@ -187,11 +187,11 @@ define signext i8 @shl_const_i8(i8 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_const_u8(i8 zeroext %0) {
; CHECK-LABEL: shl_const_u8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: lea %s1, 252
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i32
%3 = shl i32 -4, %2
%4 = trunc i32 %3 to i8
@ -201,12 +201,12 @@ define zeroext i8 @shl_const_u8(i8 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_const_i16(i16 signext %0) {
; CHECK-LABEL: shl_const_i16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i32
%3 = shl i32 -4, %2
%4 = trunc i32 %3 to i16
@ -216,11 +216,11 @@ define signext i16 @shl_const_i16(i16 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_const_u16(i16 zeroext %0) {
; CHECK-LABEL: shl_const_u16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: lea %s1, 65532
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i32
%3 = shl i32 -4, %2
%4 = trunc i32 %3 to i16
@ -230,10 +230,10 @@ define zeroext i16 @shl_const_u16(i16 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_const_i32(i32 signext %0) {
; CHECK-LABEL: shl_const_i32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 -4, %0
ret i32 %2
}
@ -241,10 +241,10 @@ define signext i32 @shl_const_i32(i32 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_const_u32(i32 zeroext %0) {
; CHECK-LABEL: shl_const_u32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 -4, %0
ret i32 %2
}
@ -252,9 +252,9 @@ define zeroext i32 @shl_const_u32(i32 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_const_i64(i64 %0) {
; CHECK-LABEL: shl_const_i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, (62)1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 -4, %0
ret i64 %2
}
@ -262,9 +262,9 @@ define i64 @shl_const_i64(i64 %0) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_const_u64(i64 %0) {
; CHECK-LABEL: shl_const_u64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, (62)1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 -4, %0
ret i64 %2
}
@ -304,11 +304,11 @@ define i128 @shl_const_u128(i128 %0) {
; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_i8_const(i8 signext %0) {
; CHECK-LABEL: shl_i8_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 3
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i8 %0, 3
ret i8 %2
}
@ -316,11 +316,11 @@ define signext i8 @shl_i8_const(i8 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_u8_const(i8 zeroext %0) {
; CHECK-LABEL: shl_u8_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 3
; CHECK-NEXT: lea %s1, 248
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i8 %0, 3
ret i8 %2
}
@ -328,11 +328,11 @@ define zeroext i8 @shl_u8_const(i8 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_i16_const(i16 signext %0) {
; CHECK-LABEL: shl_i16_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 7
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i16 %0, 7
ret i16 %2
}
@ -340,11 +340,11 @@ define signext i16 @shl_i16_const(i16 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_u16_const(i16 zeroext %0) {
; CHECK-LABEL: shl_u16_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 7
; CHECK-NEXT: lea %s1, 65408
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i16 %0, 7
ret i16 %2
}
@ -352,10 +352,10 @@ define zeroext i16 @shl_u16_const(i16 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_i32_const(i32 signext %0) {
; CHECK-LABEL: shl_i32_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 15
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 %0, 15
ret i32 %2
}
@ -363,10 +363,10 @@ define signext i32 @shl_i32_const(i32 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_u32_const(i32 zeroext %0) {
; CHECK-LABEL: shl_u32_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sla.w.sx %s0, %s0, 15
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i32 %0, 15
ret i32 %2
}
@ -374,9 +374,9 @@ define zeroext i32 @shl_u32_const(i32 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_i64_const(i64 %0) {
; CHECK-LABEL: shl_i64_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 %0, 63
ret i64 %2
}
@ -384,9 +384,9 @@ define i64 @shl_i64_const(i64 %0) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_u64_const(i64 %0) {
; CHECK-LABEL: shl_u64_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i64 %0, 63
ret i64 %2
}
@ -394,10 +394,10 @@ define i64 @shl_u64_const(i64 %0) {
; Function Attrs: norecurse nounwind readnone
define i128 @shl_i128_const(i128 %0) {
; CHECK-LABEL: shl_i128_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s0, 63
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i128 %0, 127
ret i128 %2
}
@ -405,10 +405,10 @@ define i128 @shl_i128_const(i128 %0) {
; Function Attrs: norecurse nounwind readnone
define i128 @shl_u128_const(i128 %0) {
; CHECK-LABEL: shl_u128_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sll %s1, %s0, 63
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = shl i128 %0, 127
ret i128 %2
}

104
llvm/test/CodeGen/VE/Scalar/shr.ll
View File

@ -76,11 +76,11 @@
; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: shl_i8_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (56)0
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i8 %0 to i32
%4 = zext i8 %1 to i32
%5 = ashr i32 %3, %4
@ -91,11 +91,11 @@ define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: shl_u8_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i8 %0 to i32
%4 = zext i8 %1 to i32
%5 = lshr i32 %3, %4
@ -106,11 +106,11 @@ define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: shl_i16_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (48)0
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sext i16 %0 to i32
%4 = zext i16 %1 to i32
%5 = ashr i32 %3, %4
@ -121,11 +121,11 @@ define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: shl_u16_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = zext i16 %0 to i32
%4 = zext i16 %1 to i32
%5 = lshr i32 %3, %4
@ -136,10 +136,10 @@ define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: shl_i32_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = ashr i32 %0, %1
ret i32 %3
}
@ -147,11 +147,11 @@ define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: shl_u32_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = lshr i32 %0, %1
ret i32 %3
}
@ -159,9 +159,9 @@ define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_i64_var(i64 %0, i64 %1) {
; CHECK-LABEL: shl_i64_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = ashr i64 %0, %1
ret i64 %3
}
@ -169,9 +169,9 @@ define i64 @shl_i64_var(i64 %0, i64 %1) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_u64_var(i64 %0, i64 %1) {
; CHECK-LABEL: shl_u64_var:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = lshr i64 %0, %1
ret i64 %3
}
@ -207,11 +207,11 @@ define i128 @shl_u128_var(i128 %0, i128 %1) {
; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_const_i8(i8 signext %0) {
; CHECK-LABEL: shl_const_i8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i32
%3 = ashr i32 -4, %2
%4 = trunc i32 %3 to i8
@ -221,10 +221,10 @@ define signext i8 @shl_const_i8(i8 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_const_u8(i8 zeroext %0) {
; CHECK-LABEL: shl_const_u8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i8 %0 to i32
%3 = ashr i32 -4, %2
%4 = trunc i32 %3 to i8
@ -234,11 +234,11 @@ define zeroext i8 @shl_const_u8(i8 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_const_i16(i16 signext %0) {
; CHECK-LABEL: shl_const_i16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i32
%3 = ashr i32 -4, %2
%4 = trunc i32 %3 to i16
@ -248,10 +248,10 @@ define signext i16 @shl_const_i16(i16 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_const_u16(i16 zeroext %0) {
; CHECK-LABEL: shl_const_u16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = zext i16 %0 to i32
%3 = ashr i32 -4, %2
%4 = trunc i32 %3 to i16
@ -261,10 +261,10 @@ define zeroext i16 @shl_const_u16(i16 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_const_i32(i32 signext %0) {
; CHECK-LABEL: shl_const_i32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i32 -4, %0
ret i32 %2
}
@ -272,10 +272,10 @@ define signext i32 @shl_const_i32(i32 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_const_u32(i32 zeroext %0) {
; CHECK-LABEL: shl_const_u32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, (62)1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i32 -4, %0
ret i32 %2
}
@ -283,9 +283,9 @@ define zeroext i32 @shl_const_u32(i32 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_const_i64(i64 %0) {
; CHECK-LABEL: shl_const_i64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, (62)1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i64 -4, %0
ret i64 %2
}
@ -293,9 +293,9 @@ define i64 @shl_const_i64(i64 %0) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_const_u64(i64 %0) {
; CHECK-LABEL: shl_const_u64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, (62)1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i64 -4, %0
ret i64 %2
}
@ -335,10 +335,10 @@ define i128 @shl_const_u128(i128 %0) {
; Function Attrs: norecurse nounwind readnone
define signext i8 @shl_i8_const(i8 signext %0) {
; CHECK-LABEL: shl_i8_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 3
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i8 %0, 3
ret i8 %2
}
@ -346,11 +346,11 @@ define signext i8 @shl_i8_const(i8 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i8 @shl_u8_const(i8 zeroext %0) {
; CHECK-LABEL: shl_u8_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 3
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i8 %0, 3
ret i8 %2
}
@ -358,10 +358,10 @@ define zeroext i8 @shl_u8_const(i8 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define signext i16 @shl_i16_const(i16 signext %0) {
; CHECK-LABEL: shl_i16_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 7
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i16 %0, 7
ret i16 %2
}
@ -369,11 +369,11 @@ define signext i16 @shl_i16_const(i16 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i16 @shl_u16_const(i16 zeroext %0) {
; CHECK-LABEL: shl_u16_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 7
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i16 %0, 7
ret i16 %2
}
@ -381,10 +381,10 @@ define zeroext i16 @shl_u16_const(i16 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define signext i32 @shl_i32_const(i32 signext %0) {
; CHECK-LABEL: shl_i32_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.w.sx %s0, %s0, 15
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i32 %0, 15
ret i32 %2
}
@ -392,11 +392,11 @@ define signext i32 @shl_i32_const(i32 signext %0) {
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @shl_u32_const(i32 zeroext %0) {
; CHECK-LABEL: shl_u32_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 15
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i32 %0, 15
ret i32 %2
}
@ -404,9 +404,9 @@ define zeroext i32 @shl_u32_const(i32 zeroext %0) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_i64_const(i64 %0) {
; CHECK-LABEL: shl_i64_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i64 %0, 63
ret i64 %2
}
@ -414,9 +414,9 @@ define i64 @shl_i64_const(i64 %0) {
; Function Attrs: norecurse nounwind readnone
define i64 @shl_u64_const(i64 %0) {
; CHECK-LABEL: shl_u64_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: srl %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i64 %0, 63
ret i64 %2
}
@ -424,10 +424,10 @@ define i64 @shl_u64_const(i64 %0) {
; Function Attrs: norecurse nounwind readnone
define i128 @shl_i128_const(i128 %0) {
; CHECK-LABEL: shl_i128_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s0, %s1, 63
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = ashr i128 %0, 127
ret i128 %2
}
@ -435,10 +435,10 @@ define i128 @shl_i128_const(i128 %0) {
; Function Attrs: norecurse nounwind readnone
define i128 @shl_u128_const(i128 %0) {
; CHECK-LABEL: shl_u128_const:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: srl %s0, %s1, 63
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = lshr i128 %0, 127
ret i128 %2
}

95
llvm/test/CodeGen/VE/Scalar/simple_prologue_epilogue.ll
View File

@ -1,95 +0,0 @@
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define void @func() {
; CHECK-LABEL: func:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: st %s15, 24(, %s11)
; CHECK-NEXT: st %s16, 32(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s13, -176
; CHECK-NEXT: and %s13, %s13, (32)0
; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s16, 32(, %s11)
; CHECK-NEXT: ld %s15, 24(, %s11)
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
ret void
}
define i64 @func1(i64) {
; CHECK-LABEL: func1:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: st %s15, 24(, %s11)
; CHECK-NEXT: st %s16, 32(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s13, -176
; CHECK-NEXT: and %s13, %s13, (32)0
; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s16, 32(, %s11)
; CHECK-NEXT: ld %s15, 24(, %s11)
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
ret i64 %0
}
define i64 @func2(i64, i64, i64, i64, i64) {
; CHECK-LABEL: func2:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s9, (, %s11)
; CHECK-NEXT: st %s10, 8(, %s11)
; CHECK-NEXT: st %s15, 24(, %s11)
; CHECK-NEXT: st %s16, 32(, %s11)
; CHECK-NEXT: or %s9, 0, %s11
; CHECK-NEXT: lea %s13, -176
; CHECK-NEXT: and %s13, %s13, (32)0
; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11)
; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: ld %s61, 24(, %s14)
; CHECK-NEXT: or %s62, 0, %s0
; CHECK-NEXT: lea %s63, 315
; CHECK-NEXT: shm.l %s63, (%s61)
; CHECK-NEXT: shm.l %s8, 8(%s61)
; CHECK-NEXT: shm.l %s11, 16(%s61)
; CHECK-NEXT: monc
; CHECK-NEXT: or %s0, 0, %s62
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: ld %s16, 32(, %s11)
; CHECK-NEXT: ld %s15, 24(, %s11)
; CHECK-NEXT: ld %s10, 8(, %s11)
; CHECK-NEXT: ld %s9, (, %s11)
; CHECK-NEXT: b.l.t (, %s10)
ret i64 %4
}

24
llvm/test/CodeGen/VE/Scalar/store-align1.ll
View File

@ -76,12 +76,12 @@ define void @storei8stk(i8 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storef64com(double %0) {
; CHECK-LABEL: storef64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf64@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store double %0, double* @vf64, align 1
ret void
}
@ -89,12 +89,12 @@ define void @storef64com(double %0) {
; Function Attrs: norecurse nounwind readonly
define void @storef32com(float %0) {
; CHECK-LABEL: storef32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf32@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
; CHECK-NEXT: stu %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store float %0, float* @vf32, align 1
ret void
}
@ -102,12 +102,12 @@ define void @storef32com(float %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei64com(i64 %0) {
; CHECK-LABEL: storei64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi64@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i64 %0, i64* @vi64, align 1
ret void
}
@ -115,12 +115,12 @@ define void @storei64com(i64 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei32com(i32 %0) {
; CHECK-LABEL: storei32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi32@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i32 %0, i32* @vi32, align 1
ret void
}
@ -128,12 +128,12 @@ define void @storei32com(i32 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei16com(i16 %0) {
; CHECK-LABEL: storei16com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi16@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i16 %0, i16* @vi16, align 1
ret void
}
@ -141,12 +141,12 @@ define void @storei16com(i16 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei8com(i8 %0) {
; CHECK-LABEL: storei8com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi8@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i8 %0, i8* @vi8, align 1
ret void
}

24
llvm/test/CodeGen/VE/Scalar/store-align2.ll
View File

@ -76,12 +76,12 @@ define void @storei8stk(i8 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storef64com(double %0) {
; CHECK-LABEL: storef64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf64@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store double %0, double* @vf64, align 2
ret void
}
@ -89,12 +89,12 @@ define void @storef64com(double %0) {
; Function Attrs: norecurse nounwind readonly
define void @storef32com(float %0) {
; CHECK-LABEL: storef32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf32@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
; CHECK-NEXT: stu %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store float %0, float* @vf32, align 2
ret void
}
@ -102,12 +102,12 @@ define void @storef32com(float %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei64com(i64 %0) {
; CHECK-LABEL: storei64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi64@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i64 %0, i64* @vi64, align 2
ret void
}
@ -115,12 +115,12 @@ define void @storei64com(i64 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei32com(i32 %0) {
; CHECK-LABEL: storei32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi32@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i32 %0, i32* @vi32, align 2
ret void
}
@ -128,12 +128,12 @@ define void @storei32com(i32 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei16com(i16 %0) {
; CHECK-LABEL: storei16com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi16@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i16 %0, i16* @vi16, align 2
ret void
}
@ -141,12 +141,12 @@ define void @storei16com(i16 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei8com(i8 %0) {
; CHECK-LABEL: storei8com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi8@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i8 %0, i8* @vi8, align 2
ret void
}

24
llvm/test/CodeGen/VE/Scalar/store-align4.ll
View File

@ -76,12 +76,12 @@ define void @storei8stk(i8 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storef64com(double %0) {
; CHECK-LABEL: storef64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf64@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store double %0, double* @vf64, align 4
ret void
}
@ -89,12 +89,12 @@ define void @storef64com(double %0) {
; Function Attrs: norecurse nounwind readonly
define void @storef32com(float %0) {
; CHECK-LABEL: storef32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf32@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
; CHECK-NEXT: stu %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store float %0, float* @vf32, align 4
ret void
}
@ -102,12 +102,12 @@ define void @storef32com(float %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei64com(i64 %0) {
; CHECK-LABEL: storei64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi64@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i64 %0, i64* @vi64, align 4
ret void
}
@ -115,12 +115,12 @@ define void @storei64com(i64 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei32com(i32 %0) {
; CHECK-LABEL: storei32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi32@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i32 %0, i32* @vi32, align 4
ret void
}
@ -128,12 +128,12 @@ define void @storei32com(i32 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei16com(i16 %0) {
; CHECK-LABEL: storei16com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi16@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i16 %0, i16* @vi16, align 4
ret void
}
@ -141,12 +141,12 @@ define void @storei16com(i16 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei8com(i8 %0) {
; CHECK-LABEL: storei8com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi8@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i8 %0, i8* @vi8, align 4
ret void
}

24
llvm/test/CodeGen/VE/Scalar/store-align8.ll
View File

@ -76,12 +76,12 @@ define void @storei8stk(i8 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storef64com(double %0) {
; CHECK-LABEL: storef64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf64@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store double %0, double* @vf64, align 8
ret void
}
@ -89,12 +89,12 @@ define void @storef64com(double %0) {
; Function Attrs: norecurse nounwind readonly
define void @storef32com(float %0) {
; CHECK-LABEL: storef32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf32@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
; CHECK-NEXT: stu %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store float %0, float* @vf32, align 8
ret void
}
@ -102,12 +102,12 @@ define void @storef32com(float %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei64com(i64 %0) {
; CHECK-LABEL: storei64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi64@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i64 %0, i64* @vi64, align 8
ret void
}
@ -115,12 +115,12 @@ define void @storei64com(i64 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei32com(i32 %0) {
; CHECK-LABEL: storei32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi32@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i32 %0, i32* @vi32, align 8
ret void
}
@ -128,12 +128,12 @@ define void @storei32com(i32 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei16com(i16 %0) {
; CHECK-LABEL: storei16com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi16@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i16 %0, i16* @vi16, align 8
ret void
}
@ -141,12 +141,12 @@ define void @storei16com(i16 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei8com(i8 %0) {
; CHECK-LABEL: storei8com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi8@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i8 %0, i8* @vi8, align 8
ret void
}

44
llvm/test/CodeGen/VE/Scalar/store.ll
View File

@ -3,10 +3,10 @@
; Function Attrs: norecurse nounwind readonly
define void @storef128(fp128* nocapture %0, fp128 %1) {
; CHECK-LABEL: storef128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s2, 8(, %s0)
; CHECK-NEXT: st %s3, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store fp128 %1, fp128* %0, align 16
ret void
}
@ -14,9 +14,9 @@ define void @storef128(fp128* nocapture %0, fp128 %1) {
; Function Attrs: norecurse nounwind readonly
define void @storef64(double* nocapture %0, double %1) {
; CHECK-LABEL: storef64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store double %1, double* %0, align 16
ret void
}
@ -24,9 +24,9 @@ define void @storef64(double* nocapture %0, double %1) {
; Function Attrs: norecurse nounwind readonly
define void @storef32(float* nocapture %0, float %1) {
; CHECK-LABEL: storef32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: stu %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store float %1, float* %0, align 16
ret void
}
@ -34,10 +34,10 @@ define void @storef32(float* nocapture %0, float %1) {
; Function Attrs: norecurse nounwind readonly
define void @storei128(i128* nocapture %0, i128 %1) {
; CHECK-LABEL: storei128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s2, 8(, %s0)
; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i128 %1, i128* %0, align 16
ret void
}
@ -45,9 +45,9 @@ define void @storei128(i128* nocapture %0, i128 %1) {
; Function Attrs: norecurse nounwind readonly
define void @storei64(i64* nocapture %0, i64 %1) {
; CHECK-LABEL: storei64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i64 %1, i64* %0, align 16
ret void
}
@ -55,9 +55,9 @@ define void @storei64(i64* nocapture %0, i64 %1) {
; Function Attrs: norecurse nounwind readonly
define void @storei32(i32* nocapture %0, i32 %1) {
; CHECK-LABEL: storei32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i32 %1, i32* %0, align 16
ret void
}
@ -65,9 +65,9 @@ define void @storei32(i32* nocapture %0, i32 %1) {
; Function Attrs: norecurse nounwind readonly
define void @storei32tr(i32* nocapture %0, i64 %1) {
; CHECK-LABEL: storei32tr:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: stl %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = trunc i64 %1 to i32
store i32 %3, i32* %0, align 16
ret void
@ -76,9 +76,9 @@ define void @storei32tr(i32* nocapture %0, i64 %1) {
; Function Attrs: norecurse nounwind readonly
define void @storei16(i16* nocapture %0, i16 %1) {
; CHECK-LABEL: storei16:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i16 %1, i16* %0, align 16
ret void
}
@ -86,9 +86,9 @@ define void @storei16(i16* nocapture %0, i16 %1) {
; Function Attrs: norecurse nounwind readonly
define void @storei16tr(i16* nocapture %0, i64 %1) {
; CHECK-LABEL: storei16tr:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st2b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = trunc i64 %1 to i16
store i16 %3, i16* %0, align 16
ret void
@ -97,9 +97,9 @@ define void @storei16tr(i16* nocapture %0, i64 %1) {
; Function Attrs: norecurse nounwind readonly
define void @storei8(i8* nocapture %0, i8 %1) {
; CHECK-LABEL: storei8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i8 %1, i8* %0, align 16
ret void
}
@ -107,9 +107,9 @@ define void @storei8(i8* nocapture %0, i8 %1) {
; Function Attrs: norecurse nounwind readonly
define void @storei8tr(i8* nocapture %0, i64 %1) {
; CHECK-LABEL: storei8tr:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s1, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = trunc i64 %1 to i8
store i8 %3, i8* %0, align 16
ret void

32
llvm/test/CodeGen/VE/Scalar/store_gv.ll
View File

@ -12,13 +12,13 @@
; Function Attrs: norecurse nounwind readonly
define void @storef128com(fp128 %0) {
; CHECK-LABEL: storef128com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, vf128@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, vf128@hi(, %s2)
; CHECK-NEXT: st %s0, 8(, %s2)
; CHECK-NEXT: st %s1, (, %s2)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store fp128 %0, fp128* @vf128, align 16
ret void
}
@ -26,12 +26,12 @@ define void @storef128com(fp128 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storef64com(double %0) {
; CHECK-LABEL: storef64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf64@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store double %0, double* @vf64, align 8
ret void
}
@ -39,12 +39,12 @@ define void @storef64com(double %0) {
; Function Attrs: norecurse nounwind readonly
define void @storef32com(float %0) {
; CHECK-LABEL: storef32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vf32@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vf32@hi(, %s1)
; CHECK-NEXT: stu %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store float %0, float* @vf32, align 4
ret void
}
@ -52,13 +52,13 @@ define void @storef32com(float %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei128com(i128 %0) {
; CHECK-LABEL: storei128com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, vi128@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, vi128@hi(, %s2)
; CHECK-NEXT: st %s1, 8(, %s2)
; CHECK-NEXT: st %s0, (, %s2)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i128 %0, i128* @vi128, align 16
ret void
}
@ -66,12 +66,12 @@ define void @storei128com(i128 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei64com(i64 %0) {
; CHECK-LABEL: storei64com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi64@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi64@hi(, %s1)
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i64 %0, i64* @vi64, align 8
ret void
}
@ -79,12 +79,12 @@ define void @storei64com(i64 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei32com(i32 %0) {
; CHECK-LABEL: storei32com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi32@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi32@hi(, %s1)
; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i32 %0, i32* @vi32, align 4
ret void
}
@ -92,12 +92,12 @@ define void @storei32com(i32 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei16com(i16 %0) {
; CHECK-LABEL: storei16com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi16@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi16@hi(, %s1)
; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i16 %0, i16* @vi16, align 2
ret void
}
@ -105,12 +105,12 @@ define void @storei16com(i16 %0) {
; Function Attrs: norecurse nounwind readonly
define void @storei8com(i8 %0) {
; CHECK-LABEL: storei8com:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, vi8@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, vi8@hi(, %s1)
; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
store i8 %0, i8* @vi8, align 1
ret void
}

88
llvm/test/CodeGen/VE/Scalar/subtraction.ll
View File

@ -2,48 +2,48 @@
define signext i8 @func8s(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i8 %0, %1
ret i8 %3
}
define signext i16 @func16s(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i16 %0, %1
ret i16 %3
}
define signext i32 @func32s(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sub nsw i32 %0, %1
ret i32 %3
}
define i64 @func64s(i64 %0, i64 %1) {
; CHECK-LABEL: func64s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sub nsw i64 %0, %1
ret i64 %3
}
define i128 @func128s(i128 %0, i128 %1) {
; CHECK-LABEL: func128s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: cmpu.l %s3, %s0, %s2
; CHECK-NEXT: or %s4, 0, (0)1
@ -51,53 +51,53 @@ define i128 @func128s(i128 %0, i128 %1) {
; CHECK-NEXT: adds.w.zx %s3, %s4, (0)1
; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: subs.l %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sub nsw i128 %0, %1
ret i128 %3
}
define zeroext i8 @func8z(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i8 %0, %1
ret i8 %3
}
define zeroext i16 @func16z(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i16 %0, %1
ret i16 %3
}
define zeroext i32 @func32z(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i32 %0, %1
ret i32 %3
}
define i64 @func64z(i64 %0, i64 %1) {
; CHECK-LABEL: func64z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: subs.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i64 %0, %1
ret i64 %3
}
define i128 @func128z(i128 %0, i128 %1) {
; CHECK-LABEL: func128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: cmpu.l %s3, %s0, %s2
; CHECK-NEXT: or %s4, 0, (0)1
@ -105,55 +105,55 @@ define i128 @func128z(i128 %0, i128 %1) {
; CHECK-NEXT: adds.w.zx %s3, %s4, (0)1
; CHECK-NEXT: subs.l %s1, %s1, %s3
; CHECK-NEXT: subs.l %s0, %s0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = sub i128 %0, %1
ret i128 %3
}
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%ret = add i8 %a, -5
ret i8 %ret
}
define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%ret = add i16 %a, -5
ret i16 %ret
}
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%ret = add i32 %a, -5
ret i32 %ret
}
define i64 @funci64s(i64 %a) {
; CHECK-LABEL: funci64s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%ret = add nsw i64 %a, -5
ret i64 %ret
}
define i128 @funci128s(i128 %0) {
; CHECK-LABEL: funci128s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, -5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
@ -161,53 +161,53 @@ define i128 @funci128s(i128 %0) {
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: lea %s1, -1(%s0, %s1)
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i128 %0, -5
ret i128 %2
}
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%ret = add i8 %a, -5
ret i8 %ret
}
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%ret = add i16 %a, -5
ret i16 %ret
}
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%ret = add i32 %a, -5
ret i32 %ret
}
define i64 @funci64z(i64 %a) {
; CHECK-LABEL: funci64z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -5(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%ret = add i64 %a, -5
ret i64 %ret
}
define i128 @funci128z(i128 %0) {
; CHECK-LABEL: funci128z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, -5(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
@ -215,23 +215,23 @@ define i128 @funci128z(i128 %0) {
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: lea %s1, -1(%s0, %s1)
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add i128 %0, -5
ret i128 %2
}
define i64 @funci64_2(i64 %a) {
; CHECK-LABEL: funci64_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, -2147483648(, %s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%ret = add nsw i64 %a, -2147483648
ret i64 %ret
}
define i128 @funci128_2(i128 %0) {
; CHECK-LABEL: funci128_2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, -2147483648(, %s0)
; CHECK-NEXT: cmpu.l %s0, %s2, %s0
; CHECK-NEXT: or %s3, 0, (0)1
@ -239,7 +239,7 @@ define i128 @funci128_2(i128 %0) {
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: lea %s1, -1(%s0, %s1)
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = add nsw i128 %0, -2147483648
ret i128 %2
}

8
llvm/test/CodeGen/VE/Scalar/symbol_relocation_tls.ll
View File

@ -104,7 +104,7 @@ define void @set_global(i32 %v) {
; GENDYN-NEXT: R_VE_PLT_HI32 __tls_get_addr
; GENDYN-NEXT: bsic %s10, (, %s12)
; GENDYN-NEXT: stl %s18, (, %s0)
; GENDYN-NEXT: ld %s18, 48(, %s9)
; GENDYN-NEXT: ld %s18, 288(, %s11)
; GENDYN-NEXT: or %s11, 0, %s9
;
; GENDYNPIC: lea %s15, (-24)
@ -126,7 +126,7 @@ define void @set_global(i32 %v) {
; GENDYNPIC-NEXT: R_VE_PLT_HI32 __tls_get_addr
; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: stl %s18, (, %s0)
; GENDYNPIC-NEXT: ld %s18, 48(, %s9)
; GENDYNPIC-NEXT: ld %s18, 288(, %s11)
; GENDYNPIC-NEXT: or %s11, 0, %s9
entry:
store i32 %v, i32* @x, align 4
@ -148,7 +148,7 @@ define void @set_local(i32 %v) {
; GENDYN-NEXT: R_VE_PLT_HI32 __tls_get_addr
; GENDYN-NEXT: bsic %s10, (, %s12)
; GENDYN-NEXT: stl %s18, (, %s0)
; GENDYN-NEXT: ld %s18, 48(, %s9)
; GENDYN-NEXT: ld %s18, 288(, %s11)
; GENDYN-NEXT: or %s11, 0, %s9
;
; GENDYNPIC: lea %s15, (-24)
@ -170,7 +170,7 @@ define void @set_local(i32 %v) {
; GENDYNPIC-NEXT: R_VE_PLT_HI32 __tls_get_addr
; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: stl %s18, (, %s0)
; GENDYNPIC-NEXT: ld %s18, 48(, %s9)
; GENDYNPIC-NEXT: ld %s18, 288(, %s11)
; GENDYNPIC-NEXT: or %s11, 0, %s9
entry:
store i32 %v, i32* @y, align 4

20
llvm/test/CodeGen/VE/Scalar/tls.ll
View File

@ -37,6 +37,7 @@ define nonnull i32* @get_global() {
; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: or %s11, 0, %s9
;
; LOCAL-LABEL: get_global:
; LOCAL: .LBB{{[0-9]+}}_2:
; LOCAL-NEXT: lea %s34, x@tpoff_lo
@ -77,6 +78,7 @@ define nonnull i32* @get_local() {
; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: or %s11, 0, %s9
;
; LOCAL-LABEL: get_local:
; LOCAL: .LBB{{[0-9]+}}_2:
; LOCAL-NEXT: lea %s34, y@tpoff_lo
@ -92,7 +94,7 @@ entry:
define void @set_global(i32 %v) {
; GENDYN-LABEL: set_global:
; GENDYN: .LBB{{[0-9]+}}_2:
; GENDYN-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill
; GENDYN-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; GENDYN-NEXT: or %s18, 0, %s0
; GENDYN-NEXT: lea %s0, x@tls_gd_lo(-24)
; GENDYN-NEXT: and %s0, %s0, (32)0
@ -103,12 +105,12 @@ define void @set_global(i32 %v) {
; GENDYN-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYN-NEXT: bsic %s10, (, %s12)
; GENDYN-NEXT: stl %s18, (, %s0)
; GENDYN-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload
; GENDYN-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; GENDYN-NEXT: or %s11, 0, %s9
;
; GENDYNPIC-LABEL: set_global:
; GENDYNPIC: .LBB{{[0-9]+}}_2:
; GENDYNPIC-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill
; GENDYNPIC-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; GENDYNPIC-NEXT: or %s18, 0, %s0
; GENDYNPIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; GENDYNPIC-NEXT: and %s15, %s15, (32)0
@ -123,8 +125,9 @@ define void @set_global(i32 %v) {
; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: stl %s18, (, %s0)
; GENDYNPIC-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload
; GENDYNPIC-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; GENDYNPIC-NEXT: or %s11, 0, %s9
;
; LOCAL-LABEL: set_global:
; LOCAL: .LBB{{[0-9]+}}_2:
; LOCAL-NEXT: lea %s34, x@tpoff_lo
@ -142,7 +145,7 @@ entry:
define void @set_local(i32 %v) {
; GENDYN-LABEL: set_local:
; GENDYN: .LBB{{[0-9]+}}_2:
; GENDYN-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill
; GENDYN-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; GENDYN-NEXT: or %s18, 0, %s0
; GENDYN-NEXT: lea %s0, y@tls_gd_lo(-24)
; GENDYN-NEXT: and %s0, %s0, (32)0
@ -153,12 +156,12 @@ define void @set_local(i32 %v) {
; GENDYN-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYN-NEXT: bsic %s10, (, %s12)
; GENDYN-NEXT: stl %s18, (, %s0)
; GENDYN-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload
; GENDYN-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; GENDYN-NEXT: or %s11, 0, %s9
;
; GENDYNPIC-LABEL: set_local:
; GENDYNPIC: .LBB{{[0-9]+}}_2:
; GENDYNPIC-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill
; GENDYNPIC-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; GENDYNPIC-NEXT: or %s18, 0, %s0
; GENDYNPIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
; GENDYNPIC-NEXT: and %s15, %s15, (32)0
@ -173,8 +176,9 @@ define void @set_local(i32 %v) {
; GENDYNPIC-NEXT: lea.sl %s12, __tls_get_addr@plt_hi(%s10, %s12)
; GENDYNPIC-NEXT: bsic %s10, (, %s12)
; GENDYNPIC-NEXT: stl %s18, (, %s0)
; GENDYNPIC-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload
; GENDYNPIC-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; GENDYNPIC-NEXT: or %s11, 0, %s9
;
; LOCAL-LABEL: set_local:
; LOCAL: .LBB{{[0-9]+}}_2:
; LOCAL-NEXT: lea %s34, y@tpoff_lo

28
llvm/test/CodeGen/VE/Scalar/truncstore.ll
View File

@ -2,9 +2,9 @@
define void @func0(i1 signext %p, i8* %a) {
; CHECK-LABEL: func0:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st1b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i1 %p to i8
store i8 %p.conv, i8* %a, align 2
ret void
@ -12,9 +12,9 @@ define void @func0(i1 signext %p, i8* %a) {
define void @func1(i8 signext %p, i16* %a) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st2b %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i8 %p to i16
store i16 %p.conv, i16* %a, align 2
ret void
@ -22,9 +22,9 @@ define void @func1(i8 signext %p, i16* %a) {
define void @func2(i8 signext %p, i32* %a) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i8 %p to i32
store i32 %p.conv, i32* %a, align 4
ret void
@ -32,9 +32,9 @@ define void @func2(i8 signext %p, i32* %a) {
define void @func3(i8 signext %p, i64* %a) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i8 %p to i64
store i64 %p.conv, i64* %a, align 8
ret void
@ -42,9 +42,9 @@ define void @func3(i8 signext %p, i64* %a) {
define void @func5(i16 signext %p, i32* %a) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: stl %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i16 %p to i32
store i32 %p.conv, i32* %a, align 4
ret void
@ -52,9 +52,9 @@ define void @func5(i16 signext %p, i32* %a) {
define void @func6(i16 signext %p, i64* %a) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i16 %p to i64
store i64 %p.conv, i64* %a, align 8
ret void
@ -62,10 +62,10 @@ define void @func6(i16 signext %p, i64* %a) {
define void @func8(i32 %p, i64* %a) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%p.conv = sext i32 %p to i64
store i64 %p.conv, i64* %a, align 8
ret void

68
llvm/test/CodeGen/VE/Scalar/xor.ll
View File

@ -2,120 +2,120 @@
define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i8 %a, %b
ret i8 %res
}
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i8 %b, %a
ret i8 %res
}
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i8 %a, 5
ret i8 %res
}
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i8 -5, %a
ret i8 %res
}
define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i16 %a, %b
ret i16 %res
}
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i16 %b, %a
ret i16 %res
}
define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i16 %a, 65535
ret i16 %res
}
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, (52)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i16 4095, %a
ret i16 %res
}
define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i32 %a, %b
ret i32 %res
}
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i32 %a, %b
ret i32 %res
}
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i32 %a, 268435455
ret i32 %res
}
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i32 %a, 268435455
ret i32 %res
}
define i32 @funci32_another(i32 %0) {
; CHECK-LABEL: funci32_another:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, -2147483648
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%2 = xor i32 %0, -2147483648
ret i32 %2
}
@ -123,37 +123,37 @@ define i32 @funci32_another(i32 %0) {
define i64 @func64(i64 %a, i64 %b) {
; CHECK-LABEL: func64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i64 %a, %b
ret i64 %res
}
define i64 @func64i(i64 %a) {
; CHECK-LABEL: func64i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, (24)0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i64 %a, 1099511627775
ret i64 %res
}
define i128 @func128(i128 %a, i128 %b) {
; CHECK-LABEL: func128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s2, %s0
; CHECK-NEXT: xor %s1, %s3, %s1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i128 %b, %a
ret i128 %res
}
define i128 @funci128(i128 %a) {
; CHECK-LABEL: funci128:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%res = xor i128 %a, 5
ret i128 %res
}

16
llvm/test/CodeGen/VE/VELIntrinsics/lsv.ll
View File

@ -8,14 +8,14 @@
; Function Attrs: nounwind
define void @lsv_vvss(i8* %0, i64 %1, i32 signext %2) {
; CHECK-LABEL: lsv_vvss:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s3, 256
; CHECK-NEXT: lvl %s3
; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
; CHECK-NEXT: lsv %v0(%s2), %s1
; CHECK-NEXT: vst %v0, 8, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
%5 = tail call fast <256 x double> @llvm.ve.vl.lsv.vvss(<256 x double> %4, i32 %2, i64 %1)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %5, i64 8, i8* %0, i32 256)
@ -34,13 +34,13 @@ declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind readonly
define i64 @lvsl_vssl_imm(i8* readonly %0, i32 signext %1) {
; CHECK-LABEL: lvsl_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: lvs %s0, %v0(%s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
%4 = tail call i64 @llvm.ve.vl.lvsl.svs(<256 x double> %3, i32 %1)
ret i64 %4
@ -52,13 +52,13 @@ declare i64 @llvm.ve.vl.lvsl.svs(<256 x double>, i32)
; Function Attrs: nounwind readonly
define double @lvsd_vssl_imm(i8* readonly %0, i32 signext %1) {
; CHECK-LABEL: lvsd_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: lvs %s0, %v0(%s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
%4 = tail call fast double @llvm.ve.vl.lvsd.svs(<256 x double> %3, i32 %1)
ret double %4
@ -70,13 +70,13 @@ declare double @llvm.ve.vl.lvsd.svs(<256 x double>, i32)
; Function Attrs: nounwind readonly
define float @lvss_vssl_imm(i8* readonly %0, i32 signext %1) {
; CHECK-LABEL: lvss_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vld %v0, 8, %s0
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: lvs %s0, %v0(%s0)
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
%4 = tail call fast float @llvm.ve.vl.lvss.svs(<256 x double> %3, i32 %1)
ret float %4

8
llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
View File

@ -12,7 +12,7 @@ declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, i8*, i32)
; Function Attrs: nounwind
define void @switching_vl(i32 %evl, i32 %evl2, i8* %P, i8* %Q) {
; CHECK-LABEL: switching_vl:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s4, 256
; CHECK-NEXT: lvl %s4
; CHECK-NEXT: vld %v0, 8, %s2
@ -29,7 +29,7 @@ define void @switching_vl(i32 %evl, i32 %evl2, i8* %P, i8* %Q) {
; CHECK-NEXT: vld %v0, 8, %s2
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vst %v0, 16, %s3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%l0 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 256)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l0, i64 16, i8* %Q, i32 %evl)
%l1 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 16, i8* %P, i32 128)
@ -46,7 +46,7 @@ define void @switching_vl(i32 %evl, i32 %evl2, i8* %P, i8* %Q) {
; Function Attrs: nounwind
define void @stable_vl(i32 %evl, i8* %P, i8* %Q) {
; CHECK-LABEL: stable_vl:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vld %v0, 8, %s1
@ -55,7 +55,7 @@ define void @stable_vl(i32 %evl, i8* %P, i8* %Q) {
; CHECK-NEXT: vst %v0, 16, %s2
; CHECK-NEXT: vld %v0, 8, %s1
; CHECK-NEXT: vst %v0, 16, %s2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
%l0 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %P, i32 %evl)
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %l0, i64 16, i8* %Q, i32 %evl)
%l1 = tail call <256 x double> @llvm.ve.vl.vld.vssl(i64 16, i8* %P, i32 %evl)

16
llvm/test/CodeGen/VE/VELIntrinsics/pfchv.ll
View File

@ -8,11 +8,11 @@
; Function Attrs: nounwind
define void @pfchv_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: pfchv_vssl:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: pfchv %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
tail call void @llvm.ve.vl.pfchv.ssl(i64 %1, i8* %0, i32 256)
ret void
}
@ -23,11 +23,11 @@ declare void @llvm.ve.vl.pfchv.ssl(i64, i8*, i32)
; Function Attrs: nounwind
define void @pfchv_vssl_imm(i8* %0) {
; CHECK-LABEL: pfchv_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pfchv 8, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
tail call void @llvm.ve.vl.pfchv.ssl(i64 8, i8* %0, i32 256)
ret void
}
@ -35,11 +35,11 @@ define void @pfchv_vssl_imm(i8* %0) {
; Function Attrs: nounwind
define void @pfchvnc_vssl(i8* %0, i64 %1) {
; CHECK-LABEL: pfchvnc_vssl:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: pfchv.nc %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
tail call void @llvm.ve.vl.pfchvnc.ssl(i64 %1, i8* %0, i32 256)
ret void
}
@ -50,11 +50,11 @@ declare void @llvm.ve.vl.pfchvnc.ssl(i64, i8*, i32)
; Function Attrs: nounwind
define void @pfchvnc_vssl_imm(i8* %0) {
; CHECK-LABEL: pfchvnc_vssl_imm:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pfchv.nc 8, %s0
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
tail call void @llvm.ve.vl.pfchvnc.ssl(i64 8, i8* %0, i32 256)
ret void
}

256
llvm/test/CodeGen/VE/VELIntrinsics/vld.ll
View File

File diff suppressed because it is too large Load Diff

384
llvm/test/CodeGen/VE/VELIntrinsics/vst.ll
View File

File diff suppressed because it is too large Load Diff

28
llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
View File

@ -47,68 +47,68 @@ define fastcc float @stack_stack_arg_i32f32_r9(i32 %p0, float %p1, i32 %p2, floa
; v0-to-v0 passthrough case without vreg copy.
define fastcc <256 x i32> @vreg_arg_v256i32_r0(<256 x i32> %p0) {
; CHECK-LABEL: vreg_arg_v256i32_r0:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s11, 0, %s9
; CHECK: # %bb.0:
; CHECK-NEXT: b.l.t (, %s10)
ret <256 x i32> %p0
}
define fastcc <256 x i32> @vreg_arg_v256i32_r1(<256 x i32> %p0, <256 x i32> %p1) {
; CHECK-LABEL: vreg_arg_v256i32_r1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret <256 x i32> %p1
}
define fastcc <256 x i32> @vreg_arg_v256i32_r2(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2) {
; CHECK-LABEL: vreg_arg_v256i32_r2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v2
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret <256 x i32> %p2
}
define fastcc <256 x i32> @vreg_arg_v256i32_r3(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3) {
; CHECK-LABEL: vreg_arg_v256i32_r3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v3
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret <256 x i32> %p3
}
define fastcc <256 x i32> @vreg_arg_v256i32_r4(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4) {
; CHECK-LABEL: vreg_arg_v256i32_r4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v4
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret <256 x i32> %p4
}
define fastcc <256 x i32> @vreg_arg_v256i32_r5(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5) {
; CHECK-LABEL: vreg_arg_v256i32_r5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v5
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret <256 x i32> %p5
}
define fastcc <256 x i32> @vreg_arg_v256i32_r6(<256 x i32> %p0, <256 x i32> %p1, <256 x i32> %p2, <256 x i32> %p3, <256 x i32> %p4, <256 x i32> %p5, <256 x i32> %p6) {
; CHECK-LABEL: vreg_arg_v256i32_r6:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v6
; CHECK-NEXT: or %s11, 0, %s9
; CHECK-NEXT: b.l.t (, %s10)
ret <256 x i32> %p6
}