Have HexagonSelectionDAGInfo take a DataLayout rather than a

target machine since that's all it needs.

llvm-svn: 211822
This commit is contained in:
Eric Christopher 2014-06-27 00:18:25 +00:00
parent dbe1cb0d59
commit 4496eb0b09
3 changed files with 4 additions and 6 deletions

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@ -18,8 +18,8 @@ using namespace llvm;
bool llvm::flag_aligned_memcpy; bool llvm::flag_aligned_memcpy;
HexagonSelectionDAGInfo::HexagonSelectionDAGInfo(const HexagonTargetMachine &TM) HexagonSelectionDAGInfo::HexagonSelectionDAGInfo(const DataLayout &DL)
: TargetSelectionDAGInfo(TM.getDataLayout()) {} : TargetSelectionDAGInfo(&DL) {}
HexagonSelectionDAGInfo::~HexagonSelectionDAGInfo() { HexagonSelectionDAGInfo::~HexagonSelectionDAGInfo() {
} }

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@ -18,11 +18,9 @@
namespace llvm { namespace llvm {
class HexagonTargetMachine;
class HexagonSelectionDAGInfo : public TargetSelectionDAGInfo { class HexagonSelectionDAGInfo : public TargetSelectionDAGInfo {
public: public:
explicit HexagonSelectionDAGInfo(const HexagonTargetMachine &TM); explicit HexagonSelectionDAGInfo(const DataLayout &DL);
~HexagonSelectionDAGInfo(); ~HexagonSelectionDAGInfo();
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,

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@ -71,7 +71,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32"), Subtarget(TT, CPU, FS), DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32"), Subtarget(TT, CPU, FS),
InstrInfo(Subtarget), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), TLInfo(*this), TSInfo(DL),
FrameLowering() { FrameLowering() {
initAsmInfo(); initAsmInfo();
} }