forked from OSchip/llvm-project
[X86][Costmodel] Load/store i8 Stride=3 VF=32 interleaving costs
For VF=16, costs are correct. For VF=32, load cost is divergent. The only sched models that for cpu's that support avx2 but not avx512 are: haswell, broadwell, skylake, zen1-3 For load we have: https://godbolt.org/z/qKjevqf4W - for intels `Block RThroughput: <=14.0`; for ryzens, `Block RThroughput: <=4.5` So pick cost of `14`. For store we have: https://godbolt.org/z/xTssTq319 - for intels `Block RThroughput: =13.0`; for ryzens, `Block RThroughput: <=5.5` So pick cost of `13`. I'm directly using the shuffling asm the llc produced, without any manual fixups that may be needed to ensure sequential execution. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D110961
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@ -5090,7 +5090,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
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{3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8
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{3, MVT::v8i8, 6}, // (load 24i8 and) deinterleave into 3 x 8i8
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{3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8
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{3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8
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{3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8
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{3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32
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@ -30,7 +30,7 @@ target triple = "x86_64-unknown-linux-gnu"
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; AVX2: LV: Found an estimated cost of 6 for VF 4 For instruction: %v0 = load i8, i8* %in0, align 1
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; AVX2: LV: Found an estimated cost of 9 for VF 8 For instruction: %v0 = load i8, i8* %in0, align 1
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; AVX2: LV: Found an estimated cost of 13 for VF 16 For instruction: %v0 = load i8, i8* %in0, align 1
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; AVX2: LV: Found an estimated cost of 16 for VF 32 For instruction: %v0 = load i8, i8* %in0, align 1
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; AVX2: LV: Found an estimated cost of 17 for VF 32 For instruction: %v0 = load i8, i8* %in0, align 1
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;
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; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i8, i8* %in0, align 1
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; AVX512: LV: Found an estimated cost of 4 for VF 2 For instruction: %v0 = load i8, i8* %in0, align 1
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