forked from OSchip/llvm-project
Implement the following missing functionality in the PPC backend:
cast fp->bool cast ulong->fp algebraic right shift long by non-constant value These changes tested across most of the test suite. Fixes Regression/casts llvm-svn: 16081
This commit is contained in:
Nate Begeman
parent
023ff63545
commit
4483df8b63
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@ -2324,12 +2324,43 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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BuildMI(*MBB, IP, PPC::SLW, 2, DestReg+1).addReg(SrcReg+1)
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.addReg(ShiftAmountReg);
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} else {
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if (isSigned) {
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// FIXME: Unimplemented
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// Page C-3 of the PowerPC 32bit Programming Environments Manual
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std::cerr << "ERROR: Unimplemented: signed right shift of long\n";
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abort();
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} else {
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if (isSigned) { // shift right algebraic
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MachineBasicBlock *TmpMBB =new MachineBasicBlock(BB->getBasicBlock());
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MachineBasicBlock *PhiMBB =new MachineBasicBlock(BB->getBasicBlock());
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MachineBasicBlock *OldMBB = BB;
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ilist<MachineBasicBlock>::iterator It = BB; ++It;
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F->getBasicBlockList().insert(It, TmpMBB);
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F->getBasicBlockList().insert(It, PhiMBB);
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BB->addSuccessor(TmpMBB);
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BB->addSuccessor(PhiMBB);
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BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
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.addSImm(32);
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BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg2).addReg(SrcReg+1)
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.addReg(ShiftAmountReg);
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BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg3).addReg(SrcReg)
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.addReg(TmpReg1);
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BuildMI(*MBB, IP, PPC::OR, 2, TmpReg4).addReg(TmpReg2)
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.addReg(TmpReg3);
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BuildMI(*MBB, IP, PPC::ADDICo, 2, TmpReg5).addReg(ShiftAmountReg)
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.addSImm(-32);
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BuildMI(*MBB, IP, PPC::SRAW, 2, TmpReg6).addReg(SrcReg)
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.addReg(TmpReg5);
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BuildMI(*MBB, IP, PPC::SRAW, 2, DestReg).addReg(SrcReg)
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.addReg(ShiftAmountReg);
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BuildMI(*MBB, IP, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
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// OrMBB:
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// Select correct least significant half if the shift amount > 32
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BB = TmpMBB;
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unsigned OrReg = makeAnotherReg(Type::IntTy);
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BuildMI(BB, PPC::OR, 2, OrReg).addReg(TmpReg6).addImm(TmpReg6);
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TmpMBB->addSuccessor(PhiMBB);
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BB = PhiMBB;
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BuildMI(BB, PPC::PHI, 4, DestReg+1).addReg(TmpReg4).addMBB(OldMBB)
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.addReg(OrReg).addMBB(TmpMBB);
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} else { // shift right logical
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BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
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.addSImm(32);
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BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg2).addReg(SrcReg+1)
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@ -2654,9 +2685,12 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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}
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case cFP32:
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case cFP64:
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// FSEL perhaps?
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std::cerr << "ERROR: Cast fp-to-bool not implemented!\n";
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abort();
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unsigned TmpReg = makeAnotherReg(Type::IntTy);
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unsigned ConstZero = getReg(ConstantFP::get(Type::DoubleTy, 0.0), BB, IP);
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BuildMI(*MBB, IP, PPC::FCMPU, PPC::CR7).addReg(SrcReg).addReg(ConstZero);
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BuildMI(*MBB, IP, PPC::MFCR, TmpReg);
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BuildMI(*MBB, IP, PPC::RLWINM, DestReg).addReg(TmpReg).addImm(31)
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.addImm(31).addImm(31);
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}
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return;
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}
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@ -2678,13 +2712,70 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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// Emit a library call for long to float conversion
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if (SrcClass == cLong) {
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std::vector<ValueRecord> Args;
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Args.push_back(ValueRecord(SrcReg, SrcTy));
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Function *floatFn = (DestClass == cFP32) ? __floatdisfFn : __floatdidfFn;
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MachineInstr *TheCall =
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BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
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doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
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TM.CalledFunctions.insert(floatFn);
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if (SrcTy->isSigned()) {
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std::vector<ValueRecord> Args;
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Args.push_back(ValueRecord(SrcReg, SrcTy));
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MachineInstr *TheCall =
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BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
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doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
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TM.CalledFunctions.insert(floatFn);
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} else {
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std::vector<ValueRecord> CmpArgs, ClrArgs, SetArgs;
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unsigned ZeroLong = getReg(ConstantUInt::get(SrcTy, 0));
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unsigned CondReg = makeAnotherReg(Type::IntTy);
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// Update machine-CFG edges
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MachineBasicBlock *ClrMBB = new MachineBasicBlock(BB->getBasicBlock());
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MachineBasicBlock *SetMBB = new MachineBasicBlock(BB->getBasicBlock());
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MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
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MachineBasicBlock *OldMBB = BB;
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ilist<MachineBasicBlock>::iterator It = BB; ++It;
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F->getBasicBlockList().insert(It, ClrMBB);
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F->getBasicBlockList().insert(It, SetMBB);
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F->getBasicBlockList().insert(It, PhiMBB);
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BB->addSuccessor(ClrMBB);
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BB->addSuccessor(SetMBB);
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CmpArgs.push_back(ValueRecord(SrcReg, SrcTy));
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CmpArgs.push_back(ValueRecord(ZeroLong, SrcTy));
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MachineInstr *TheCall =
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BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(__cmpdi2Fn, true);
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doCall(ValueRecord(CondReg, Type::IntTy), TheCall, CmpArgs, false);
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TM.CalledFunctions.insert(__cmpdi2Fn);
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BuildMI(*MBB, IP, PPC::CMPWI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
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BuildMI(*MBB, IP, PPC::BLE, 2).addReg(PPC::CR0).addMBB(SetMBB);
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// ClrMBB
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BB = ClrMBB;
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unsigned ClrReg = makeAnotherReg(DestTy);
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ClrArgs.push_back(ValueRecord(SrcReg, SrcTy));
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TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
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doCall(ValueRecord(ClrReg, DestTy), TheCall, ClrArgs, false);
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TM.CalledFunctions.insert(floatFn);
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BuildMI(BB, PPC::B, 1).addMBB(PhiMBB);
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BB->addSuccessor(PhiMBB);
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// SetMBB
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BB = SetMBB;
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unsigned SetReg = makeAnotherReg(DestTy);
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unsigned CallReg = makeAnotherReg(DestTy);
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unsigned ShiftedReg = makeAnotherReg(SrcTy);
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ConstantSInt *Const1 = ConstantSInt::get(Type::IntTy, 1);
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emitShiftOperation(BB, BB->end(), Src, Const1, false, SrcTy, ShiftedReg);
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SetArgs.push_back(ValueRecord(ShiftedReg, SrcTy));
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TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
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doCall(ValueRecord(CallReg, DestTy), TheCall, SetArgs, false);
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TM.CalledFunctions.insert(floatFn);
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unsigned SetOpcode = (DestClass == cFP32) ? PPC::FADDS : PPC::FADD;
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BuildMI(BB, SetOpcode, 2, SetReg).addReg(CallReg).addReg(CallReg);
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BB->addSuccessor(PhiMBB);
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// PhiMBB
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BB = PhiMBB;
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BuildMI(BB, PPC::PHI, 4, DestReg).addReg(ClrReg).addMBB(ClrMBB)
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.addReg(SetReg).addMBB(SetMBB);
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}
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return;
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}
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@ -2706,25 +2797,25 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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if (!SrcTy->isSigned()) {
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ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000000p52);
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unsigned ConstF = getReg(CFP, BB, IP);
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BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
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BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
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addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
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ValueFrameIdx);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(SrcReg),
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addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(SrcReg),
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ValueFrameIdx, 4);
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addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
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BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
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addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
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BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
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} else {
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ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000008p52);
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unsigned ConstF = getReg(CFP, BB, IP);
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unsigned TempLo = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
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BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
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addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
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ValueFrameIdx);
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BuildMI(*BB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
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addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(TempLo),
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BuildMI(*MBB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
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addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(TempLo),
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ValueFrameIdx, 4);
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addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
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BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
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addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
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BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
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}
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return;
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}
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@ -2754,8 +2845,8 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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unsigned TempReg = makeAnotherReg(Type::DoubleTy);
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// Convert to integer in the FP reg and store it to a stack slot
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BuildMI(*BB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
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addFrameReference(BuildMI(*BB, IP, PPC::STFD, 3)
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BuildMI(*MBB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
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addFrameReference(BuildMI(*MBB, IP, PPC::STFD, 3)
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.addReg(TempReg), ValueFrameIdx);
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// There is no load signed byte opcode, so we must emit a sign extend for
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@ -2763,13 +2854,13 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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// correct offset.
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if (DestClass == cByte) {
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unsigned TempReg2 = makeAnotherReg(DestTy);
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addFrameReference(BuildMI(*BB, IP, PPC::LBZ, 2, TempReg2),
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addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, TempReg2),
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ValueFrameIdx, 7);
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BuildMI(*BB, IP, PPC::EXTSB, 1, DestReg).addReg(TempReg2);
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BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(TempReg2);
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} else {
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int offset = (DestClass == cShort) ? 6 : 4;
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unsigned LoadOp = (DestClass == cShort) ? PPC::LHA : PPC::LWZ;
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addFrameReference(BuildMI(*BB, IP, LoadOp, 2, DestReg),
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addFrameReference(BuildMI(*MBB, IP, LoadOp, 2, DestReg),
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ValueFrameIdx, offset);
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}
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} else {
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@ -2800,34 +2891,34 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
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// Convert from floating point to unsigned 32-bit value
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// Use 0 if incoming value is < 0.0
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BuildMI(*BB, IP, PPC::FSEL, 3, UseZero).addReg(SrcReg).addReg(SrcReg)
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BuildMI(*MBB, IP, PPC::FSEL, 3, UseZero).addReg(SrcReg).addReg(SrcReg)
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.addReg(Zero);
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// Use 2**32 - 1 if incoming value is >= 2**32
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BuildMI(*BB, IP, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(SrcReg);
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BuildMI(*BB, IP, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt)
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BuildMI(*MBB, IP, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(SrcReg);
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BuildMI(*MBB, IP, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt)
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.addReg(UseZero).addReg(MaxInt);
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// Subtract 2**31
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BuildMI(*BB, IP, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
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BuildMI(*MBB, IP, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
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// Use difference if >= 2**31
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BuildMI(*BB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice)
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BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice)
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.addReg(Border);
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BuildMI(*BB, IP, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
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BuildMI(*MBB, IP, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
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.addReg(UseChoice);
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// Convert to integer
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BuildMI(*BB, IP, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
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addFrameReference(BuildMI(*BB, IP, PPC::STFD, 3).addReg(ConvReg),
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BuildMI(*MBB, IP, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
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addFrameReference(BuildMI(*MBB, IP, PPC::STFD, 3).addReg(ConvReg),
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FrameIdx);
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if (DestClass == cByte) {
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addFrameReference(BuildMI(*BB, IP, PPC::LBZ, 2, DestReg),
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addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, DestReg),
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FrameIdx, 7);
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} else if (DestClass == cShort) {
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addFrameReference(BuildMI(*BB, IP, PPC::LHZ, 2, DestReg),
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addFrameReference(BuildMI(*MBB, IP, PPC::LHZ, 2, DestReg),
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FrameIdx, 6);
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} if (DestClass == cInt) {
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addFrameReference(BuildMI(*BB, IP, PPC::LWZ, 2, IntTmp),
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addFrameReference(BuildMI(*MBB, IP, PPC::LWZ, 2, IntTmp),
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FrameIdx, 4);
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BuildMI(*BB, IP, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
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BuildMI(*BB, IP, PPC::B, 1).addMBB(XorMBB);
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BuildMI(*MBB, IP, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
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BuildMI(*MBB, IP, PPC::B, 1).addMBB(XorMBB);
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// XorMBB:
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// add 2**31 if input was >= 2**31
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@ -47,6 +47,7 @@ def SUBI : DForm_2<"subi", 14, 0, 0>;
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def LI : DForm_2_r0<"li", 14, 0, 0>;
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def LIS : DForm_2_r0<"lis", 15, 0, 0>;
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def ADDIC : DForm_2<"addic", 12, 0, 0>;
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def ADDICo : DForm_2<"addic.", 13, 0, 0>;
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def ADD : XOForm_1<"add", 31, 266, 0, 0, 0, 0>;
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def ADDC : XOForm_1<"addc", 31, 10, 0, 0, 0, 0>;
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def ADDE : XOForm_1<"adde", 31, 138, 0, 0, 0, 0>;
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@ -1,28 +1,10 @@
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TODO:
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* switch to auto-generated asm writer
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* use stfiwx in float->int
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* implement cast fp to bool
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* implement algebraic shift right long by reg
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* implement scheduling info
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* implement powerpc-64 for darwin
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* implement powerpc-64 for aix
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* fix rlwimi generation to be use-and-def
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* fix ulong to double:
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floatdidf assumes signed longs. so if the high but of a ulong
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just happens to be set, you get the wrong sign. The fix for this
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is to call cmpdi2 to compare against zero, if so shift right by one,
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convert to fp, and multiply by (add to itself). the sequence would
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look like:
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{r3:r4} holds ulong a;
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li r5, 0
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li r6, 0 (set r5:r6 to ulong 0)
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call cmpdi2 ==> sets r3 <, =, > 0
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if r3 > 0
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call floatdidf as usual
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else
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shift right ulong a, 1 (we could use emitShift)
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call floatdidf
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fadd f1, f1, f1 (fp left shift by 1)
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* cast elimination pass (uint -> sbyte -> short, kill the byte -> short)
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* should hint to the branch select pass that it doesn't need to print the
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second unconditional branch, so we don't end up with things like:
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b .LBBl42__2E_expand_function_8_674 ; loopentry.24
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@ -30,9 +12,6 @@ TODO:
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b .LBBl42__2E_expand_function_8_42 ; NewDefault
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Currently failing tests that should pass:
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* SingleSource
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`- Regression
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| `- casts (ulong to fp failure)
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* MultiSource
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|- Applications
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| `- hbd: miscompilation
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