forked from OSchip/llvm-project
[VE][NFC] Split up lowering init
Split up the monolithic VETargetLowering ctor into three initialization phases: 1. initRegisterClasses() 2. initSPUActions() 3. // TODO initVPUActions() Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D90463
This commit is contained in:
Simon Moll
parent
790f5771fd
commit
4474d4d49c
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@ -49,6 +49,219 @@ bool VETargetLowering::CanLowerReturn(
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return CCInfo.CheckReturn(Outs, RetCC);
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}
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void VETargetLowering::initRegisterClasses() {
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// Set up the register classes.
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addRegisterClass(MVT::i32, &VE::I32RegClass);
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addRegisterClass(MVT::i64, &VE::I64RegClass);
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addRegisterClass(MVT::f32, &VE::F32RegClass);
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addRegisterClass(MVT::f64, &VE::I64RegClass);
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addRegisterClass(MVT::f128, &VE::F128RegClass);
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addRegisterClass(MVT::v2i32, &VE::V64RegClass);
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addRegisterClass(MVT::v4i32, &VE::V64RegClass);
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addRegisterClass(MVT::v8i32, &VE::V64RegClass);
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addRegisterClass(MVT::v16i32, &VE::V64RegClass);
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addRegisterClass(MVT::v32i32, &VE::V64RegClass);
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addRegisterClass(MVT::v64i32, &VE::V64RegClass);
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addRegisterClass(MVT::v128i32, &VE::V64RegClass);
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addRegisterClass(MVT::v256i32, &VE::V64RegClass);
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addRegisterClass(MVT::v512i32, &VE::V64RegClass);
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addRegisterClass(MVT::v2i64, &VE::V64RegClass);
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addRegisterClass(MVT::v4i64, &VE::V64RegClass);
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addRegisterClass(MVT::v8i64, &VE::V64RegClass);
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addRegisterClass(MVT::v16i64, &VE::V64RegClass);
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addRegisterClass(MVT::v32i64, &VE::V64RegClass);
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addRegisterClass(MVT::v64i64, &VE::V64RegClass);
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addRegisterClass(MVT::v128i64, &VE::V64RegClass);
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addRegisterClass(MVT::v256i64, &VE::V64RegClass);
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addRegisterClass(MVT::v2f32, &VE::V64RegClass);
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addRegisterClass(MVT::v4f32, &VE::V64RegClass);
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addRegisterClass(MVT::v8f32, &VE::V64RegClass);
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addRegisterClass(MVT::v16f32, &VE::V64RegClass);
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addRegisterClass(MVT::v32f32, &VE::V64RegClass);
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addRegisterClass(MVT::v64f32, &VE::V64RegClass);
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addRegisterClass(MVT::v128f32, &VE::V64RegClass);
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addRegisterClass(MVT::v256f32, &VE::V64RegClass);
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addRegisterClass(MVT::v512f32, &VE::V64RegClass);
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addRegisterClass(MVT::v2f64, &VE::V64RegClass);
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addRegisterClass(MVT::v4f64, &VE::V64RegClass);
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addRegisterClass(MVT::v8f64, &VE::V64RegClass);
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addRegisterClass(MVT::v16f64, &VE::V64RegClass);
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addRegisterClass(MVT::v32f64, &VE::V64RegClass);
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addRegisterClass(MVT::v64f64, &VE::V64RegClass);
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addRegisterClass(MVT::v128f64, &VE::V64RegClass);
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addRegisterClass(MVT::v256f64, &VE::V64RegClass);
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addRegisterClass(MVT::v256i1, &VE::VMRegClass);
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addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
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}
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void VETargetLowering::initSPUActions() {
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const auto &TM = getTargetMachine();
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/// Load & Store {
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// VE doesn't have i1 sign extending load.
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for (MVT VT : MVT::integer_valuetypes()) {
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
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setTruncStoreAction(VT, MVT::i1, Expand);
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}
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// VE doesn't have floating point extload/truncstore, so expand them.
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for (MVT FPVT : MVT::fp_valuetypes()) {
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for (MVT OtherFPVT : MVT::fp_valuetypes()) {
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setLoadExtAction(ISD::EXTLOAD, FPVT, OtherFPVT, Expand);
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setTruncStoreAction(FPVT, OtherFPVT, Expand);
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}
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}
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// VE doesn't have fp128 load/store, so expand them in custom lower.
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setOperationAction(ISD::LOAD, MVT::f128, Custom);
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setOperationAction(ISD::STORE, MVT::f128, Custom);
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/// } Load & Store
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// Custom legalize address nodes into LO/HI parts.
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MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
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setOperationAction(ISD::BlockAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
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setOperationAction(ISD::ConstantPool, PtrVT, Custom);
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/// VAARG handling {
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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// VAARG needs to be lowered to access with 8 bytes alignment.
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setOperationAction(ISD::VAARG, MVT::Other, Custom);
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// Use the default implementation.
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setOperationAction(ISD::VACOPY, MVT::Other, Expand);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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/// } VAARG handling
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/// Stack {
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
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/// } Stack
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/// Branch {
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// VE doesn't have BRCOND
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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// BRIND and BR_JT are not implemented yet.
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// FIXME: Implement both for the scalar perforamnce.
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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/// } Branch
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/// Int Ops {
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for (MVT IntVT : {MVT::i32, MVT::i64}) {
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// VE has no REM or DIVREM operations.
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setOperationAction(ISD::UREM, IntVT, Expand);
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setOperationAction(ISD::SREM, IntVT, Expand);
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setOperationAction(ISD::SDIVREM, IntVT, Expand);
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setOperationAction(ISD::UDIVREM, IntVT, Expand);
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// VE has no SHL_PARTS/SRA_PARTS/SRL_PARTS operations.
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setOperationAction(ISD::SHL_PARTS, IntVT, Expand);
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setOperationAction(ISD::SRA_PARTS, IntVT, Expand);
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setOperationAction(ISD::SRL_PARTS, IntVT, Expand);
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// VE has no MULHU/S or U/SMUL_LOHI operations.
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// TODO: Use MPD instruction to implement SMUL_LOHI for i32 type.
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setOperationAction(ISD::MULHU, IntVT, Expand);
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setOperationAction(ISD::MULHS, IntVT, Expand);
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setOperationAction(ISD::UMUL_LOHI, IntVT, Expand);
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setOperationAction(ISD::SMUL_LOHI, IntVT, Expand);
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// VE has no CTTZ, ROTL, ROTR operations.
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setOperationAction(ISD::CTTZ, IntVT, Expand);
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setOperationAction(ISD::ROTL, IntVT, Expand);
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setOperationAction(ISD::ROTR, IntVT, Expand);
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// VE has 64 bits instruction which works as i64 BSWAP operation. This
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// instruction works fine as i32 BSWAP operation with an additional
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// parameter. Use isel patterns to lower BSWAP.
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setOperationAction(ISD::BSWAP, IntVT, Legal);
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// VE has only 64 bits instructions which work as i64 BITREVERSE/CTLZ/CTPOP
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// operations. Use isel patterns for i64, promote for i32.
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LegalizeAction Act = (IntVT == MVT::i32) ? Promote : Legal;
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setOperationAction(ISD::BITREVERSE, IntVT, Act);
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setOperationAction(ISD::CTLZ, IntVT, Act);
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, IntVT, Act);
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setOperationAction(ISD::CTPOP, IntVT, Act);
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// VE has only 64 bits instructions which work as i64 AND/OR/XOR operations.
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// Use isel patterns for i64, promote for i32.
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setOperationAction(ISD::AND, IntVT, Act);
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setOperationAction(ISD::OR, IntVT, Act);
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setOperationAction(ISD::XOR, IntVT, Act);
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}
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/// } Int Ops
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/// Conversion {
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// VE doesn't have instructions for fp<->uint, so expand them by llvm
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); // use i64
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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// fp16 not supported
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for (MVT FPVT : MVT::fp_valuetypes()) {
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setOperationAction(ISD::FP16_TO_FP, FPVT, Expand);
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setOperationAction(ISD::FP_TO_FP16, FPVT, Expand);
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}
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/// } Conversion
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/// Floating-point Ops {
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/// Note: Floating-point operations are fneg, fadd, fsub, fmul, fdiv, frem,
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/// and fcmp.
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// VE doesn't have following floating point operations.
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for (MVT VT : MVT::fp_valuetypes()) {
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setOperationAction(ISD::FNEG, VT, Expand);
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setOperationAction(ISD::FREM, VT, Expand);
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}
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// VE doesn't have fdiv of f128.
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setOperationAction(ISD::FDIV, MVT::f128, Expand);
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for (MVT FPVT : {MVT::f32, MVT::f64}) {
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// f32 and f64 uses ConstantFP. f128 uses ConstantPool.
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setOperationAction(ISD::ConstantFP, FPVT, Legal);
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}
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/// } Floating-point Ops
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/// Floating-point math functions {
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// VE doesn't have following floating point math functions.
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for (MVT VT : MVT::fp_valuetypes()) {
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setOperationAction(ISD::FABS, VT, Expand);
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setOperationAction(ISD::FCOPYSIGN, VT, Expand);
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setOperationAction(ISD::FCOS, VT, Expand);
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setOperationAction(ISD::FSIN, VT, Expand);
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setOperationAction(ISD::FSQRT, VT, Expand);
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}
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/// } Floating-point math functions
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/// Atomic instructions {
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setMaxAtomicSizeInBitsSupported(64);
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setMinCmpXchgSizeInBits(32);
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setSupportsUnalignedAtomics(false);
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// Use custom inserter for ATOMIC_FENCE.
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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/// } Atomic isntructions
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}
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SDValue
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VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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@ -627,213 +840,9 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
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setBooleanContents(ZeroOrOneBooleanContent);
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setBooleanVectorContents(ZeroOrOneBooleanContent);
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// Set up the register classes.
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addRegisterClass(MVT::i32, &VE::I32RegClass);
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addRegisterClass(MVT::i64, &VE::I64RegClass);
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addRegisterClass(MVT::f32, &VE::F32RegClass);
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addRegisterClass(MVT::f64, &VE::I64RegClass);
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addRegisterClass(MVT::f128, &VE::F128RegClass);
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addRegisterClass(MVT::v2i32, &VE::V64RegClass);
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addRegisterClass(MVT::v4i32, &VE::V64RegClass);
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addRegisterClass(MVT::v8i32, &VE::V64RegClass);
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addRegisterClass(MVT::v16i32, &VE::V64RegClass);
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addRegisterClass(MVT::v32i32, &VE::V64RegClass);
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addRegisterClass(MVT::v64i32, &VE::V64RegClass);
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addRegisterClass(MVT::v128i32, &VE::V64RegClass);
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addRegisterClass(MVT::v256i32, &VE::V64RegClass);
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addRegisterClass(MVT::v512i32, &VE::V64RegClass);
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addRegisterClass(MVT::v2i64, &VE::V64RegClass);
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addRegisterClass(MVT::v4i64, &VE::V64RegClass);
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addRegisterClass(MVT::v8i64, &VE::V64RegClass);
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addRegisterClass(MVT::v16i64, &VE::V64RegClass);
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addRegisterClass(MVT::v32i64, &VE::V64RegClass);
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addRegisterClass(MVT::v64i64, &VE::V64RegClass);
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addRegisterClass(MVT::v128i64, &VE::V64RegClass);
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addRegisterClass(MVT::v256i64, &VE::V64RegClass);
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addRegisterClass(MVT::v2f32, &VE::V64RegClass);
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addRegisterClass(MVT::v4f32, &VE::V64RegClass);
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addRegisterClass(MVT::v8f32, &VE::V64RegClass);
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addRegisterClass(MVT::v16f32, &VE::V64RegClass);
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addRegisterClass(MVT::v32f32, &VE::V64RegClass);
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addRegisterClass(MVT::v64f32, &VE::V64RegClass);
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addRegisterClass(MVT::v128f32, &VE::V64RegClass);
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addRegisterClass(MVT::v256f32, &VE::V64RegClass);
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addRegisterClass(MVT::v512f32, &VE::V64RegClass);
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addRegisterClass(MVT::v2f64, &VE::V64RegClass);
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addRegisterClass(MVT::v4f64, &VE::V64RegClass);
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addRegisterClass(MVT::v8f64, &VE::V64RegClass);
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addRegisterClass(MVT::v16f64, &VE::V64RegClass);
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addRegisterClass(MVT::v32f64, &VE::V64RegClass);
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addRegisterClass(MVT::v64f64, &VE::V64RegClass);
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addRegisterClass(MVT::v128f64, &VE::V64RegClass);
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addRegisterClass(MVT::v256f64, &VE::V64RegClass);
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addRegisterClass(MVT::v256i1, &VE::VMRegClass);
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addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
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/// Load & Store {
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// VE doesn't have i1 sign extending load.
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for (MVT VT : MVT::integer_valuetypes()) {
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
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setTruncStoreAction(VT, MVT::i1, Expand);
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}
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// VE doesn't have floating point extload/truncstore, so expand them.
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for (MVT FPVT : MVT::fp_valuetypes()) {
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for (MVT OtherFPVT : MVT::fp_valuetypes()) {
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setLoadExtAction(ISD::EXTLOAD, FPVT, OtherFPVT, Expand);
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setTruncStoreAction(FPVT, OtherFPVT, Expand);
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}
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}
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// VE doesn't have fp128 load/store, so expand them in custom lower.
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setOperationAction(ISD::LOAD, MVT::f128, Custom);
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setOperationAction(ISD::STORE, MVT::f128, Custom);
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/// } Load & Store
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// Custom legalize address nodes into LO/HI parts.
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MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
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setOperationAction(ISD::BlockAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
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setOperationAction(ISD::ConstantPool, PtrVT, Custom);
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/// VAARG handling {
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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// VAARG needs to be lowered to access with 8 bytes alignment.
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setOperationAction(ISD::VAARG, MVT::Other, Custom);
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// Use the default implementation.
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setOperationAction(ISD::VACOPY, MVT::Other, Expand);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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/// } VAARG handling
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/// Stack {
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
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/// } Stack
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/// Branch {
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// VE doesn't have BRCOND
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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// BRIND and BR_JT are not implemented yet.
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// FIXME: Implement both for the scalar perforamnce.
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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/// } Branch
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/// Int Ops {
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for (MVT IntVT : {MVT::i32, MVT::i64}) {
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// VE has no REM or DIVREM operations.
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setOperationAction(ISD::UREM, IntVT, Expand);
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setOperationAction(ISD::SREM, IntVT, Expand);
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setOperationAction(ISD::SDIVREM, IntVT, Expand);
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setOperationAction(ISD::UDIVREM, IntVT, Expand);
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// VE has no SHL_PARTS/SRA_PARTS/SRL_PARTS operations.
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setOperationAction(ISD::SHL_PARTS, IntVT, Expand);
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setOperationAction(ISD::SRA_PARTS, IntVT, Expand);
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setOperationAction(ISD::SRL_PARTS, IntVT, Expand);
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// VE has no MULHU/S or U/SMUL_LOHI operations.
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// TODO: Use MPD instruction to implement SMUL_LOHI for i32 type.
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setOperationAction(ISD::MULHU, IntVT, Expand);
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setOperationAction(ISD::MULHS, IntVT, Expand);
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setOperationAction(ISD::UMUL_LOHI, IntVT, Expand);
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setOperationAction(ISD::SMUL_LOHI, IntVT, Expand);
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// VE has no CTTZ, ROTL, ROTR operations.
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setOperationAction(ISD::CTTZ, IntVT, Expand);
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setOperationAction(ISD::ROTL, IntVT, Expand);
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setOperationAction(ISD::ROTR, IntVT, Expand);
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// VE has 64 bits instruction which works as i64 BSWAP operation. This
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// instruction works fine as i32 BSWAP operation with an additional
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// parameter. Use isel patterns to lower BSWAP.
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setOperationAction(ISD::BSWAP, IntVT, Legal);
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// VE has only 64 bits instructions which work as i64 BITREVERSE/CTLZ/CTPOP
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// operations. Use isel patterns for i64, promote for i32.
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LegalizeAction Act = (IntVT == MVT::i32) ? Promote : Legal;
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setOperationAction(ISD::BITREVERSE, IntVT, Act);
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setOperationAction(ISD::CTLZ, IntVT, Act);
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, IntVT, Act);
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setOperationAction(ISD::CTPOP, IntVT, Act);
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// VE has only 64 bits instructions which work as i64 AND/OR/XOR operations.
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// Use isel patterns for i64, promote for i32.
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setOperationAction(ISD::AND, IntVT, Act);
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setOperationAction(ISD::OR, IntVT, Act);
|
||||
setOperationAction(ISD::XOR, IntVT, Act);
|
||||
}
|
||||
/// } Int Ops
|
||||
|
||||
/// Conversion {
|
||||
// VE doesn't have instructions for fp<->uint, so expand them by llvm
|
||||
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); // use i64
|
||||
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64
|
||||
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
|
||||
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
|
||||
|
||||
// fp16 not supported
|
||||
for (MVT FPVT : MVT::fp_valuetypes()) {
|
||||
setOperationAction(ISD::FP16_TO_FP, FPVT, Expand);
|
||||
setOperationAction(ISD::FP_TO_FP16, FPVT, Expand);
|
||||
}
|
||||
/// } Conversion
|
||||
|
||||
/// Floating-point Ops {
|
||||
/// Note: Floating-point operations are fneg, fadd, fsub, fmul, fdiv, frem,
|
||||
/// and fcmp.
|
||||
|
||||
// VE doesn't have following floating point operations.
|
||||
for (MVT VT : MVT::fp_valuetypes()) {
|
||||
setOperationAction(ISD::FNEG, VT, Expand);
|
||||
setOperationAction(ISD::FREM, VT, Expand);
|
||||
}
|
||||
|
||||
// VE doesn't have fdiv of f128.
|
||||
setOperationAction(ISD::FDIV, MVT::f128, Expand);
|
||||
|
||||
for (MVT FPVT : {MVT::f32, MVT::f64}) {
|
||||
// f32 and f64 uses ConstantFP. f128 uses ConstantPool.
|
||||
setOperationAction(ISD::ConstantFP, FPVT, Legal);
|
||||
}
|
||||
/// } Floating-point Ops
|
||||
|
||||
/// Floating-point math functions {
|
||||
|
||||
// VE doesn't have following floating point math functions.
|
||||
for (MVT VT : MVT::fp_valuetypes()) {
|
||||
setOperationAction(ISD::FABS, VT, Expand);
|
||||
setOperationAction(ISD::FCOPYSIGN, VT, Expand);
|
||||
setOperationAction(ISD::FCOS, VT, Expand);
|
||||
setOperationAction(ISD::FSIN, VT, Expand);
|
||||
setOperationAction(ISD::FSQRT, VT, Expand);
|
||||
}
|
||||
|
||||
/// } Floating-point math functions
|
||||
|
||||
/// Atomic instructions {
|
||||
|
||||
setMaxAtomicSizeInBitsSupported(64);
|
||||
setMinCmpXchgSizeInBits(32);
|
||||
setSupportsUnalignedAtomics(false);
|
||||
|
||||
// Use custom inserter for ATOMIC_FENCE.
|
||||
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
|
||||
|
||||
/// } Atomic isntructions
|
||||
initRegisterClasses();
|
||||
initSPUActions();
|
||||
// TODO initVPUActions();
|
||||
|
||||
setStackPointerRegisterToSaveRestore(VE::SX11);
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,10 @@ enum NodeType : unsigned {
|
|||
class VETargetLowering : public TargetLowering {
|
||||
const VESubtarget *Subtarget;
|
||||
|
||||
void initRegisterClasses();
|
||||
void initSPUActions();
|
||||
// TODO void initVPUActions();
|
||||
|
||||
public:
|
||||
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue