From 446f3e2084e026115f498717be7eb13ad69ee912 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 15 Dec 2017 19:01:49 +0000 Subject: [PATCH] [X86] Remove the 'Requires' In64BitMode/Not64BitMode from the LWP instructions. These aren't doing anything due to a top level "let Predicates =". I think the GR32/GR64 register class protects these anyway. llvm-svn: 320844 --- llvm/lib/Target/X86/X86InstrInfo.td | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 54231662808e..c2aca53a2d47 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -2571,17 +2571,17 @@ let Predicates = [HasLWP], SchedRW = [WriteSystem] in { def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", [(int_x86_llwpcb GR32:$src)], IIC_LWP>, - XOP, XOP9, Requires<[Not64BitMode]>; + XOP, XOP9; def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", [(set GR32:$dst, (int_x86_slwpcb))], IIC_LWP>, - XOP, XOP9, Requires<[Not64BitMode]>; + XOP, XOP9; def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", [(int_x86_llwpcb GR64:$src)], IIC_LWP>, - XOP, XOP9, VEX_W, Requires<[In64BitMode]>; + XOP, XOP9, VEX_W; def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", [(set GR64:$dst, (int_x86_slwpcb))], IIC_LWP>, - XOP, XOP9, VEX_W, Requires<[In64BitMode]>; + XOP, XOP9, VEX_W; multiclass lwpins_intr { def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),