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[X86] Remove the 'Requires' In64BitMode/Not64BitMode from the LWP instructions. 

These aren't doing anything due to a top level "let Predicates =". I think the GR32/GR64 register class protects these anyway.

llvm-svn: 320844
This commit is contained in:
Craig Topper 2017-12-15 19:01:49 +00:00
parent 365e8aa5d5
commit 446f3e2084
1 changed files with 4 additions and 4 deletions
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8
llvm/lib/Target/X86/X86InstrInfo.td
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@ -2571,17 +2571,17 @@ let Predicates = [HasLWP], SchedRW = [WriteSystem] in {
def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src",
[(int_x86_llwpcb GR32:$src)], IIC_LWP>,
XOP, XOP9, Requires<[Not64BitMode]>;
XOP, XOP9;
def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst",
[(set GR32:$dst, (int_x86_slwpcb))], IIC_LWP>,
XOP, XOP9, Requires<[Not64BitMode]>;
XOP, XOP9;
def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src",
[(int_x86_llwpcb GR64:$src)], IIC_LWP>,
XOP, XOP9, VEX_W, Requires<[In64BitMode]>;
XOP, XOP9, VEX_W;
def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst",
[(set GR64:$dst, (int_x86_slwpcb))], IIC_LWP>,
XOP, XOP9, VEX_W, Requires<[In64BitMode]>;
XOP, XOP9, VEX_W;
multiclass lwpins_intr<RegisterClass RC> {
def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),