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Fixing Intel format of the vshufpd instruction. 

Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759

llvm-svn: 191481
This commit is contained in:
Yunzhong Gao 2013-09-27 01:44:23 +00:00
parent 333d28a0bb
commit 4467f33e3c
3 changed files with 7 additions and 2 deletions
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4
llvm/lib/Target/X86/X86InstrSSE.td
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@ -2553,10 +2553,10 @@ defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
"shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
let Constraints = "$src1 = $dst" in {

3
llvm/test/MC/Disassembler/X86/intel-syntax.txt
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@ -105,6 +105,9 @@
# CHECK: retf
0x66 0xcb
# CHECK: vshufpd xmm0, xmm1, xmm2, 1
0xc5 0xf1 0xc6 0xc2 0x01
# CHECK: vpgatherqq ymm2, qword ptr [rdi + 2*ymm1], ymm0
0xc4 0xe2 0xfd 0x91 0x14 0x4f

2
llvm/test/MC/X86/intel-syntax.s
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@ -69,6 +69,8 @@ _main:
mov QWORD PTR FS:320, RAX
// CHECK: movq %rax, %fs:20(%rbx)
mov QWORD PTR FS:20[rbx], RAX
// CHECK: vshufpd $1, %xmm2, %xmm1, %xmm0
vshufpd XMM0, XMM1, XMM2, 1
// CHECK: vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm1
vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
// CHECK: movsd -8, %xmm5