forked from OSchip/llvm-project
parent
4a744e5c9d
commit
4464383a17
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@ -52,8 +52,6 @@ Missing intrinsics:
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ds*
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mf*
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vavg*
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vmax*
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vmin*
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vmladduhm
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vmr*
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vsel (some aliases only accessible using builtins)
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@ -64,6 +62,19 @@ FABS/FNEG can be codegen'd with the appropriate and/xor of -0.0.
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//===----------------------------------------------------------------------===//
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Codegen the constant here with something better than a constant pool load.
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void %test_f(<4 x float>* %P, <4 x float>* %Q, float %X) {
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%tmp = load <4 x float>* %Q
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%tmp = cast <4 x float> %tmp to <4 x int>
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%tmp1 = and <4 x int> %tmp, < int 2147483647, int 2147483647, int 2147483647, int 2147483647 >
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%tmp2 = cast <4 x int> %tmp1 to <4 x float>
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store <4 x float> %tmp2, <4 x float>* %P
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ret void
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}
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//===----------------------------------------------------------------------===//
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For functions that use altivec AND have calls, we are VRSAVE'ing all call
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clobbered regs.
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