forked from OSchip/llvm-project
Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
llvm-svn: 192566
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@ -6053,6 +6053,13 @@ defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
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/// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
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multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
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let isCodeGenOnly = 1, hasSideEffects = 0 in
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def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
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(ins VR128:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, OpSize;
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let neverHasSideEffects = 1, mayStore = 1 in
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def mr : SS4AIi8<opc, MRMDestMem, (outs),
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(ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
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@ -235,3 +235,9 @@
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# CHECK: movd %xmm0, %rax
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0x66 0x48 0x0f 0x7e 0xc0
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# CHECK: pextrw $3, %xmm3, %ecx
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0x66 0x0f 0x3a 0x15 0xd9 0x03
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# CHECK: pextrw $3, %xmm3, (%rax)
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0x66 0x0f 0x3a 0x15 0x18 0x03
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