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[X86][Haswell] Strip unnecessary WriteFAdd/WriteFHAdd instruction instrw overrides. 

llvm-svn: 330514
This commit is contained in:
Simon Pilgrim 2018-04-21 16:20:28 +00:00
parent a80df0999f
commit 44278f6598
1 changed files with 2 additions and 16 deletions
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18
llvm/lib/Target/X86/X86SchedHaswell.td
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@ -1582,19 +1582,9 @@ def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr",
"PEXT(32|64)rr",
"SHLD(16|32|64)rri8",
"SHRD(16|32|64)rri8",
"(V?)ADDPD(Y?)rr",
"(V?)ADDPS(Y?)rr",
"(V?)ADDSDrr",
"(V?)ADDSSrr",
"(V?)ADDSUBPD(Y?)rr",
"(V?)ADDSUBPS(Y?)rr",
"(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr",
"(V?)CVTTPS2DQ(Y?)rr",
"(V?)SUBPD(Y?)rr",
"(V?)SUBPS(Y?)rr",
"(V?)SUBSDrr",
"(V?)SUBSSrr")>;
"(V?)CVTTPS2DQ(Y?)rr")>;
def HWWriteResGroup50_16i : SchedWriteRes<[HWPort1, HWPort0156]> {
let Latency = 4;
@ -2227,11 +2217,7 @@ def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> {
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr",
"(V?)HADDPD(Y?)rr",
"(V?)HADDPS(Y?)rr",
"(V?)HSUBPD(Y?)rr",
"(V?)HSUBPS(Y?)rr")>;
def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>;
def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {
let Latency = 5;