From 43e4367961958fa973677f3464f796371f04070b Mon Sep 17 00:00:00 2001
From: Luke Geeson <luke.geeson@arm.com>
Date: Mon, 4 Jun 2018 09:41:32 +0000
Subject: [PATCH] [AArch64] Audit on rL333634 to fix FP16 Disasm BitPatterns

llvm-svn: 333879
---
 llvm/lib/Target/AArch64/AArch64InstrFormats.td | 3 ++-
 llvm/lib/Target/AArch64/AArch64InstrInfo.td    | 1 -
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 861cdc8109cb..69a5f849833c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -7928,9 +7928,10 @@ multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> {
     let Inst{19-16} = imm{3-0};
     let Inst{23-22} = 0b11;
   }
-  def SHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
+  def SHr : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
                                 FPR32, FPR16, vecshiftR32, asm, []> {
     let Inst{19-16} = imm{3-0};
+    let Inst{22-21} = 0b01;
   }
   def HDr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
                                 FPR16, FPR64, vecshiftR32, asm, []> {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index ac7bc9873c5a..b9d88fc87b3c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4984,7 +4984,6 @@ def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
           (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
 
-
 defm SHL      : SIMDScalarLShiftD<   0, 0b01010, "shl", AArch64vshl>;
 defm SLI      : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
 defm SQRSHRN  : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",