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Bug 18149: [AArch32] VSel instructions has no ARMCC field 

The current peephole optimizing for compare inst assumes an instr that
uses CPSR has an MO for ARM Cond code.However, for VSEL instructions
(vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do
they support the modification of Cond Code.

llvm-svn: 196588
This commit is contained in:
Weiming Zhao 2013-12-06 17:56:48 +00:00
parent 028ed91127
commit 43d8e6cb3b
2 changed files with 94 additions and 7 deletions
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41
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -2374,8 +2374,32 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
isSafe = true;
break;
}
// Condition code is after the operand before CPSR.
ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
// Condition code is after the operand before CPSR except for VSELs.
ARMCC::CondCodes CC;
bool IsInstrVSel = true;
switch (Instr.getOpcode()) {
default:
IsInstrVSel = false;
CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
break;
case ARM::VSELEQD:
case ARM::VSELEQS:
CC = ARMCC::EQ;
break;
case ARM::VSELGTD:
case ARM::VSELGTS:
CC = ARMCC::GT;
break;
case ARM::VSELGED:
case ARM::VSELGES:
CC = ARMCC::GE;
break;
case ARM::VSELVSS:
case ARM::VSELVSD:
CC = ARMCC::VS;
break;
}
if (Sub) {
ARMCC::CondCodes NewCC = getSwappedCondition(CC);
if (NewCC == ARMCC::AL)
@ -2386,11 +2410,14 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
// If it is safe to remove CmpInstr, the condition code of these
// operands will be modified.
if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
Sub->getOperand(2).getReg() == SrcReg)
OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
NewCC));
}
else
Sub->getOperand(2).getReg() == SrcReg) {
// VSel doesn't support condition code update.
if (IsInstrVSel)
return false;
OperandsToUpdate.push_back(
std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
}
} else
switch (CC) {
default:
// CPSR can be used multiple times, we should continue.

60
llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
View File

@ -1,4 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8
define i32 @f(i32 %a, i32 %b) nounwind ssp {
entry:
@ -84,3 +87,60 @@ land.lhs.true: ; preds = %num2long.exit
if.end11: ; preds = %num2long.exit
ret i32 23
}
define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
entry:
; CHECK-LABEL: float_sel:
; CHECK-NOT: cmp
; V8-LABEL: float_sel:
; V8-NOT: cmp
; V8: vseleq.f32
%sub = sub i32 %a, %b
%cmp = icmp eq i32 %sub, 0
%ret = select i1 %cmp, float %x, float %y
ret float %ret
}
define double @double_sel(i32 %a, i32 %b, double %x, double %y) {
entry:
; CHECK-LABEL: double_sel:
; CHECK-NOT: cmp
; V8-LABEL: double_sel:
; V8-NOT: cmp
; V8: vseleq.f64
%sub = sub i32 %a, %b
%cmp = icmp eq i32 %sub, 0
%ret = select i1 %cmp, double %x, double %y
ret double %ret
}
@t = common global i32 0
define double @double_sub(i32 %a, i32 %b, double %x, double %y) {
entry:
; CHECK-LABEL: double_sub:
; CHECK: subs
; CHECK-NOT: cmp
; V8-LABEL: double_sub:
; V8: vsel
%cmp = icmp sgt i32 %a, %b
%sub = sub i32 %a, %b
store i32 %sub, i32* @t
%ret = select i1 %cmp, double %x, double %y
ret double %ret
}
define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) {
entry:
; V7-LABEL: double_sub_swap:
; V7-NOT: cmp
; V7: subs
; V8-LABEL: double_sub_swap:
; V8-NOT: subs
; V8: cmp
; V8: vsel
%cmp = icmp sgt i32 %a, %b
%sub = sub i32 %b, %a
%ret = select i1 %cmp, double %x, double %y
store i32 %sub, i32* @t
ret double %ret
}